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| User's Manual V850E/ME2 32-Bit Single-Chip Microcontroller Hardware PD703111A Document No. U16031EJ4V1UD00 (4th edition) Date Published August 2005 N CP(K) (c) Printed in Japan [MEMO] 2 User's Manual U16031EJ4V1UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U16031EJ4V1UD 3 * The information in this document is current as of August, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U16031EJ4V1UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65030 * Sucursal en Espana NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 User's Manual U16031EJ4V1UD 5 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850E/ME2 (PD703111A) to design application systems using the V850E/ME2. Purpose The purpose of this manual is for users to gain an understanding of the hardware functions of the V850E/ME2. Organization The V850E/ME2 User's Manual is divided into two parts: Hardware (this manual) and Architecture (V850E1 Architecture User's Manual). The organization of each manual is as follows: Hardware * Pin functions * CPU function * Internal peripheral functions * Electrical specifications Architecture * Data type * Register set * Instruction format and instruction set * Interrupts and exceptions * Pipeline operation How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. * To find the details of a register where the name is known Refer to APPENDIX A REGISTER INDEX. * To understand the details of an instruction function Refer to the V850E1 Architecture User's Manual. To know the electrical specifications of the V850E/ME2 Refer to CHAPTER 17 ELECTRICAL SPECIFICATIONS. * To understand the overall functions of the V850E/ME2 Read this manual according to the CONTENTS. * How to interpret the register format For a bit whose bit number is enclosed in brackets, its bit name is defined as a reserved word in the device file. The mark shows major revised points. 6 User's Manual U16031EJ4V1UD Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243 Data type: Word ... 32 bits Halfword ... 16 bits Byte ... 8 bits Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Document related to V850E/ME2 Document Name V850E1 Architecture User's Manual V850E/ME2 Hardware User's Manual V850E/ME2 Hardware Application Note V850E/ME2 USB Function Drivers Application Note V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 PCI Host Bridge Macro Application Note Document No. U14559E This manual U16794E U17069E U17121E User's Manual U16031EJ4V1UD 7 Document related to development tools (user's manuals) Document Name CA850 Ver. 3.00 C Compiler Package Operation C Language Assembly Language Link Directive PM plus Ver. 6.00 RX850 Ver. 3.13 or Later Real-Time OS Basics Installation Technical RX850 Pro Ver. 3.15 Real-Time OS Basics Installation Technical RD850 Ver. 3.01 Task Debugger RD850 Pro Ver. 3.01 Task Debugger Document No. U17293E U17291E U17292E U17294E U17178E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E 8 User's Manual U16031EJ4V1UD CONTENTS CHAPTER 1 INTRODUCTION ...............................................................................................................17 1.1 1.2 1.3 1.4 1.5 1.6 Outline........................................................................................................................................17 Features .....................................................................................................................................18 Applications...............................................................................................................................20 Ordering Information ................................................................................................................20 Pin Configuration ......................................................................................................................21 Function Blocks ........................................................................................................................26 1.6.1 1.6.2 Internal block diagram..................................................................................................................26 On-chip units................................................................................................................................27 CHAPTER 2 PIN FUNCTIONS ..............................................................................................................30 2.1 2.2 2.3 2.4 2.5 List of Pin Functions ................................................................................................................30 Pin Status...................................................................................................................................40 Description of Pin Functions ...................................................................................................42 Pin I/O Circuits and Recommended Connection of Unused Pins........................................58 Pin I/O Circuits ..........................................................................................................................63 CHAPTER 3 CPU FUNCTION...............................................................................................................64 3.1 3.2 Features .....................................................................................................................................64 CPU Register Set.......................................................................................................................65 3.2.1 3.2.2 Program register set ....................................................................................................................66 System register set ......................................................................................................................67 Operating modes .........................................................................................................................73 Operating mode specification.......................................................................................................73 CPU address space .....................................................................................................................74 Image ...........................................................................................................................................75 Wrap-around of CPU address space ...........................................................................................76 Memory map ................................................................................................................................77 Area .............................................................................................................................................78 Recommended use of address space..........................................................................................82 On-chip peripheral I/O registers ...................................................................................................84 Specific registers........................................................................................................................110 System wait control register (VSWC).........................................................................................110 Initialization sequence................................................................................................................111 Restriction on conflict between sld instruction and interrupt request..........................................113 3.3 Operating Modes.......................................................................................................................73 3.3.1 3.3.2 3.4 Address Space ..........................................................................................................................74 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 3.4.10 3.4.11 3.5 Cautions...................................................................................................................................114 CHAPTER 4 BUS CONTROL FUNCTION.........................................................................................115 4.1 4.2 Features ...................................................................................................................................115 Bus Control Pins .....................................................................................................................115 User's Manual U16031EJ4V1UD 9 4.2.1 Pin status during internal instruction RAM, internal data RAM, and on-chip peripheral I/O access..............................................................................................116 4.3 4.4 4.5 Memory Block Function......................................................................................................... 117 4.3.1 Chip select control function ........................................................................................................118 Bus Cycle Type Control Function ........................................................................................ 121 Bus Access ............................................................................................................................. 122 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 Number of access clocks ...........................................................................................................122 Bus sizing function .....................................................................................................................123 Endian control function...............................................................................................................124 Big endian method usage restrictions in NEC Electronics development tools............................125 Bus width....................................................................................................................................127 Data read control function ..........................................................................................................146 4.6 4.7 Bus Clock Control Function.................................................................................................. 151 Wait Function.......................................................................................................................... 153 4.7.1 4.7.2 4.7.3 4.7.4 Programmable wait function.......................................................................................................153 External wait function .................................................................................................................158 Relationship between programmable wait and external wait......................................................158 Bus cycles in which wait function is valid ...................................................................................159 4.8 4.9 Idle State Insertion Function................................................................................................. 160 Instruction Cache Function................................................................................................... 162 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.10.1 4.10.2 4.10.3 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5 4.11.6 Cache configuration register (BHC) ...........................................................................................162 8 KB 2-way set associative cache..............................................................................................164 LRU algorithm ............................................................................................................................164 Instruction cache control function...............................................................................................165 Tag clear function.......................................................................................................................167 Auto fill function (way 0 only)......................................................................................................168 Cautions .....................................................................................................................................168 Internal instruction RAM mode register (IRAMM).......................................................................169 Operation ...................................................................................................................................170 Cautions .....................................................................................................................................171 Function outline..........................................................................................................................172 Bus hold procedure ....................................................................................................................173 Operation in power-save mode ..................................................................................................173 Bus hold timing...........................................................................................................................174 Bus hold timing (SRAM) .............................................................................................................175 Bus hold timing (SDRAM) ..........................................................................................................178 4.10 Internal Instruction RAM Control Function ......................................................................... 169 4.11 Bus Hold Function ................................................................................................................. 172 4.12 Bus Priority Order .................................................................................................................. 182 4.13 Boundary Operation Conditions........................................................................................... 182 4.13.1 4.13.2 Program space...........................................................................................................................182 Data space .................................................................................................................................182 4.14 Timing at Which T0 State Is Not Inserted ............................................................................ 183 4.15 Cautions .................................................................................................................................. 184 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION .............................................................. 186 5.1 10 SRAM, External ROM, External I/O Interface ....................................................................... 186 User's Manual U16031EJ4V1UD 5.1.1 5.1.2 5.1.3 Features.....................................................................................................................................186 SRAM connection ......................................................................................................................187 SRAM, external ROM, external I/O access ................................................................................189 Features.....................................................................................................................................199 Page ROM connection ...............................................................................................................200 On-page/off-page judgment .......................................................................................................201 Page ROM configuration register (PRC) ....................................................................................202 Page ROM access .....................................................................................................................203 Features.....................................................................................................................................209 SDRAM connection....................................................................................................................209 Address multiplex function .........................................................................................................210 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) ...................................216 SDRAM access..........................................................................................................................219 Refresh control function .............................................................................................................243 Self-refresh control function .......................................................................................................248 SDRAM initialization sequence ..................................................................................................250 5.2 Page ROM Controller (ROMC) ...............................................................................................199 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3 SDRAM Controller (SDRAMC) ...............................................................................................209 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.4 Cautions...................................................................................................................................253 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)..................................................................254 6.1 6.2 6.3 Features ...................................................................................................................................254 Configuration...........................................................................................................................255 Control Registers ....................................................................................................................256 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 DMA source address registers 0 to 3 (DSA0 to DSA3)..............................................................256 DMA destination address registers 0 to 3 (DDA0 to DDA3) ....................................................... 258 DMA transfer count registers 0 to 3 (DBC0 to DBC3) ................................................................260 DMA addressing control registers 0 to 3 (DADC0 to DADC3).................................................... 261 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) ........................................................264 DMA terminal count output control register (DTOC) ..................................................................267 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)..............................................................268 DMA interface control register (DIFC)........................................................................................274 Single transfer mode..................................................................................................................275 Single-step transfer mode ..........................................................................................................277 Block transfer mode ...................................................................................................................278 2-cycle transfer ..........................................................................................................................279 Flyby transfer .............................................................................................................................290 Transfer type and transfer target................................................................................................302 External bus cycles during DMA transfer ...................................................................................304 6.4 Transfer Modes .......................................................................................................................275 6.4.1 6.4.2 6.4.3 6.5 Transfer Types ........................................................................................................................279 6.5.1 6.5.2 6.6 Transfer Target........................................................................................................................302 6.6.1 6.6.2 6.7 6.8 6.9 6.10 6.11 DMA Channel Priorities ..........................................................................................................304 Next Address Setting Function .............................................................................................305 DMA Transfer Start Factors ...................................................................................................307 Terminal Count Output upon DMA Transfer End ................................................................309 Forcible Interruption...............................................................................................................310 User's Manual U16031EJ4V1UD 11 6.12 6.13 6.14 6.15 Forcible Termination.............................................................................................................. 311 Times Related to DMA Transfer............................................................................................ 312 Maximum Response Time for DMA Transfer Request ....................................................... 313 Cautions .................................................................................................................................. 314 6.15.1 Interrupt factors ..........................................................................................................................317 6.16 DMA Transfer End .................................................................................................................. 317 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 318 7.1 7.2 Features .................................................................................................................................. 318 Non-Maskable Interrupts ....................................................................................................... 322 7.2.1 7.2.2 7.2.3 7.2.4 Operation ...................................................................................................................................323 Restore.......................................................................................................................................325 Non-maskable interrupt status flag (NP) ....................................................................................326 Edge detection function..............................................................................................................326 Operation ...................................................................................................................................327 Restore.......................................................................................................................................329 Priorities of maskable interrupts .................................................................................................330 Interrupt control register (xxICn).................................................................................................334 Interrupt mask registers 0 to 5 (IMR0 to IMR5) ..........................................................................337 NMI reset status register (NRS) .................................................................................................339 In-service priority register (ISPR) ...............................................................................................340 Maskable interrupt status flag (ID) .............................................................................................340 Selecting interrupt trigger mode .................................................................................................341 Operation ...................................................................................................................................356 Restore.......................................................................................................................................357 Exception status flag (EP) ..........................................................................................................358 Illegal opcode definition..............................................................................................................359 Debug trap .................................................................................................................................361 7.3 Maskable Interrupts ............................................................................................................... 327 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.4 Software Exception ................................................................................................................ 356 7.4.1 7.4.2 7.4.3 7.5 Exception Trap ....................................................................................................................... 359 7.5.1 7.5.2 7.6 7.7 7.8 7.9 Multiple Interrupt Servicing Control..................................................................................... 363 Interrupt Latency Time........................................................................................................... 365 Periods in Which CPU Does Not Acknowledge Interrupts ................................................ 366 Cautions .................................................................................................................................. 366 CHAPTER 8 CLOCK GENERATION FUNCTION............................................................................. 367 8.1 8.2 8.3 Features .................................................................................................................................. 367 Configuration.......................................................................................................................... 368 Control Registers ................................................................................................................... 368 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 Clock control register (CKC).......................................................................................................368 Clock source select register (CKS).............................................................................................373 SSCG control register (SSCGC) ................................................................................................375 USB clock control register (UCKC) ............................................................................................377 Lock register (LOCKR) ...............................................................................................................378 Oscillation stabilization time select register (OSTS)...................................................................379 8.4 12 Operation ................................................................................................................................ 380 User's Manual U16031EJ4V1UD 8.4.1 8.4.2 Operation status of each clock...................................................................................................380 Setting of input clock (FX)...........................................................................................................380 Calculating BUSCLK frequency .................................................................................................382 Calculating operating clock frequency of each on-chip peripheral function................................382 Overview ....................................................................................................................................385 Control registers.........................................................................................................................387 HALT mode................................................................................................................................390 IDLE mode .................................................................................................................................394 Software STOP mode ................................................................................................................398 Oscillation stabilization time security specification .....................................................................404 Time base counter (TBC)...........................................................................................................404 8.5 Operating Clock Provisions...................................................................................................381 8.5.1 8.5.2 8.6 Power-Save Control................................................................................................................385 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.7 Securing Oscillation Stabilization Time ...............................................................................404 8.7.1 8.7.2 8.8 Cautions...................................................................................................................................405 CHAPTER 9 TIMER/COUNTER FUNCTION ......................................................................................406 9.1 Timer C.....................................................................................................................................406 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 Features.....................................................................................................................................406 Function overview ......................................................................................................................406 Basic configuration.....................................................................................................................407 Timer C ......................................................................................................................................409 Control registers.........................................................................................................................413 Operation ...................................................................................................................................421 Application examples .................................................................................................................428 Cautions.....................................................................................................................................435 Features.....................................................................................................................................437 Function overview ......................................................................................................................437 Basic configuration.....................................................................................................................437 Timer D ......................................................................................................................................438 Control registers.........................................................................................................................441 Operation ...................................................................................................................................443 Application examples .................................................................................................................445 Cautions.....................................................................................................................................445 9.2 Timer D.....................................................................................................................................437 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.3 16-Bit 2-Phase Encoder Input Up/Down Counter/General-Purpose Timer (Timer ENC1) ...........................................................................................................................446 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 Functions ...................................................................................................................................446 Features.....................................................................................................................................446 Basic configuration.....................................................................................................................447 Timer ENC1 ...............................................................................................................................449 Control registers.........................................................................................................................451 Operation ...................................................................................................................................465 Supplementary description of internal operation ........................................................................474 Cautions.....................................................................................................................................477 CHAPTER 10 SERIAL INTERFACE FUNCTION ..............................................................................478 User's Manual U16031EJ4V1UD 13 10.1 Features .................................................................................................................................. 478 10.1.1 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 Switching between UARTB0 and CSI30 modes.........................................................................478 Features .....................................................................................................................................479 Configuration..............................................................................................................................480 Control registers.........................................................................................................................484 Interrupt requests .......................................................................................................................501 Control method...........................................................................................................................504 Operation ...................................................................................................................................507 Dedicated baud rate generators 0, 1 (BRG0, BRG1) .................................................................518 Control flow ................................................................................................................................524 Cautions .....................................................................................................................................535 Features .....................................................................................................................................537 Configuration..............................................................................................................................538 Control registers.........................................................................................................................540 Dedicated baud rate generators 0, 1 (BRG0, BRG1) .................................................................552 Operation ...................................................................................................................................554 Usage.........................................................................................................................................572 Cautions .....................................................................................................................................578 10.2 Asynchronous Serial Interfaces B0, B1 (UARTB0, UARTB1) ............................................ 479 10.3 Clocked Serial Interfaces 30, 31 (CSI30, CSI31).................................................................. 537 CHAPTER 11 USB FUNCTION CONTROLLER (USBF)................................................................. 579 11.1 Overview ................................................................................................................................. 579 11.2 Configuration.......................................................................................................................... 580 11.3 Requests ................................................................................................................................. 581 11.3.1 11.3.2 11.4.1 11.4.2 11.4.3 11.4.4 Automatic requests ....................................................................................................................581 Other requests ...........................................................................................................................588 Control registers.........................................................................................................................589 Data hold registers .....................................................................................................................642 Request data register area.........................................................................................................667 Peripheral control registers ........................................................................................................683 11.4 Register Configuration .......................................................................................................... 589 11.5 STALL Handshake or No Handshake................................................................................... 687 11.6 Register Values in Specific Status ....................................................................................... 688 11.7 FW Processing ....................................................................................................................... 690 11.7.1 11.7.2 11.7.3 11.7.4 11.7.5 11.7.6 11.7.7 11.7.8 Initialization processing ..............................................................................................................692 Interrupt servicing.......................................................................................................................695 USB main processing.................................................................................................................696 Suspend/Resume processing ....................................................................................................723 Processing after power application ............................................................................................726 Receiving data for bulk transfer (OUT) in DMA mode ................................................................729 Transmitting data for bulk transfer (IN) in DMA mode ................................................................733 USB connection example ...........................................................................................................738 CHAPTER 12 A/D CONVERTER ....................................................................................................... 739 12.1 Features .................................................................................................................................. 739 12.2 Configuration.......................................................................................................................... 740 14 User's Manual U16031EJ4V1UD 12.3 Control Registers ....................................................................................................................742 12.4 Operation .................................................................................................................................749 12.4.1 12.4.2 12.5.1 12.5.2 12.6.1 12.6.2 12.7.1 12.7.2 Basic operation ..........................................................................................................................749 Operation mode and trigger mode .............................................................................................750 Select mode operation ...............................................................................................................755 Scan mode operations ...............................................................................................................757 Select mode operation ...............................................................................................................759 Scan mode operation.................................................................................................................761 Select mode operations .............................................................................................................762 Scan mode operation.................................................................................................................765 12.5 Operation in A/D Trigger Mode..............................................................................................755 12.6 Operation in Timer Trigger Mode ..........................................................................................758 12.7 Operation in External Trigger Mode......................................................................................762 12.8 Cautions...................................................................................................................................766 12.9 How to Read A/D Converter Characteristics Table .............................................................768 CHAPTER 13 PWM UNIT....................................................................................................................772 13.1 13.2 13.3 13.4 Features ...................................................................................................................................772 Configuration...........................................................................................................................772 Control Registers ....................................................................................................................774 Operation .................................................................................................................................777 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 PWM basic operation.................................................................................................................777 Starting/stopping PWM operation ..............................................................................................780 Setting active level of PWM pulse..............................................................................................782 Specifying PWM pulse width rewrite period ...............................................................................783 Repeat cycle ..............................................................................................................................784 CHAPTER 14 PORT FUNCTIONS......................................................................................................785 14.1 Features ...................................................................................................................................785 14.2 Port Configuration ..................................................................................................................785 14.3 Port Pin Functions ..................................................................................................................815 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 Port 1 .........................................................................................................................................815 Port 2 .........................................................................................................................................820 Port 5 .........................................................................................................................................825 Port 6 .........................................................................................................................................830 Port 7 .........................................................................................................................................835 Port AL .......................................................................................................................................838 Port AH ......................................................................................................................................843 Port DH ......................................................................................................................................845 Port CS ......................................................................................................................................854 14.3.10 Port CT ......................................................................................................................................858 14.3.11 Port CM......................................................................................................................................861 14.3.12 Port CD ......................................................................................................................................864 14.4 Configuration of RESET, A2 to A15, and D0 to D15 Pins ...................................................866 14.5 Operation of Port Function ....................................................................................................868 14.5.1 14.5.2 Writing to I/O port.......................................................................................................................868 Reading from I/O port ................................................................................................................868 User's Manual U16031EJ4V1UD 15 14.5.3 14.6.1 14.6.2 14.6.3 14.7.1 14.7.2 Output status of alternate function in control mode ....................................................................868 Interrupt input pin .......................................................................................................................869 A/D converter input pin...............................................................................................................870 Timer C and timer ENC1 input pins............................................................................................870 Cautions on setting port pins......................................................................................................874 Cautions on bit manipulation instruction for port n register (Pn).................................................875 14.6 Noise Eliminator ..................................................................................................................... 869 14.7 Cautions .................................................................................................................................. 874 CHAPTER 15 RESET FUNCTIONS ................................................................................................... 876 15.1 15.2 15.3 15.4 Overview ................................................................................................................................. 876 Configuration.......................................................................................................................... 876 Operation ................................................................................................................................ 877 Initialization............................................................................................................................. 882 CHAPTER 16 DEBUG FUNCTION (DCU) ........................................................................................ 888 16.1 Functional Outline.................................................................................................................. 888 16.1.1 16.1.2 16.1.3 16.2.1 16.2.2 Debug function ...........................................................................................................................888 Trace function ............................................................................................................................889 Event function ............................................................................................................................889 Emulator connector ....................................................................................................................891 Recommended circuit example ..................................................................................................892 16.2 Connection with N-Wire Type Emulator............................................................................... 890 CHAPTER 17 ELECTRICAL SPECIFICATIONS ............................................................................... 893 CHAPTER 18 PACKAGE DRAWINGS .............................................................................................. 938 CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS......................................................... 940 APPENDIX A REGISTER INDEX ....................................................................................................... 941 APPENDIX B INSTRUCTION SET LIST ........................................................................................... 954 B.1 B.2 Conventions............................................................................................................................ 954 Instruction Set (in Alphabetical Order) ................................................................................ 957 APPENDIX C REVISION HISTORY ................................................................................................... 964 C.1 C.2 Major Revisions in This Edition............................................................................................ 964 Revision History up to Previous Edition.............................................................................. 967 16 User's Manual U16031EJ4V1UD CHAPTER 1 INTRODUCTION The V850E/ME2 is a product of the NEC Electronics single-chip microcontroller "V850 Series". This chapter gives a simple outline of the V850E/ME2. 1.1 Outline The V850E/ME2 is a 32-bit single-chip microcontroller that integrates the V850E1 CPU, which is a 32-bit RISCtype CPU core for ASIC, newly developed as the CPU core central to system LSI for the current age of system-onchip. This device incorporates cache, data RAM, instruction RAM, and various peripheral functions such as memory controllers, a DMA controller, timer/counter, serial interfaces, USB function controller (USBF), and an A/D converter for realizing high-capacity data processing and sophisticated real-time control. (1) V850E1 CPU The V850E1 CPU is a CPU core that enhances the external bus interface performance of the V850 CPU, which is the CPU core integrated in the V850 Series, and has added instructions supporting high-level languages, such as C-language switch statement processing, table lookup branching, stack frame creation/deletion, and data conversion. This enhances the performance of both data processing and control. It is possible to use the software resources of the V850 CPU integrated system since the instruction codes of the V850E1 are upwardly compatible at the object code level with those of the V850 CPU. (2) External memory interface function The V850E/ME2 features various on-chip external memory interfaces including separately configured address (26 bits) and data (32 bits) buses, and SDRAM and ROM interfaces, as well as on-chip memory controllers that can be directly linked to page ROM, etc., thereby raising system performance and reducing the number of parts needed for application systems. Also, through the DMA controller, CPU internal calculations and data transfers can be performed simultaneously with transfers to and from the external memory, so it is possible to process large volumes of image data or voice data, etc., and through high-speed execution of instructions using internal data RAM and instruction RAM, motor control, communications control and other real-time control tasks can be realized simultaneously. (3) Internal instruction RAM The instruction RAM can be accessed at high speed, in one clock, so that application programs can be executed in real time. (4) A full range of middleware and development environment products The V850E/ME2 can execute middleware such as JPEG, JBIG, MH/MR/MMR, and TCP/IP at high speed. Also, middleware that enables speech recognition, voice synthesis, and other such processing is available, and by including these middleware programs, a multimedia system can be easily realized. A development environment system that includes an optimized C compiler, debugger, in-circuit emulator, and other elements is also available. User's Manual U16031EJ4V1UD 17 CHAPTER 1 INTRODUCTION 1.2 Features Number of instructions: Minimum instruction execution time: General-purpose registers: Instruction set: 80 10 ns/7.5 ns/6.7 ns (at internal 100 MHz/133 MHz/150 MHz operation) 32 bits x 32 V850E1 CPU Signed multiplication (16 bits x 16 bits 32 bits or 32 bits x 32 bits 64 bits): 1 to 2 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock Bit manipulation instructions Load/store instructions with long/short format Signed load instructions Memory space: 256 MB linear address space (common program/data use) Chip select output function: 8 spaces Memory block division function: 2, 4, 6, 8, 64 MB/block Programmable wait function Idle state insertion function External bus interface: 32-bit data bus (address/data separated) 32-/16-/8-bit bus sizing function External bus division function: 1/1, 1/2, 1/3, 1/4 (66 MHz MAX.) Bus hold function External wait function Address setup wait function Endian control function Internal memory Instruction RAM: 128 KB Data RAM: 16 KB 8 KB 2-way set associative External interrupts: 40 (including NMI) Internal interrupts: 59 sources Exceptions: 2 sources Eight levels of priorities can be set. Memory access controller DRAM controller (compatible with SDRAM) Page ROM controller Speculative read/write buffer function Instruction cache Interrupts/exceptions: 18 User's Manual U16031EJ4V1UD CHAPTER 1 INTRODUCTION DMA controller: 4 channels Transfer unit: 8 bits/16 bits/32 bits Maximum transfer count: 65,536 (216) Transfer type: Flyby (1-cycle)/2-cycle Transfer mode: Single/Single step/Block Transfer target: Memory memory, memory I/O Transfer request: External request/On-chip peripheral I/O/ Software DMA transfer terminate (terminal count) output signal Next address setting function I/O lines: Input ports: 1 I/O ports: 77 Timer/counter function: 16-bit timer/event counter: 6 channels (no capture operation for 2 channels) 16-bit timers: 6 16-bit capture/compare registers: 12 16-bit interval timer: 4 channels Up/down counter/general-purpose timer for 16-bit 2-phase encoder input: 2 channels 16-bit capture/compare registers: 4 16-bit compare registers: 4 Serial interfaces: Asynchronous serial interface B (UARTB) Clocked serial interface 3 (CSI3) CSI3/UARTB: 1 channel UARTB: CSI3: 1 channel 1 channel USB function controller (USBF): 1 channel Full speed (12 Mbps) Endpoint Control transfer: 64 bytes x 2 Interrupt transfer: 8 bytes x 2 Bulk transfer (IN): 64 bytes x 2 banks x 2 Bulk transfer (OUT): 64 bytes x 2 banks x 2 A/D converter: PWM (Pulse Width Modulation): Clock generator: Power-save function: Package: 10-bit resolution A/D converter: 8 channels 16-bit resolution PWM: 2 channels x8 function using SSCG HALT/IDLE/software STOP mode 176-pin plastic LQFP (fine pitch) (24 x 24) 240-pin plastic FBGA (16 x 16) CMOS technology: All static circuits User's Manual U16031EJ4V1UD 19 CHAPTER 1 INTRODUCTION 1.3 Applications Servo control, NC machine tools, ink-jet printers, facsimiles, DVD players, video printers, PPC, information equipment, etc. 1.4 Ordering Information Part Number Package 176-pin plastic LQFP (fine pitch) (24 x 24) 176-pin plastic LQFP (fine pitch) (24 x 24) 176-pin plastic LQFP (fine pitch) (24 x 24) 176-pin plastic LQFP (fine pitch) (24 x 24) 176-pin plastic LQFP (fine pitch) (24 x 24) 176-pin plastic LQFP (fine pitch) (24 x 24) 240-pin plastic FBGA (16 x 16) 240-pin plastic FBGA (16 x 16) 240-pin plastic FBGA (16 x 16) 240-pin plastic FBGA (16 x 16) Maximum Operating Frequency 100 MHz 100 MHz 133 MHz 133 MHz 150 MHz 150 MHz 133 MHz 133 MHz 150 MHz 150 MHz PD703111AGM-10-UEU PD703111AGM-10-UEU-A PD703111AGM-13-UEU PD703111AGM-13-UEU-A PD703111AGM-15-UEU PD703111AGM-15-UEU-A PD703111AF1-13-GA3 PD703111AF1-13-GA3-A PD703111AF1-15-GA3 PD703111AF1-15-GA3-A Remark Products with -A at the end of the part number are lead-free products. 20 User's Manual U16031EJ4V1UD CHAPTER 1 INTRODUCTION 1.5 Pin Configuration * 176-pin plastic LQFP (fine pitch) (24 x 24) PD703111AGM-10-UEU PD703111AGM-10-UEU-A PD703111AGM-13-UEU PD703111AGM-13-UEU-A PD703111AGM-15-UEU PD703111AGM-15-UEU-A Top View P72/DMARQ2/INTPC20/TIC2 P73/DMAAK2/INTPC21 P74/TC2/TOC2 P75/DMARQ3/INTPC30/TIC3 P76/DMAAK3/INTPC31 P77/TC3/TOC3 SSEL0 SSEL1 PLLVSS PLLVDD OSCVSS X2 X1 OSCVDD UVDD UDM UDP P10/UCLK/INTP10 IVSS IVDD PLLSEL P11/SCK0/INTP11 P12/RXD0/SI0 P13/TXD0/SO0 P20/NMI EVSS EVDD P21/RXD1/INTP21 P22/TXD1/INTP22 P23/SCK1/INTP23 P24/SI1/INTP24 P25/SO1/INTP25 DCK DMS DRST DDI DDO TRCCLK TRCEND TRCDATA0 TRCDATA1 IVSS IVDD TRCDATA2 JIT1 JIT0 AVDD AVREFP ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVREFM AVSS MODE1 MODE0 INTP67/TOC1/P67 INTP66/INTPC11/P66 INTP65/TIC1/INTPC10/P65 TOC0/TC1/P55 INTPC01/DMAAK1/P54 INTPC00/TIC0/DMARQ1/P53 INTP52/TC0/P52 INTP51/DMAAK0/P51 INTP50/DMARQ0/P50 IVDD IVSS RESET ADTRG/SELFREF/PCM5 REFRQ/PCM4 HLDRQ/PCM3 HLDAK/PCM2 PCM1 WAIT/PCM0 CS7/PCS7 CS6/PCS6 IORD/CS5/PCS5 EVDD EVSS CS4/PCS4 CS3/PCS3 IOWR/CS2/PCS2 CS1/PCS1 CS0/PCS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 TRCDATA3 PDH15/D31/INTPD15/PWM1 PDH14/D30/INTPD14/PWM0 EVSS EVDD PDH13/D29/INTPD13/TIUD11 PDH12/D28/INTPD12/TO11 PDH11/D27/INTPD11/INTP111/TCLR11 PDH10/D26/INTPD10/INTP110/TCUD11 PDH9/D25/INTPD9/TIUD10 PDH8/D24/INTPD8/TO10 PDH7/D23/INTPD7/INTP101/TCLR10 PDH6/D22/INTPD6/INTP100/TCUD10 PDH5/D21/INTPD5/TOC5 PDH4/D20/INTPD4 PDH3/D19/INTPD3 EVSS EVDD PDH2/D18/INTPD2/TOC4 PDH1/D17/INTPD1 PDH0/D16/INTPD0 D15 D14 D13 D12 D11 D10 D9 D8 IVSS IVDD EVSS EVDD D7 D6 D5 D4 D3 D2 D1 D0 SDCKE/PCD0 EVSS EVDD A25/PAH9 A24/PAH8 A23/PAH7 A22/PAH6 A21/PAH5 A20/PAH4 A19/PAH3 A18/PAH2 EVDD EVSS IVDD IVSS A17/PAH1 A16/PAH0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 EVDD EVSS A4 A3 A2 INTPL1/A1/PAL1 INTPL0/A0/PAL0 BCYST/PCT7 WE/WR/PCT5 RD/PCT4 UUDQM/UUBE/UUWR/PCT3 PCT2/ULWR/ULBE/ULDQM PCT1/LUWR/LUBE/LUDQM PCT0/LLWR/LLBE/LLDQM IVDD IVSS SDRAS/PCD3 SDCAS/PCD2 BUSCLK/PCD1 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 User's Manual U16031EJ4V1UD 21 CHAPTER 1 INTRODUCTION * 240-pin plastic FBGA (16 x 16) PD703111AF1-13-GA3 PD703111AF1-13-GA3-A PD703111AF1-15-GA3 PD703111AF1-15-GA3-A BottomView 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TopView VUTRPNMLKJHGFEDCBA ABCDEFGHJKLMNPRTUV Index mark 22 User's Manual U16031EJ4V1UD CHAPTER 1 INTRODUCTION (1/2) Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 PCD3/SDRAS IVDD PCT2/ULWR/ULBE/ULDQM PCT5/WE/WR PAL1/INTPL1/A1 EVSS A7 A11 A15 PCS1/CS1 - - PAH8/A24 - A8 A12 PAH0/A16 - - - - PAH5/A21 PAH7/A23 PAH9/A25 - - PCD1/BUSCLK PCD2/SDCAS - PCT3/UUWR/UUBE/UUDQM PCT7/BCYST A2 - A14 IVSS EVDD - EVDD A9 - PCT4/RD - - IVSS PCT0/LLWR/LLBE/LLDQM - Pin Name - Pin No. C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E8 E9 E10 E11 E15 E16 E17 E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 PCS7/CS7 PCM0/WAIT PCM2/HLDAK IVDD EVDD User's Manual U16031EJ4V1UD Pin Name IVDD PAH2/A18 PAH4/A20 PAH6/A22 - PCS0/CS0 - D0 EVSS PCD0/SDCKE EVDD PCT1/LUWR/LUBE/LUDQM - PAL0/INTPL0/A0 A4 A6 - A13 EVSS PAH3/A19 - - PCS2/CS2/IOWR PCS3/CS3 EVDD D3 D2 D1 - A3 A5 A10 PAH1/A17 PCS4/CS4 EVSS PCS5/CS5/IORD PCS6/CS6 D6 D5 D4 - - Pin No. G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 H5 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J14 J15 J16 J17 J18 K1 K2 K3 K4 K5 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L14 L15 L16 L17 L18 M1 MODE0 EVSS EVDD D13 D11 D12 IVDD RESET IVSS D8 D9 D10 IVSS EVSS D7 PCM1 Pin Name PCM3/HLDRQ PCM4/REFRQ PCM5/ADTRG/SELFREF - - - - - - P50/INTP50/DMARQ0 P51/INTP51/DMAAK0 P52/INTP52/TC0 P53/INTPC00/TIC0/DMARQ1 D14 D15 PDH0/D16/INTPD0 PDH1/D17/INTPD1 PDH2/D18/INTPD2/TOC4 P55/TOC0/TC1 P54/INTPC01/DMAAK1 P65/INTP65/INTPC10/TIC1 P66/INTP66/INTPC11 - - PDH3/D19/INTPD3 PDH4/D20/INTPD4 MODE1 - - P67/INTP67/TOC1 - 23 CHAPTER 1 INTRODUCTION (2/2) Pin No. M2 M3 M4 M15 M16 M17 M18 N1 N2 N3 N4 N15 N16 N17 N18 P1 P2 P3 P4 P8 P9 P10 P11 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 DDO ANI0 ANI1 - PDH12/D28/INTPD12/TO11 EVSS PDH14/D30/INTPD14/PWM0 IVDD - UVDD - ANI6 AVREFM ANI7 AVSS PDH7/D23/INTPD7/INTP101/TCLR10 PDH8/D24/INTPD8/TO10 PDH9/D25/INTPD9/TIUD10 PDH10/D26/INTPD10/INTP110/TCUD11 ANI2 ANI3 ANI4 ANI5 - PDH11/D27/INTPD11/INTP111/TCLR11 PDH13/D29/INTPD13/TIUD11 - P23/INTP23/SCK1 P12/SI0/RXD0 - Pin Name PDH5/D21/INTPD5/TOC5 PDH6/D22/INTPD6/INTP100/TCUD10 - Pin No. R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 JIT1 JIT0 PDH15/D31/INTPD15/PWM1 - - UDP X1 OSCVSS SSEL1 P75/INTPC30/TIC3/DMARQ3 - TRCDATA1 TRCEND DDI - P21/INTP21/RXD1 P20/NMI - EVDD TRCDATA3 - AVREFP AVDD - DCK EVDD P11/INTP11/SCK0 IVSS UDM X2 PLLVDD SSEL0 - Pin Name Pin No. U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 PLLVSS P77/TOC3/TC3 P74/TOC2/TC2 - DMS P24/INTP24/SI1 - P13/SO0/TXD0 PLLSEL P10/INTP10/UCLK - - - TRCDATA2 IVSS TRCDATA0 - OSCVDD - - P76/INTPC31/DMAAK3 P73/INTPC21/DMAAK2 P72/INTPC20/TIC2/DMARQ2 - - TRCCLK DRST P25/INTP25/SO1 P22/INTP22/TXD1 EVSS IVDD - Pin Name - Remark Leave the A1, A4, A6, A7, A10, A14, A18, B1, B4, B8, B12 to B15, B17, C1, C2, C16, C18, D6, D10, D14, D15, E4, F4, F15, H1, H14, H17, J1, J4, J14, K18, L2, L15, L17, M1, M4, P1, P4, P10, P15, P18, R5, R15, R18, T3, T7, T10, T16, U2 to U4, U11, U13, U14, U18, V1, V5, V8, V12 to V14, and V18 pins open. 24 User's Manual U16031EJ4V1UD CHAPTER 1 INTRODUCTION Pin Identification A0 to A25: ADTRG: ANI0 to ANI7: AVDD: AVREFM: AVREFP: AVSS: BCYST: BUSCLK: CS0 to CS7: D0 to D31: DCK: DDI: DDO: DRST: DMS: DMAAK0 to DMAAK3: DMARQ0 to DMARQ3: EVDD: EVSS: HLDAK: HLDRQ: INTP10, INTP11, : INTP21 to INTP25, INTP50 to INTP52, INTP65 to INTP67, INTP100, INTP101, INTP110, INTP111, INTPC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, INTPC31, INTPD0 to INTPD15 INTPL0, INTPL1 IORD: IOWR: IVDD: IVSS: JIT0, JIT1: LLBE: LLDQM: LLWR: LUBE: LUDQM: LUWR: MODE0, MODE1: NMI: OSCVDD: OSCVSS: P10 to P13: P20 to P25: P50 to P55: P65 to P67: Address bus A/D trigger input Analog input Analog power supply Analog reference voltage Analog reference voltage Analog ground Bus cycle start timing Bus clock output Chip select Data bus Debug clock input Debug data input Debug data output Debug reset Debug mode DMA acknowledge DMA request Power supply for external pins Ground for external pins Hold acknowledge Hold request External interrupt input P72 to P77: PAH0 to PAH9: PAL0, PAL1: PCD0 to PCD3: PCM0 to PCM5: PCS0 to PCS7: PCT0 to PCT5, PCT7: PDH0 to PDH15: PLLSEL: PLLVDD: PLLVSS: PWM0, PWM1: RD: REFRQ: RESET: RXD0, RXD1: SCK0, SCK1: SDCAS: SDCKE: SDRAS: SELFREF: SI0, SI1: SO0, SO1: SSEL0, SSEL1: TC0 to TC3: TCLR10, TCLR11: TCUD10, TCUD11: TIC0 to TIC3: TIUD10, TIUD11: TO10, TO11, : TOC0 to TOC5 TRCCLK: TRCDATA0 to: TRCDATA3 TRCEND: TXD0, TXD1: UCLK: UDM: UDP: ULBE: ULDQM: ULWR: UUBE: UUDQM: UUWR: UVDD: WAIT: WE: WR: X1, X2: Port 7 Port AH Port AL Port CD Port CM Port CS Port CT Port DH PLL operating mode select PLL power supply PLL ground Pulse width modulation Read strobe Refresh request Reset Receive data Serial clock SDRAM column address strobe SDRAM clock enable SDRAM row address strobe Self-refresh request Serial input Serial output Clock generator operating mode select Terminal count signal Timer clear Timer control pulse input Timer input Timer count pulse input Timer output Trace clock Trace data output Trace end status output Transmit data USB external clock input USB data input & output (-) USB data input & output (+) Upper byte enable (D16 to D23) Upper DQ mask enable (D16 to D23) Upper write strobe (D16 to D23) Upper byte enable (D24 to D31) Upper DQ mask enable (D24 to D31) Upper write strobe (D24 to D31) Power supply for USB unit Wait Write enable Write strobe output enable Crystal I/O read strobe I/O write strobe Power supply for internal unit Ground for internal unit SSCG jitter select Lower byte enable (D0 to D7) Lower DQ mask enable (D0 to D7) Lower write strobe (D0 to D7) Lower byte enable (D8 to D15) Lower DQ mask enable (D8 to D15) Lower write strobe (D8 to D15) Mode Non-maskable interrupt request Clock generator power supply Clock generator ground Port 1 Port 2 Port 5 Port 6 User's Manual U16031EJ4V1UD 25 CHAPTER 1 INTRODUCTION 1.6 Function Blocks 1.6.1 Internal block diagram DRST, DCK, DMS, DDI DCU DDO, TRCCLK, TRCDATA0 to TRCDATA3, TRCEND NMI INTP10, INTP11 INTP21 to INTP25 INTP50 to INTP52 INTP65 to INTP67 INTPD0 to INTPD15 INTPL0, INTPL1 TCLR10, TCLR11 TIUD10, TIUD11 TCUD10, TCUD11 INTP100, INTP110 INTP101, INTP111 TO10, TO11 TIC0 to TIC3 INTPC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, INTPC31 TOC0 to TOC3 Data RAM TMC 16 KB General-purpose registers (32 bits x 32) TMENC1 CPU MEMC WAIT HLDRQ HLDAK A0 to A25 D0 to D31 Multiplier (32 x 32 64) 32-bit barrel shifter ALU SDRAMC Instruction queue ROMC CS0, CS1, CS3, CS4, CS6, CS7 CS2/IOWR CS5/IORD BCYST RD xxWR/xxBE WR BUSCLK SDCKE SDRAS SDCAS WE xxDQM REFRQ SELFREF DMARQ0 to DMARQ3 DMAC TOC4, TOC5 TMC BBR TMD SI0/RXD0 SO0/TXD0 SCK0 SI1 SO1 SCK1 RXD1 TXD1 SSEL0, SSEL1 JIT0, JIT1 PLLSEL X1 X2 OSCVDD OSCVSS PLLVDD PLLVSS DMAAK0 to DMAAK3 TC0 to TC3 BCU INTC Instruction cache 8 KB PC SRAMC Instruction RAM 128 KB System registers CSI30/UARTB0 Ports PWM PWM0, PWM1 P10 to P13 P20 P21 to P25 P50 to P55 P65 to P67 P72 to P77 PAL0, PAL1 PAH0 to PAH9 PCD0 to PCD3 PCS0 to PCS7 PCT0 to PCT5, PCT7 PDH0 to PDH15 PCM0 to PCM5 CSI31 ADC ANI0 to ANI7 ADTRG AVREFP, AVREFM AVDD AVSS UDP UDM UCLK UVDD UARTB1 USBF CG System controller RESET MODE0, MODE1 IVDD IVSS EVDD EVSS Remark xx: LL, LU, UL, UU 26 User's Manual U16031EJ4V1UD CHAPTER 1 INTRODUCTION 1.6.2 On-chip units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits or 32 bits x 32 bits 64 bits) and a barrel shifter (32 bits), help accelerate complex processing. (2) Bus control unit (BCU) The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue in the CPU. The BCU controls an SDRAM controller (SDRAMC), SRAM controller (SRAMC), page ROM controller (ROMC), and DMA controller (DMAC) and performs external memory access and DMA transfer. (a) SDRAM controller (SDRAMC) The SDRAM controller generates the SDRAS, SDCAS, UUDQM, ULDQM, LUDQM, and LLDQM signals and performs access control for SDRAM. CAS latency 1 (excluding flyby DMA transfer), 2, and 3 are supported, and the burst length is fixed to 1. A refresh function that supports the CBR (auto) refresh cycle and a dynamic self-refresh function based on an external input are also available. (b) Page ROM controller (ROMC) This controller supports accessing ROM that includes the page access function. It performs address comparisons with the immediately preceding bus cycle and executes wait control for normal access (off-page)/page access (on-page). (c) DMA controller (DMAC) This controller controls data transfer between memory and I/O instead of the CPU. There are two address modes: flyby (1-cycle) transfer, and 2-cycle transfer. There are three bus modes, single transfer, single step transfer, and block transfer. (3) RAM Instruction RAM (128 KB) and data RAM (16 KB) are provided. The instruction RAM can be accessed in one clock from the CPU when an instruction is fetched. Its write access time depends on the BUSCLK frequency to the CS0 space and the number of wait cycles. This RAM is mapped from address 00000000H. The data RAM can be accessed in one clock from the CPU when its data is read or written. It is mapped from address FFFF8000H. (4) Cache A 2-way set associative instruction cache (8 KB) is provided. User's Manual U16031EJ4V1UD 27 CHAPTER 1 INTRODUCTION (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTPn) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple-interrupt servicing control can be performed (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, L1, C00, C01, C10, C11, C20, C21, C30, C31). (6) Clock generator (CG) This clock generator supplies frequencies which are 8 times the input clock (FX) (using an on-chip PLL) as the internal system clock (fCLK). As the input clock, an external oscillator is input from pins X1 and X2. (7) Timer/counter function This unit incorporates a 6-channel 16-bit timer/event counter C (TMC), 4-channel 16-bit interval timer D (TMD), and 2-channel up/down counter/general-purpose timer (TMENC1) for 16-bit 2-phase encoder input and can measure pulse widths or frequency and output a programmable pulse. (8) Serial interfaces The serial interfaces consist of 3 channels divided between an asynchronous serial interface B (UARTB) and clocked serial interface 3 (CSI3). Of these 3 channels, one is alternative with UARTB and CSI3, one is fixed to CSI3, and one is fixed to UARTB. UARTB transfers data by using the TXDn and RXDn pins (n = 0, 1). CSI3 transfers data by using the SOn, SIn, and SCKn pins (n = 0, 1). In addition, a USB function controller (USBF) is also provided. (9) A/D converter (ADC) This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive approximation method. (10) PWM Two channels for PWM signal output of 16-bit resolution have been provided. By connecting an external low-pass filter, PWM output can be used as digital to analog conversion output. PWM is ideal for actuator control signals such as those in motors. (11) On-chip debug function (DCU) An on-chip debug function via an N-Wire type emulator is provided. 28 User's Manual U16031EJ4V1UD CHAPTER 1 INTRODUCTION (12) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port 1 Port 2 I/O 4-bit I/O 1-bit input, 5-bit I/O 6-bit I/O 3-bit I/O 6-bit I/O 2-bit I/O 10-bit I/O 16-bit I/O 8-bit I/O 7-bit I/O 6-bit I/O Control Function Serial interface I/O, USB clock signal input, external interrupt input NMI input, serial interface I/O, external interrupt input Port 5 Port 6 Port 7 Port AL Port AH Port DH Port CS Port CT Port CM DMA controller I/O, external interrupt input, timer/counter I/O Timer/counter I/O, external interrupt input DMA controller I/O, timer/counter I/O, external interrupt input External address bus, external interrupt input External address bus External data bus, external interrupt input, PWM output, timer/counter I/O External bus interface control signal output External bus interface control signal output Wait insertion signal input, external bus interface control signal I/O, self-refresh request signal input, A/D converter external trigger input External bus interface control signal output, bus clock output Port CD 4-bit I/O User's Manual U16031EJ4V1UD 29 CHAPTER 2 PIN FUNCTIONS The names and functions of the pins in the V850E/ME2 are listed below. These pins can be divided into port pins and non-port pins according to their functions. 2.1 List of Pin Functions (1) Port pins (1/3) Pin Name Pin No. GM F1 I/O Function Alternate Function P10 P11 P12 P13 P20 P21 P22 P23 P24 P25 P50 P51 P52 P53 P54 P55 P65 P66 P67 P72 P73 P74 P75 P76 P77 159 V11 155 154 153 152 149 148 147 146 145 25 24 23 22 21 20 19 18 17 R9 P9 V9 T9 T8 U8 P8 V7 U7 J15 J16 J17 J18 K15 K14 K16 K17 L18 I/O Port 1 4-bit I/O port Input data can be read/output data can be written in 1-bit units. INTP10/UCLK INTP11/SCK0 SI0/RXD0 SO0/TXD0 Input I/O Port 2 P20 is an input port dedicated to checking the NMI input status. If a valid edge is input, it operates as an NMI input. P21 to P25 are a 5-bit I/O port. Input data can be read/output data can be written in 1-bit units. NMI INTP21/RXD1 INTP22/TXD1 INTP23/SCK1 INTP24/SI1 INTP25/SO1 I/O Port 5 6-bit I/O port Input data can be read/output data can be written in 1-bit units. INTP50/DMARQ0 INTP51/DMAAK0 INTP52/TC0 INTPC00/TIC0/DMARQ1 INTPC01/DMAAK1 TOC0/TC1 I/O Port 6 3-bit I/O port Input data can be read/output data can be written in 1-bit units. INTP65/INTPC10/TIC1 INTP66/INTPC11 INTP67/TOC1 INTPC20/TIC2/DMARQ2 INTPC21/DMAAK2 TOC2/TC2 INTPC30/TIC3/DMARQ3 INTPC31/DMAAK3 TOC3/TC3 176 U17 175 U16 174 V17 173 T15 I/O Port 7 6-bit I/O port Input data can be read/output data can be written in 1-bit units. 172 U15 171 V16 Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 30 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Pin No. GM PAH0 PAH1 PAH2 PAH3 PAH4 PAH5 PAH6 PAH7 PAH8 PAH9 PAL0 PAL1 58 57 52 51 50 49 48 47 46 45 76 75 F1 B11 E11 C13 D13 C14 A15 C15 A16 B16 A17 D7 C7 I/O Port AL 2-bit I/O port Input data can be read/output data can be written in 1-bit units. PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDH8 PDH9 PDH10 PDH11 PDH12 PDH13 PDH14 PDH15 PCD0 PCD1 PCD2 PCD3 112 113 114 117 118 119 120 121 122 123 124 125 126 127 130 131 91 88 87 86 K3 K4 K5 L4 L5 M2 M3 N1 N2 N3 N4 P2 R1 P3 R3 U1 D3 B2 B3 C3 I/O Port CD 4-bit I/O port Input data can be read/output data can be written in 1-bit units. I/O Port DH 8-/16-bit I/O port Input data can be read/output data can be written in 1-bit units. D16/INTPD0 D17/INTPD1 D18/INTPD2/TOC4 D19/INTPD3 D20/INTPD4 D21/INTPD5/TOC5 D22/INTPD6/INTP100/TCUD10 D23/INTPD7/INTP101/TCLR10 D24/INTPD8/TO10 D25/INTPD9/TIUD10 D26/INTPD10/INTP110/TCUD11 D27/INTPD11/INTP111/TCLR11 D28/INTPD12/TO11 D29/INTPD13/TIUD11 D30/INTPD14/PWM0 D31/INTPD15/PWM1 SDCKE BUSCLK SDCAS SDRAS I/O Port AH 8-/10-bit I/O port Input data can be read/output data can be written in 1-bit units. A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 INTPL0/A0 INTPL1/A1 I/O Function Alternate Function Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 31 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Pin No. GM PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT7 34 33 32 31 30 29 44 43 42 41 40 37 36 35 83 82 81 80 79 78 77 F1 F17 G15 F18 G16 G17 G18 C17 B18 D16 D17 E15 E17 E18 F16 A3 D5 C5 B5 A5 C6 B6 I/O Port CT 7-bit I/O port Input data can be read/output data can be written in 1-bit units. I/O Port CS 8-bit I/O port Input data can be read/output data can be written in 1-bit units. I/O Port CM 6-bit I/O port Input data can be read/output data can be written in 1-bit units. HLDAK HLDRQ REFRQ ADTRG/SELFREF CS0 CS1 CS2/IOWR CS3 CS4 CS5/IORD CS6 CS7 LLWR/LLBE/LLDQM LUWR/LUBE/LUDQM ULWR/ULBE/ULDQM UUWR/UUBE/UUDQM RD WE/WR BCYST WAIT - I/O Function Alternate Function Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 32 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/7) Pin Name Pin No. GM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 ADTRG ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 76 75 74 73 72 69 68 67 66 65 64 63 62 61 60 59 58 57 52 51 50 49 48 47 46 45 29 5 6 7 8 9 10 11 12 F1 D7 C7 B7 E8 D8 E9 D9 C9 B9 A9 E10 C10 B10 D11 A11 C11 B11 E11 C13 D13 C14 A15 C15 A16 B16 A17 G18 P16 P17 N15 N16 N17 N18 M15 M17 Input Input A/D converter external trigger input Analog inputs to A/D converter PAH0 PAH1 PAH2 PAH3 PAH4 PAH5 PAH6 PAH7 PAH8 PAH9 PCM5/SELFREF - - - - - - - - Output 26-bit address bus for external memory PAL0/INTPL0 PAL1/INTPL1 - - - - - - - - - - - - - - I/O Function Alternate Function Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 33 CHAPTER 2 PIN FUNCTIONS (2/7) Pin Name Pin No. GM AVDD AVREFM AVREFP AVSS BCYST 3 13 4 14 77 F1 R17 M16 R16 M18 B6 - Output Ground potential for A/D converter Strobe signal output that shows the start of the bus cycle BUSCLK CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 88 44 43 42 41 40 37 36 35 92 93 94 95 96 97 98 99 104 105 106 107 108 109 110 111 112 113 114 117 118 B2 C17 B18 D16 D17 E15 E17 E18 F16 D1 E3 E2 E1 F3 F2 F1 G4 H2 H3 H4 J2 J3 J5 K1 K2 K3 K4 K5 L4 L5 PDH0/INTPD0 PDH1/INTPD1 PDH2/INTPD2/TOC4 PDH3/INTPD3 PDH4/INTPD4 I/O 32-bit data bus for external memory Output Output Clock output for SDRAM Chip select signal output PCD1 PCS0 PCS1 PCS2/IOWR PCS3 PCS4 PCS5/IORD PCS6 PCS7 - - - - - - - - - - - - - - - - PCT7 - Input 3.3 V positive power supply for A/D converter Reference voltage input for A/D converter - - - - I/O Function Alternate Function Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 34 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (3/7) Pin Name Pin No. GM D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DCK DDI DDO DMAAK0 DMAAK1 DMAAK2 DMAAK3 DMARQ0 DMARQ1 DMARQ2 DMARQ3 DMS DRST EVDD EVSS HLDAK HLDRQ INTP10 INTP11 INTP21 INTP22 119 120 121 122 123 124 125 126 127 130 131 144 141 140 24 21 175 172 25 22 176 173 143 142 F1 M2 M3 N1 N2 N3 N4 P2 R1 P3 R3 U1 R7 T6 R6 J16 K15 U16 U15 J15 J18 U17 T15 V6 U6 Input Input - - Output Input Input Debug mode select Reset input for debugging 3.3 V positive power supply for external pin Ground potential for external pin Bus hold acknowledge output Bus hold request input External maskable interrupt request input PCM2 PCM3 P10/UCLK P11/SCK0 P21/RXD1 P22/TXD1 Input DMA request signal input Input Input Output Output Debug clock input Debug data input Debug data output DMA acknowledge signal output P51/INTP51 P54/INTPC01 P73/INTPC21 P76/INTPC31 P50/INTP50 P53/INTPC00/TIC0 P72/INTPC20/TIC2 P75/INTPC30/TIC3 - - - - I/O 32-bit data bus for external memory PDH5/INTPD5/TOC5 PDH6/INTPD6/INTP100/TCUD10 PDH7/INTPD7/INTP101/TCLR10 PDH8/INTPD8/TO10 PDH9/INTPD9/TIUD10 PDH10/INTPD10/INTP110/TCUD11 PDH11/INTPD11/INTP111/TCLR11 PDH12/INTPD12/TO11 PDH13/INTPD13/TIUD11 PDH14/INTPD14/PWM0 PDH15/INTPD15/PWM1 - - - I/O Function Alternate Function Note 1 Note 2 Note 3 Note 4 32 31 159 155 149 148 F18 G16 V11 R9 T8 U8 Notes 1. 2. 3. 4. Remark 38, 53, 70, 89, 100, 115, 128, 150 A8, A13, D4, D18, G2, L1, R8, T1 39, 54, 71, 90, 101, 116, 129, 151 C8, D2, D12, E16, G3, L3, R2, U9 GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 35 CHAPTER 2 PIN FUNCTIONS (4/7) Pin Name Pin No. GM INTP23 INTP24 INTP25 INTP50 INTP51 INTP52 INTP65 INTP66 INTP67 INTPD0 INTPD1 INTPD2 INTPD3 INTPD4 INTPD5 INTPD6 INTPD7 INTPD8 INTPD9 INTPD10 INTPD11 INTPD12 INTPD13 INTPD14 INTPD15 INTPL0 INTPL1 INTP100 INTP101 INTP110 INTP111 INTPC00 INTPC01 INTPC10 INTPC11 147 146 145 25 24 23 19 18 17 112 113 114 117 118 119 120 121 122 123 124 125 126 127 130 131 76 75 120 121 124 125 22 21 19 18 F1 P8 V7 U7 J15 J16 J17 K16 K17 L18 K3 K4 K5 L4 L5 M2 M3 N1 N2 N3 N4 P2 R1 P3 R3 U1 D7 C7 M3 N1 N4 P2 J18 K15 K16 K17 Input External maskable interrupt request input/timer C0 external capture trigger input External maskable interrupt request input/timer C1 external capture trigger input Input Timer ENC11 external capture trigger input Input Timer ENC10 external capture trigger input Input External maskable interrupt request input P23/SCK1 P24/SI1 P25/SO1 P50/DMARQ0 P51/DMAAK0 P52/TC0 P65/TIC1/INTPC10 P66/INTPC11 P67/TOC1 PDH0/D16 PDH1/D17 PDH2/TOC4/D18 PDH3/D19 PDH4/D20 PDH5/TOC5/D21 PDH6/INTP100/TCUD10/D22 PDH7/INTP101/TCLR10/D23 PDH8/TO10/D24 PDH9/TIUD10/D25 PDH10/INTP110/TCUD11/D26 PDH11/INTP111/TCLR11/D27 PDH12/TO11/D28 PDH13/TIUD11/D29 PDH14/PWM0/D30 PDH15/PWM1/D31 PAL0/A0 PAL1/A1 PDH6/TCUD10/D22/INTPD6 PDH7/TCLR10/D23/INTPD7 PDH10/TCUD11/D26/INTPD10 PDH11/TCLR11/D27/INTPD11 P53/TIC0/DMARQ1 P54/DMAAK1 P65/INTP65/TIC1 P66/INTP66 I/O Function Alternate Function Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 36 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (5/7) Pin Name Pin No. GM INTPC20 INTPC21 INTPC30 INTPC31 IORD IOWR IVDD IVSS JIT0 JIT1 LLBE LLDQM LLWR LUBE LUDQM LUWR MODE0 MODE1 NMI OSCVDD OSCVSS PLLSEL PLLVDD 176 175 173 172 37 42 F1 U17 U16 T15 U15 E17 D16 Output Output - Input External maskable interrupt request input/timer C2 external capture trigger input External maskable interrupt request input/timer C3 external capture trigger input DMA read strobe signal output DMA write strobe signal output 1.5 V positive power supply for internal unit Ground potential for internal unit Input Specifying SSCG operating mode P72/TIC2/DMARQ2 P73/DMAAK2 P75/TIC3/DMARQ3 P76/DMAAK3 PCS5/CS5 PCS2/CS2 - - - - Output Output Output Output Output Output Input External data bus byte enable signal output (lowest byte (D0 to D7)) Output disable/write mask signal output for SDRAM (lowest byte (D0 to D7)) External data bus write strobe signal output (lowest byte (D0 to D7)) External data bus byte enable signal output (third byte (D8 to D15)) Output disable/write mask signal output for SDRAM (third byte (D8 to D15)) External data bus write strobe signal output (third byte (D8 to D15)) Specifying V850E/ME2 operating mode PCT0/LLDQM/LLWR PCT0/LLWR/LLBE PCT0/LLBE/LLDQM PCT1/LUDQM/LUWR PCT1/LUWR/LUBE PCT1/LUBE/LUDQM - - Input - Non-maskable interrupt request signal input 3.3 V positive power supply for oscillator Ground potential for oscillator Input - Input specifying PLL operating mode 1.5 V positive power supply for PLL synthesizer PLLVSS PWM0 PWM1 RD REFRQ 168 130 131 79 30 V15 R3 U1 A5 G17 Output Output External data bus read strobe signal output Refresh request signal output for SDRAM Output Ground potential for PLL synthesizer PWM pulse signal output - PDH14/D30/INTPD14 PDH15/D31/INTPD15 PCT4 PCM4 P20 - - - - I/O Function Alternate Function Note 1 Note 2 Note 3 Note 4 2 1 83 83 83 82 82 82 16 15 152 163 166 156 167 T18 T17 A3 A3 A3 D5 D5 D5 L16 L14 T9 U12 T13 V10 R13 Notes 1. 2. 3. 4. Remark 26, 55, 84, 102, 134, 157 C4, C12, G1, H18, R4, U10 27, 56, 85, 103, 135, 158 A2, A12, H5, H16, R10, V3 GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 37 CHAPTER 2 PIN FUNCTIONS (6/7) Pin Name Pin No. GM RESET RXD0 RXD1 SCK0 SCK1 SDCAS 28 154 149 155 147 87 F1 H15 P9 T8 R9 P8 B3 Output Column address strobe signal output for SDRAM SDCKE SDRAS SELFREF SI0 SI1 SO0 SO1 SSEL0 SSEL1 TC0 TC1 TC2 TC3 TCLR10 TCLR11 TCUD10 TCUD11 TIC0 TIC1 TIC2 TIC3 TIUD10 TIUD11 TO10 TO11 TOC0 TOC1 TOC2 TOC3 91 86 29 154 146 153 145 170 169 23 20 174 171 121 125 120 124 22 19 176 173 123 127 122 126 20 17 174 171 D3 C3 G18 P9 V7 V9 U7 R14 T14 J17 K14 V17 V16 N1 P2 M3 N4 J18 K16 U17 T15 N3 P3 N2 R1 K14 L18 V17 V16 Output Output Input External count clock input to timer ENC10 and ENC11 Pulse signal output of timer ENC10 and ENC11 Pulse signal output of timer C0 to C5 Input Input Count operation switching signal input to timer ENC10 and ENC11 External count clock input of timer C0 to C3 Input Clear signal input to timer ENC10 and ENC11 Output Input Output Output Output Input Input SDRAM clock enable signal output Row address strobe signal output for SDRAM Self-refresh request input for SDRAM CSI30 and CSI31 serial receive data input (3wire) CSI30 and CSI31 serial transmit data output (3-wire) Specifying the clock generator's operating mode DMA transfer end (terminal count) signal output P52/INTP52 P55/TOC0 P74/TOC2 P77/TOC3 PDH7/D23/INTPD7/INTP101 PDH11/D27/INTPD11/INTP111 PDH6/D22/INTPD6/INTP100 PDH10/D26/INTPD10/INTP110 P53/DMARQ1/INTPC00 P65/INTP65/INTPC10 P72/INTPC20/DMARQ2 P75/INTPC30/DMARQ3 PDH9/D25/INTPD9 PDH13/D29/INTPD13 PDH8/D24/INTPD8 PDH12/D28/INTPD12 P55/TC1 P67/INTP67 P74/TC2 P77/TC3 PCD0 PCD3 PCM5/ADTRG P12/RXD0 P24/INTP24 P13/TXD0 P25/INTP25 - - I/O Input Input System reset input UARTB0 and UARTB1 serial receive data input CSI30 and CSI31 serial clock I/O (3-wire) P12/SI0 P21/INTP21 P11/INTP11 P23/INTP23 PCD2 - I/O Function Alternate Function Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 38 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (7/7) Pin Name Pin No. GM TOC4 TOC5 TRCCLK TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 TRCEND TXD0 TXD1 UCLK UDM UDP ULBE Note I/O Function Alternate Function F1 K5 M2 U5 V4 T4 V2 T2 T5 V9 U8 V11 R11 T11 C5 Input I/O I/O Output Output Output Trace end status output UARTB0 and UARTB1 serial transmit data output USB clock signal input USB data I/O (-) USB data I/O (+) External data bus byte enable signal output (second byte (D16 to D23)) P13/SO0 P22/INTP22 P10/INTP10 - - PCT2/ULDQM/ULWR Output Output Trace clock output Trace data output (D0 to D3) Output Pulse signal output of timer C0 to C5 PDH2/D18/INTPD2 PDH5/D21/INTPD5 - - - - - - 114 119 139 137 136 133 132 138 153 148 159 161 160 81 ULDQM 81 C5 Output Output disable/write mask signal output for SDRAM (second byte (D16 to D23)) PCT2/ULWR/ULBE ULWR 81 C5 Output External data bus write strobe signal output (second byte (D16 to D23)) PCT2/ULBE/ULDQM UUBE 80 B5 Output External data bus byte enable signal output (highest byte (D24 to D31)) PCT3/UUWR/UUDQM UUDQM 80 B5 Output Output disable/write mask signal output for SDRAM (highest byte (D24 to D31)) PCT3/UUWR/UUBE UUWR 80 B5 Output - Input External data bus write strobe signal output (highest byte (D24 to D31)) PCT3/UUDQM/UUBE - PCM0 UVDD WAIT 162 34 P11 F17 3.3 V positive power supply for USB Control signal input that inserts a wait in the bus cycle WE WR X1 X2 78 78 164 165 C6 C6 T12 R12 Output Output Input - Write enable signal output for SDRAM Write strobe signal output for SDRAM Connects the crystal resonator for system clock oscillation. PCT5/WR PCT5/WE - - Note When using as the UCLK pin, be careful to avoid the input of a staircase waveform due to reflection, etc., or the input of noise. Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 39 CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The status of each pin after reset, in power-save mode (software STOP, IDLE, HALT modes), and during DMA transfer, refresh, and bus hold (TH) is shown below. Operating Status Pin A0 to A1 (PAL0 to PAL1) A2 to A15 A16 to A25 (PAH0 to PAH9) D0 to D15 D16 to D31 (PDH to PDH15) CS0 to CS7 (PCS0 to PCS7) IOWR (PCS2) IORD (PCS5) LLWR, LUWR, ULWR, UUWR (PCT0 to PCT3) LLBE, LUBE, ULBE, UUBE (PCT0 to PCT3) LLDQM, LUDQM, ULDQM, UUDQM (PCT0 to PCT3) RD (PCT4) WR (PCT5) WE (PCT5) BCYST (PCT7) WAIT (PCM0) HLDAK (PCM2) HLDRQ (PCM3) REFRQ (PCM4) SELFREF (PCM5) SDCKE (PCD0) BUSCLK (PCD1) SDCAS (PCD2) SDRAS (PCD3) DMAAK0 (P51) DMAAK1 (P54) DMAAK2 (P73) DMAAK3 (P76) MODE0, MODE1 DDI, DMS, DCK NMI (P20) SSEL0, SSEL1 PLLSEL Peripheral function input pin other than above Peripheral function output pin other than above Port input pin other than above Port output pin other than above Hi-Z x Hold Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating Hi-Z Hi-Z x x x x SELF SELF SELF SELF H H H H H - Operating - Note 2 Note 2 Reset IDLE Mode/ Software STOP Mode HALT Mode/ During DMA Transfer/Refresh Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Bus Hold (TH) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - L Operating Operating Operating Operating Operating Hi-Z Hi-Z H H H H Note 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z x x Hi-Z x x Hi-Z Hi-Z x Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SELF H H H H H H H H H - Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating MODE0, MODE1 input DDI, DMS, DCK input NMI input SSEL0, SSEL1 input PLLSEL input x x Hold - Hold - Operating Operating - Operating Operating Operating Operating Remark Explanation on Note and Remark are given on the next page. User's Manual U16031EJ4V1UD 40 CHAPTER 2 PIN FUNCTIONS Notes 1. 2. Remark The pin set in the port mode holds the status immediately before. High-level output when the SDRAM controller is not used Hi-Z: H: L: -: x: High-impedance High-level output Low-level output No sampling of input No select function at reset SELF: Self-refresh state when pins are connected to SDRAM Notes on turning on/off power The V850E/ME2 has two power supply pins: a power supply pin for internal units (IVDD) and a power supply pin for external pins (EVDD). The I/O status of an alternate-function I/O pin may be undefined outside the range in which the operation is guaranteed. If this undefined I/O status affects the system, the pin can be made to go into a high-impedance state using the following measure. * When turning on power Keep the voltage on the EVDD pin at 0 V until the voltage on the IVDD pin reaches the operation guaranteed range (100 MHz product, 133 MHz product: 1.35 to 1.65 V, 150 MHz product: 1.40 to 1.65 V). * When turning off power Keep the voltage on the IVDD pin to within the operation guaranteed range (100 MHz product, 133 MHz product: 1.35 to 1.65 V, 150 MHz product: 1.40 to 1.65 V) until the voltage on the EVDD pin drops to 0 V. IVDD Note Note EVDD 0V Oscillation stabilization time 0V RESET (input) Note 100 MHz product, 133 MHz product: 1.35 V 150 MHz product: 1.40 V User's Manual U16031EJ4V1UD 41 CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P10 to P13 (Port 1) *** 3-state I/O P10 to P13 function as a 4-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as serial interface I/O (UARTB0, CSI30), USB clock signal input, and external interrupt request input. The operation mode can be set to port or control mode in 1-bit units, specified by the PMC1 register. (a) Port mode P10 to P13 can be set to input or output in 1-bit units using the PM1 register. (b) Control mode P10 to P13 can be set to port/control mode in 1-bit units using the PMC1 register. (i) INTP10, INTP11 (Interrupt request from peripherals) *** input These are external interrupt request input pins. (ii) SO0 (Serial output) *** output This is a serial transmit data output pin of CSI30. (iii) SI0 (Serial input) *** input This is a serial receive data input pin of CSI30. (iv) SCK0 (Serial clock) *** 3-state I/O This is a CSI30 serial clock I/O pin. (v) TXD0 (Transmit data) *** output This is a serial transmit data output pin of UARTB0. (vi) RXD0 (Receive data) *** input This is a serial receive data input pin of UARTB0. (vii) UCLK (USB clock) *** input This is a clock input pin of the USB. When using as the UCLK pin, be careful to avoid the input of a staircase waveform due to reflection, etc., or the input of noise. 42 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (2) P20 to P25 (Port 2) *** 3-state I/O Port 2, except P20, which is an input pin dedicated to checking the input status of NMI, is a 5-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as serial interface I/O (UARTB1/CSI31) and external interrupt request input. The operation mode can be set to port or control mode in 1-bit units, specified by the PMC2 register. (a) Port mode P21 to P25 can be set to input or output in 1-bit units using the PM2 register. P20 is an input port dedicated to checking the NMI input status, and if a valid edge is input, it operates as an NMI input. (b) Control mode P21 to P25 can be set to port/control mode in 1-bit units using the PMC2 register. (i) NMI (Non-maskable interrupt request) *** input This is the non-maskable interrupt request input pin. (ii) INTP21 to INTP25 (Interrupt request from peripherals) *** input These are external interrupt request input pins. (iii) SO1 (Serial output) *** output This is a serial transmit data output pin of CSI31. (iv) SI1 (Serial input) *** input This is a serial receive data input pin of CSI31. (v) SCK1 (Serial clock) *** 3-state I/O This is a CSI31 serial clock I/O pin. (vi) TXD1 (Transmit data) *** output This is a serial transmit data output pin of UARTB1. (vii) RXD1 (Receive data) *** input This is a serial receive data input pin of UARTB1. User's Manual U16031EJ4V1UD 43 CHAPTER 2 PIN FUNCTIONS (3) P50 to P55 (Port 5) *** 3-state I/O P50 to P55 function as a 6-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as DMA request input, DMA acknowledge output, DMA transfer termination output (terminal count), timer/counter I/O, and external interrupt request input. The operation mode can be set to port or control mode in 1-bit units, specified by the PMC5 register. (a) Port mode P50 to P55 can be set to input or output in 1-bit units using the PM5 register. (b) Control mode P50 to P55 can be set to port/control mode in 1-bit units using the PMC5 register. (i) DMARQ0, DMARQ1 (DMA request) *** input These are DMA service request signal input pins. They correspond to DMA channels 0 and 1, respectively, and operate independently of each other. The priority order is fixed to DMARQ0 > DMARQ1 > DMARQ2 > DMARQ3. These signals are sampled at the rising edge of the BUSCLK signal. Maintain an active level until a DMA request is acknowledged. (ii) DMAAK0, DMAAK1 (DMA acknowledge) *** output These are acknowledge signal output pins that show a DMA service request was granted. They correspond to DMA channels 0 and 1, respectively, and operate independently of each other. In flyby transfer, these signals become active when external memory is being accessed and internal instruction RAM (in the write mode) is being accessed. When DMA transfers are being executed between internal data RAM, internal instruction RAM (in the read mode), and on-chip peripheral I/O, they do not become active. In 2-cycle transfer, these are used as the signals to control the DMARQ0 and DMARQ1 signals. (iii) TC0, TC1 (Terminal count) *** output These are terminal count signal output pins that show that the DMA transfer from the DMA controller is complete. These pins correspond to DMA channels 0 and 1 respectively, and operate independently of each other. The terminal count signals of DMA channels 0 to 3 can be commonly output from the TC0 pin. (iv) INTPC00, INTPC01 (Interrupt request from peripherals) *** input These are external interrupt request input pins and the external capture trigger input pins of timer C0. (v) TIC0 (Timer input) *** input This is an external count clock input pin of timer C0. (vi) TOC0 (Timer output) *** output This is a pulse signal output pin of timer C0. (vii) INTP50 to INTP52 (Interrupt request from peripherals) *** input These are external interrupt request input pins. 44 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (4) P65 to P67 (Port 6) *** 3-state I/O P65 to P67 function as a 3-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as timer/counter I/O and external interrupt request input. The operation mode can be set to port or control mode in 1-bit units, specified by the PMC6 register. (a) Port mode P65 to P67 can be set to input or output in 1-bit units using the PM6 register. (b) Control mode P65 to P67 can be set to port/control mode in 1-bit units using the PMC6 register. (i) TIC1 (Timer input) *** input This is the external count clock input pin for timer C1. (ii) TOC1 (Timer output) *** output This is the pulse signal output pin for timer C1. (iii) INTP65 to INTP67 (Interrupt request from peripherals) *** input These are external interrupt request input pins. (iv) INTPC10, INTPC11 (Interrupt request from peripherals) *** input These are external interrupt request input pins and the external capture trigger input pins of timer C1. User's Manual U16031EJ4V1UD 45 CHAPTER 2 PIN FUNCTIONS (5) P72 to P77 (Port 7) *** 3-state I/O P72 to P77 function as a 6-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as DMA request input, DMA acknowledge output, DMA transfer termination output (terminal count), timer/counter I/O, and external interrupt request input. The operation mode can be set to port or control mode in 1-bit units, specified by the PMC7 register. (a) Port mode P72 to P77 can be set to input or output in 1-bit units using the PM7 register. (b) Control mode P72 to P77 can be set to port/control mode in 1-bit units using the PMC7 register. (i) DMARQ2, DMARQ3 (DMA request) *** input These are DMA service request signal input pins. They correspond to DMA channels 2 and 3, respectively, and operate independently of each other. The priority order is fixed to DMARQ0 > DMARQ1 > DMARQ2 > DMARQ3. These signals are sampled at the rising edge of the BUSCLK signal. Maintain an active level until a DMA request is acknowledged. (ii) DMAAK2, DMAAK3 (DMA acknowledge) *** output These are acknowledge signal output pins that show a DMA service request was granted. They correspond to DMA channels 2 and 3, respectively, and operate independently of each other. In flyby transfer, these signals become active only when external memory is being accessed and internal instruction RAM (in the write mode) is being accessed. When DMA transfers are being executed between internal data RAM, internal instruction RAM (in the read mode), and on-chip peripheral I/O, they do not become active. In 2-cycle transfer, these are used as the signals to control the DMARQ2 and DMARQ3 signals. (iii) TC2, TC3 (Terminal count) *** output These are terminal count signal output pins that show that DMA transfer from the DMA controller is complete. These pins correspond to DMA channels 2 and 3 respectively, and operate independently of each other. The terminal count signals of DMA channels 0 to 3 can be commonly output from the TC0 pin. (iv) INTPC20, INTPC21, INTPC30, INTPC31 (Interrupt request from peripherals) *** input These are external interrupt request input pins and the external capture trigger input pins of timers C2 and C3. (v) TIC2, TIC3 (Timer input) *** input These are external count clock input pins of timers C2 and C3. (vi) TOC2, TOC3 (Timer output) *** output These are pulse signal output pins of timers C2 and C3. 46 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (6) PCM0 to PCM5 (Port CM) *** 3-state I/O PCM0 to PCM5 function as a 6-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as a port, in the control mode, these pins operate as wait insertion signal input, bus hold control signal, refresh request signal output for SDRAM, self-refresh request signal input, and A/D converter external trigger input. The operation mode can be set to port or control in 1-bit units, specified by the PMCCM register. (a) Port mode PCM0 to PCM5 can be set to input or output in 1-bit units using the PMCM register. (b) Control mode PCM0 to PCM5 can be set to port/control mode in 1-bit units using the PMCCM register. (i) WAIT (Wait) *** input This is the control signal input pin at which a data wait is inserted in the bus cycle. The WAIT signal can be input asynchronously to the BUSCLK signal. When the BUSCLK signal falls, sampling is executed. When the set/hold time is not terminated within the sampling timing, wait insertion may not be executed. Caution Input to the WAIT pin is valid immediately after reset release. If a low level is input to the WAIT pin because an external pull-down resistor is connected to it, the external bus is placed in the bus hold status. (ii) HLDAK (Hold acknowledge) *** output This is the acknowledge signal output pin that indicates the high impedance status for the address bus, data bus, and control bus when the V850E/ME2 receives a bus hold request. While this signal is active, the impedance of the address bus, data bus, and control bus becomes high and the bus mastership is transferred to the external bus master. (iii) HLDRQ (Hold request) *** input This is the input pin through which an external device requests the V850E/ME2 to release the address bus, data bus, and control bus. The HLDRQ signal can be input asynchronously to the BUSCLK signal. When this pin is active, the address bus, data bus, and control bus are set to the high impedance status. This occurs either when the V850E/ME2 completes execution of the current bus cycle or immediately if no bus cycle is being executed, then the HLDAK signal is set as active and the bus is released. In order to make the bus hold state secure, keep the HLDRQ signal active until the HLDAK signal is output. Caution Input to the HLDRQ pin is valid immediately after reset release. If a low level is input to the HLDRQ pin because an external pull-down resistor is connected to it, the external bus is placed in the bus hold status. User's Manual U16031EJ4V1UD 47 CHAPTER 2 PIN FUNCTIONS (iv) REFRQ (Refresh request) *** output This is the refresh request signal output pin for SDRAM. This signal becomes active during the refresh cycle. Also, during bus hold, it becomes active when a refresh request is generated and notifies the external bus master that a refresh request was generated. (v) SELFREF (Self refresh request) *** input This is a self-refresh request signal input pin for SDRAM. The internal data RAM and internal instruction RAM (in the read mode) can be accessed even in the self-refresh cycle. However, access to an on-chip peripheral I/O register or external device is held pending until the self-refresh cycle is cancelled. Caution Input to the SELFREF pin becomes valid immediately after the reset signal has been cleared. Consequently, if a low level is input to the SELFREF pin by an external pull-down resistor, self refreshing is started. Note that, at this time, the normal instruction fetch cycle does not occur. (vi) ADTRG (A/D trigger input) *** input This is an external trigger input pin of the A/D converter. 48 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (7) PCT0 to PCT5, PCT7 (Port CT) *** 3-state I/O PCT0 to PCT5 and PCT7 function as a 7-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when memory is expanded externally. The operation mode can be set to port or control mode in 1-bit units, specified by the PMCCT register. (a) Port mode PCT0 to PCT5 and PCT7 can be set to input or output in 1-bit units using the PMCT register. (b) Control mode PCT0 to PCT5 and PCT7 can be set to port/control mode in 1-bit units using the PMCCT register. (i) LLWR (Lower lower byte write strobe) *** 3-state output This is a strobe signal output pin that shows whether the bus cycle currently being executed is a write cycle for the SRAM, external ROM, or external peripheral I/O area. For the data bus, the lowest byte (D0 to D7) becomes valid. If the bus cycle is a lowest memory write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes inactive at the falling edge of the BUSCLK signal in the T2 state. (ii) LUWR (Lower upper byte write strobe) *** 3-state output This is a strobe signal output pin that shows whether the bus cycle currently being executed is a write cycle for the SRAM, external ROM, or external peripheral I/O area. For the data bus, the third byte (D8 to D15) becomes valid. If the bus cycle is a third byte memory write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes inactive at the falling edge of the BUSCLK signal in the T2 state. (iii) ULWR (Upper lower byte write strobe) *** 3-state output This is a strobe signal output pin that shows whether the bus cycle currently being executed is a write cycle for the SRAM, external ROM, or external peripheral I/O area. For the data bus, the second byte (D16 to D23) becomes valid. If the bus cycle is a second byte memory write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes inactive at the falling edge of the BUSCLK signal in the T2 state. (iv) UUWR (Upper upper byte write strobe) *** 3-state output This is a strobe signal output pin that shows whether the bus cycle currently being executed is a write cycle for the SRAM, external ROM, or external peripheral I/O area. For the data bus, the highest byte (D24 to D31) becomes valid. If the bus cycle is a highest memory write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes inactive at the falling edge of the BUSCLK signal in the T2 state. (v) LLBE (Lower lower byte enable) *** 3-state output This is a signal output pin that enables the lowest byte (D0 to D7) of the external data bus. (vi) LUBE (Lower upper byte enable) *** 3-state output This is a signal output pin that enables the third byte (D8 to D15) of the external data bus. User's Manual U16031EJ4V1UD 49 CHAPTER 2 PIN FUNCTIONS (vii) ULBE (Upper lower byte enable) *** 3-state output This is a signal output pin that enables the second byte (D16 to D23) of the external data bus. (viii) UUBE (Upper upper byte enable) *** 3-state output This is a signal output pin that enables the highest byte (D24 to D31) of the external data bus. (ix) LLDQM (Lower lower DQ mask enable) *** 3-state output This is a control signal output pin for the data bus to SDRAM. For the data bus, the lowest byte (D0 to D7) is valid. This signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask control during a write operation. (x) LUDQM (Lower upper DQ mask enable) *** 3-state output This is a control signal output pin for the data bus to SDRAM. For the data bus, the third byte (D8 to D15) is valid. This signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask control during a write operation. (xi) ULDQM (Upper lower DQ mask enable) *** 3-state output This is a control signal output pin for the data bus to SDRAM. For the data bus, the second byte (D16 to D23) is valid. This signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask control during a write operation. (xii) UUDQM (Upper upper DQ mask enable) *** 3-state output This is a control signal output pin for the data bus to SDRAM. For the data bus, the highest byte (D24 to D31) is valid. This signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask control during a write operation. (xiii) RD (Read strobe) *** 3-state output This is a strobe signal output pin that shows the bus cycle currently being executed is a read cycle for the SRAM, external ROM, external peripheral I/O, or page ROM area. In the idle state (TI), it becomes inactive. (xiv) WR (Write strobe) *** 3-state output This is a strobe signal output pin that shows the bus cycle currently being executed is a write cycle for the SRAM, external ROM, or external peripheral I/O area. It becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes inactive at the falling edge of the BUSCLK signal in the T2 state. (xv) WE (Write enable) *** 3-state output This is an enable signal output pin that shows the bus cycle currently being executed is a write cycle for the SDRAM area. In the idle state (TI), it becomes inactive. (xvi) BCYST (Bus cycle start timing) *** 3-state output This is a status signal output pin that shows the start of the bus cycle. It becomes active for 1-clock cycle from the start of each cycle. 50 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (8) PCS0 to PCS7 (Port CS) *** 3-state I/O PCS0 to PCS7 function as an 8-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when memory and peripheral I/O are expanded externally. The operation mode can be set to port or control mode in 1-bit units, specified by the PMCCS register. (a) Port mode PCS0 to PCS7 can be set to input or output in 1-bit units using the PMCS register. (b) Control mode PCS0 to PCS7 can be set to port/control mode in 1-bit units using the PMCCS register. (i) CS0 to CS7 (Chip select) *** 3-state output These are the chip select signal output pins for the SRAM, external ROM, external peripheral I/O, and page ROM area. The CSn signal is assigned to memory block n (n = 0 to 7). It becomes active while the bus cycle that accesses the corresponding memory block is activated. In the idle state (TI), it becomes inactive. (ii) IOWR (I/O write) *** 3-state output This is a write strobe signal output pin for external I/O during DMA flyby transfer. It indicates whether the bus cycle currently being executed is a write cycle for external I/O during DMA flyby transfer, or a write cycle for the SRAM area. Note that if the IOEN bit of the bus cycle period control register (BCP) is set (1), this signal can be output even in the normal SRAM, external ROM, or external I/O cycle. (iii) IORD (I/O read) *** 3-state output This is a read strobe signal output pin for external I/O during DMA flyby transfer. It indicates whether the bus cycle currently being executed is a read cycle for external I/O during DMA flyby transfer, or a read cycle for the SRAM area. Note that if the IOEN bit of the BCP register is set (1), this signal can be output even in the normal SRAM, external ROM, or external I/O cycle. User's Manual U16031EJ4V1UD 51 CHAPTER 2 PIN FUNCTIONS (9) PCD0 to PCD3 (Port CD) *** 3-state I/O PCD0 to PCD3 function as a 4-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as a port, in control mode, these pins operate as control signal outputs for when the memory and peripheral I/O are expanded externally. The operation mode can be set to port or control mode in 1-bit units, specified by the PMCCD register. (a) Port mode PCD0 to PCD3 can be set to input or output in 1-bit units using the PMCD register. (b) Control mode PCD0 to PCD3 can be set to port or control mode in 1-bit units using the PMCCD register. (i) SDCKE (SDRAM clock enable) *** output This is the SDRAM clock enable output signal. It becomes inactive in self-refresh and standby mode. (ii) BUSCLK (Clock output) *** output This is a clock output pin for SDRAM. (iii) SDCAS (SDRAM column address strobe) *** 3-state output This is a command output signal for SDRAM. (iv) SDRAS (SDRAM row address strobe) *** 3-state output This is a command output signal for SDRAM. (10) PAH0 to PAH9 (Port AH) *** 3-state I/O PAH0 to PAH9 function as an 8- or 10-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as a port, in control mode, these pins operate as an address bus (A16 to A25) for when the memory is expanded externally. The operation mode can be set to port or control mode in 1-bit units, specified by the PMCAH register. (a) Port mode PAH0 to PAH9 can be set to input or output in 1-bit units using the PMAH register. (b) Control mode PAH0 to PAH9 can be set to function alternately as A16 to A25 using the PMCAH register. (i) A16 to A25 (Address) *** 3-state output These are the address output pins of the higher 10 bits of the address bus's 26-bit address when the external memory is accessed. The output changes in synchronization with the fall of the BUSCLK signal in the T1 state. In the idle state (TI), the address of the bus cycle immediately before is retained. 52 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (11) PAL0, PAL1 (Port AL) *** 3-state I/O PAL0 and PAL1 function as a 2-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as a port, in control mode, these pins operate as an address bus (A0, A1) and external interrupt request input for when the memory is expanded externally. The operation mode can be set to port or control mode in 1-bit units, specified by the PMCAL register. (a) Port mode PAL0 and PAL1 can be set to input or output in 1-bit units using the PMAL register. (b) Control mode PAL0 and PAL1 can be set to port or control mode in 1-bit units using the PMCAL register. (i) A0, A1 (Address) *** 3-state output These are the address output pins of the lower 2 bits of the address bus's 26-bit address when the external memory is accessed. The output changes in synchronization with the fall of the BUSCLK signal in the T1 state. In the idle state (TI), the address of the bus cycle immediately before is retained. (ii) INTPL0, INTPL1 (Interrupt request from peripherals) *** input These are external interrupt request input pins. User's Manual U16031EJ4V1UD 53 CHAPTER 2 PIN FUNCTIONS (12) PDH0 to PDH15 (Port DH) *** 3-state I/O PDH0 to PDH15 function as an 8- or 16-bit I/O port that can read input data or write output data in 1-bit units. Besides functioning as a port, in control mode, these pins operate as timer/counter I/O, PWM output, data bus (D16 to D31), and external interrupt request input. The operation mode can be set to port or control mode in 1-bit units, specified by the PMCDH register. (a) Port mode PDH0 to PDH15 can be set to input or output in 1-bit units using the PMDH register. (b) Control mode PDH0 to PDH15 can be set to port or control mode in 1-bit units using the PMCDH register. (i) INTPD0 to INTPD15 (Interrupt request from peripherals) *** input These are external interrupt request input pins. (ii) TOC4, TOC5 (Timer output) *** output These are pulse signal output pins of timers C4 and C5. (iii) INTP100, INTP101, INTP110, INTP111 (Timer capture trigger input) *** input These are external capture trigger input pins of timers ENC10 and ENC11. (iv) TIUD10, TIUD11 (Timer count pulse input) *** input These are external count clock input pins of timers ENC10 and ENC11. (v) TCUD10, TCUD11 (Timer control pulse input) *** input These are external count clock input pins of timers ENC10 and ENC11. (vi) TCLR10, TCLR11 (Timer clear) *** input These are clear signal input pins of timers ENC10 and ENC11. (vii) TO10, TO11 (Timer output) *** output These are pulse signal output pins of timers ENC10 and ENC11. (viii) PWM0, PWM1 (Pulse width modulation) *** output These pins output the PWM pulse signal. (ix) D16 to D31 (Data) *** 3-state I/O These pins constitute a data bus for when the external memory is accessed. These are the higher 16-bit I/O bus pins of the 32-bit data. The output changes in synchronization with the rise of the BUSCLK signal in the T1 state. (13) PLLSEL (PLL operating mode select) *** input This is an input pin used to specify the PLL operating mode. Fix the operating mode via a resistor. (14) PLLVDD (PLL power supply) This is a 1.5 V positive power supply pin for PLL synthesizer. 54 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (15) PLLVSS (PLL ground) This is a ground pin for PLL synthesizer. (16) SSEL0, SSEL1 (Clock generator operating mode select) *** input These are input pins used to specify the clock generator's operating mode. Fix the operating mode via a resistor. (17) JIT0, JIT1 (SSCG (spread spectrum frequency synthesizer phase locked loop) clock generator operating mode select) *** input These are input pins used to specify the SSCG operating mode. Fix the operating mode via a resistor. (18) DCK (Debug clock) *** input This pin inputs a debug clock. At the rising edge of the DCK signal, the DMS and DDI signals are sampled, and data is output from the DDO pin at the falling edge of the DCK signal. Keep this pin high when the debug function is not used. (19) DDI (Debug data input) *** input This pin inputs debug data. This pin is sampled at the rising edge of the DCK signal when the debug serial interface is in the shift state. Data is input with the LSB first. Keep this pin high when the debug function is not used. (20) DDO (Debug data output) *** 3-state output This pin outputs debug data. It outputs data at the falling edge of the DCK signal when the debug serial interface is in the shift state. Data is output with the LSB first. (21) DMS (Debug mode select) *** input This input pin selects a debug mode. Depending on the level of the DMS signal, the state machine of the debug serial interface changes. This pin is sampled at the rising edge of the DCK signal. Keep this pin high when the debug function is not used. (22) DRST (Debug reset) *** input This pin inputs a debug reset signal that is a negative-logic signal to initialize the DCU asynchronously. When this signal goes low, the DCU is reset/invalidated. Keep this pin low when the debug function is not used. (23) MODE0, MODE1 (Mode) *** input These are input pins used to specify the operating mode. Fix the operating mode via a resistor. (24) RESET (Reset) *** input RESET is a signal that is input asynchronously and that has a constant low level width regardless of the operating clock's status. When this signal is input, a system reset is executed as the first priority ahead of all other operations. In addition to being used for ordinary initialization/start operations, this pin can also be used to release a standby mode (HALT, IDLE, or software STOP). (25) X1, X2 (Crystal) These pins are used to connect the resonator that generates the system clock. User's Manual U16031EJ4V1UD 55 CHAPTER 2 PIN FUNCTIONS (26) ANI0 to ANI7 (Analog input) *** input These are analog input pins for the A/D converter. Connect a capacitor between these pins and AVSS to prevent noise-related operation faults. Also, do not apply voltage that is outside the range for AVSS and AVDD to pins that are being used as inputs for the A/D converter. If it is possible for noise above the AVDD range or below the AVSS to enter, clamp these pins using a diode that has a small VF value. (27) AVREFM, AVREFP (Analog reference voltage) *** input These are reference voltage supply pins for the A/D converter. (28) AVDD (Analog power supply) This is a 3.3 V positive power supply pin for the A/D converter. (29) AVSS (Analog ground) This is a ground pin for the A/D converter. (30) EVDD (Port power supply) This is a 3.3 V positive power supply pin for port. (31) EVSS (Port ground) This is a ground pin for port. (32) OSCVDD (Power supply for clock generator) This is a 3.3 V positive power supply pin for the clock generator. (33) OSCVSS (Ground for clock generator) This is a ground pin for the clock generator. (34) UVDD (Ground) This is a 3.3 V positive power supply pin for the USB. (35) UDP (USB Data +) *** I/O This is a data I/O pin (+) of the USB. (36) UDM (USB Data -) *** I/O This is a data I/O pin (-) of the USB. (37) IVDD (Power supply) These are 1.5 V positive power supply pins for each internal unit. All the IVDD pins should be connected to a positive power supply. (38) IVSS (Ground) These are ground pins. All the IVSS pins should be grounded. (39) A2 to A15 (Address) *** output These are the address output pins of the lower 14 bits of the address bus's 26-bit address when the external memory is accessed. 56 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (40) D0 to D15 (Data) *** 3-state I/O These pins constitute a data bus for when the external memory is accessed. These are the lower 16-bit I/O bus pins of the 32-bit data. The output changes in synchronization with the rise of the BUSCLK signal in the T1 state. (41) TRCCLK (Trace clock) *** output This is a trace clock output pin. (42) TRCDATA0 to TRCDATA3 (Trace data output) *** output These are trace data output (D0 to D3) pins. (43) TRCEND (Trace end status output) *** output This is a trace end status output pin. User's Manual U16031EJ4V1UD 57 CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins It is recommended that 1 to 10 k resistors be used when connecting to VDD or VSS via resistors. (1/5) Pin Alternate Pin Pin No. GM P10 P11 P12 P13 P20 P21 P22 P23 P24 P25 P50 INTP10/UCLK INTP11/SCK0 SI0/RXD0 SO0/TXD0 NMI INTP21/RXD1 INTP22/TXD1 INTP23/SCK1 INTP24/SI1 INTP25/SO1 INTP50/DMARQ0 159 155 154 153 152 149 148 147 146 145 25 F1 V11 R9 P9 V9 T9 T8 U8 P8 V7 U7 J15 5 Input: Independently connect to EVDD via a 5 2 8-J 5 8-J Connect to VSS directly. Input: Independently connect to EVDD or 5 8-J Input: Independently connect to EVDD or I/O Circuit Type Recommended Connection EVSS via a resistor. Output: Leave open. EVSS via a resistor. Output: Leave open. resistor. Output: Leave open. P51 P52 P53 INTP51/DMAAK0 INTP52/TC0 INTPC00/TIC0/DMARQ1 24 23 22 J16 J17 J18 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Input: Independently connect to EVDD via a resistor. Output: Leave open. P54 P55 P65 P66 P67 P72 INTPC01/DMAAK1 TOC0/TC1 INTP65/INTPC10/TIC1 INTP66/INTPC11 INTP67/TOC1 INTPC20/TIC2/DMARQ2 21 20 19 18 17 176 K15 K14 K16 K17 L18 U17 Input: Independently connect to EVDD via a Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. resistor. Output: Leave open. P73 P74 P75 INTPC21/DMAAK2 TOC2/TC2 INTPC30/TIC3/DMARQ3 175 174 173 U16 V17 T15 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Input: Independently connect to EVDD via a resistor. Output: Leave open. P76 P77 INTPC31/DMAAK3 TOC3/TC3 172 171 U15 V16 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 58 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (2/5) Pin Alternate Pin Pin No. GM PAH0 PAH1 PAH2 PAH3 PAH4 PAH5 PAH6 PAH7 PAH8 PAH9 PAL0 PAL1 PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDH8 PDH9 PDH10 PDH11 PDH12 PDH13 PDH14 PDH15 PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 INTPL0/A0 INTPL1/A1 D16/INTPD0 D17/INTPD1 D18/INTPD2/TOC4 D19/INTPD3 D20/INTPD4 D21/INTPD5/TOC5 D22/INTPD6/INTP100/ TCUD10 D23/INTPD7/INTP101/ TCLR10 D24/INTPD8/TO10 D25/INTPD9/TIUD10 D26/INTPD10/INTP110/ TCUD11 D27/INTPD11/INTP111/ TCLR11 D28/INTPD12/TO11 D29/INTPD13/TIUD11 D30/INTPD14/PWM0 D31/INTPD15/PWM1 CS0 CS1 CS2/IOWR CS3 CS4 CS5/IORD CS6 CS7 126 127 130 131 44 43 42 41 40 37 36 35 R1 P3 R3 U1 C17 B18 D16 D17 E15 E17 E18 F16 125 P2 122 123 124 N2 N3 N4 121 N1 58 57 52 51 50 49 48 47 46 45 76 75 112 113 114 117 118 119 120 F1 B11 E11 C13 D13 C14 A15 C15 A16 B16 A17 D7 C7 K3 K4 K5 L4 L5 M2 M3 5 Input: Independently connect to EVDD or I/O Circuit Type Recommended Connection EVSS via a resistor. Output: Leave open. Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 59 CHAPTER 2 PIN FUNCTIONS (3/5) Pin Alternate Pin Pin No. GM PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT7 PCM0 LLWR/LLBE/LLDQM LUWR/LUBE/LUDQM ULWR/ULBE/ULDQM UUWR/UUBE/UUDQM RD WE/WR BCYST WAIT 83 82 81 80 79 78 77 34 F1 A3 D5 C5 B5 A5 C6 B6 F17 Input: Independently connect to EVDD via a resistor. Output: Leave open. PCM1 PCM2 PCM3 HLDAK HLDRQ - 33 32 31 G15 F18 G16 8-J 5 Input: Independently connect to EVDD or 5 Input: Independently connect to EVDD or I/O Circuit Type Recommended Connection EVSS via a resistor. Output: Leave open. EVSS via a resistor. Output: Leave open. Input: Independently connect to EVDD via a resistor. Output: Leave open. PCM4 REFRQ 30 G17 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. PCM5 ADTRG/SELFREF 29 G18 Input: Independently connect to EVDD via a resistor. Output: Leave open. PCD0 PCD1 PCD2 PCD3 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 SDCKE BUSCLK SDCAS SDRAS - - - - - - - - - - - - - - 91 88 87 86 74 73 72 69 68 67 66 65 64 63 62 61 60 59 D3 B2 B3 C3 B7 E8 D8 E9 D9 C9 B9 A9 E10 C10 B10 D11 A11 C11 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 60 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS (4/5) Pin Alternate Pin Pin No. GM D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 - - - - - - - - - - - - - - - - 92 93 94 95 96 97 98 99 104 105 106 107 108 109 110 111 F1 D1 E3 E2 E1 F3 F2 F1 G4 H2 H3 H4 J2 J3 J5 K1 K2 5 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. I/O Circuit Type Recommended Connection Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 61 CHAPTER 2 PIN FUNCTIONS (5/5) Pin Alternate Pin Pin No. GM AVDD AVSS DCK DDI DMS DDO DRST TRCCLK TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 TRCEND UVDD UDM UDP ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVREFM AVREFP - - - - - - - - - - - - - - - - - - - - - - - - - - 3 14 144 141 143 140 142 139 137 136 133 132 138 162 161 160 5 6 7 8 9 10 11 12 13 4 F1 R17 M18 R7 T6 V6 R6 U6 U5 V4 T4 V2 T2 T5 P11 R11 T11 P16 P17 N15 N16 N17 N18 M15 M17 M16 R16 - - Connect to EVDD. 9-E - 24-A Connect to EVDD. Connect to EVSS. Leave open. Connect to EVSS. Leave open. - - 1 Connect to EVDD. Connect to EVSS. Connect to EVDD via a resistor. I/O Circuit Type Recommended Connection Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 62 User's Manual U16031EJ4V1UD CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 1 Type 8-J VDD Data VDD P-ch IN N-ch Output disable P-ch IN/OUT N-ch Type 2 Type 9-E IN IN + - AVSS AVREF Schmitt-triggered input with hysteresis characteristics Type 5 VDD Data Type 24-A UVDD P-ch IN/OUT Output data Input data P-ch IN/OUT N-ch Output disable N-ch Output data Input enable EVSS User's Manual U16031EJ4V1UD 63 CHAPTER 3 CPU FUNCTION The CPU of the V850E/ME2 is based on RISC architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 Features * Minimum instruction execution time: 10 ns/7.5 ns/6.7 ns (@100 MHz/133 MHz/150 MHz internal operation) * Memory space Program space: 64 MB linear Data space: * Internal 32-bit architecture * Five-stage pipeline control * Multiply/divide instructions * Saturated operation instructions * One-clock 32-bit shift instruction * Load/store instruction with long/short format * Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 4 GB linear * Thirty-two 32-bit general-purpose registers 64 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/ME2 can be classified into two categories: a general program register set and a dedicated system register set. All the registers have a 32-bit width. For details, refer to V850E1 Architecture User's Manual. Figure 3-1. CPU Register Set (1) Program register set 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (Element pointer (EP)) r31 (Link pointer (LP)) 31 PC (Program counter) 0 (Zero register) (Assembler-reserved register) (Stack pointer (SP)) (Global pointer (GP)) (Text pointer (TP)) 0 (2) System register set 31 0 EIPC (Status saving register during interrupt) EIPSW (Status saving register during interrupt) FEPC (Status saving register during NMI) FEPSW (Status saving register during NMI) ECR (Interrupt source register) PSW (Program status word) CTPC (Status saving register during CALLT execution) CTPSW (Status saving register during CALLT execution) DBPC (Status saving register during exception/debug trap) DBPSW (Status saving register during exception/debug trap) CTBP (CALLT base pointer) User's Manual U16031EJ4V1UD 65 CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are provided. All these registers can be used for data variables or address variables. However, care must be exercised as follows in using the r0 to r5, r30, and r31 registers. (a) r0, r30 r0 and r30 are implicitly used by instructions. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used as a base pointer when accessing memory using the SLD and SST instructions. (b) r1, r3 to r5, r31 r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, their contents must be saved before using these registers so that they are not lost. The contents must be restored to the registers after the registers have been used. (c) r2 r2 is sometimes used by a real-time OS. When the real-time OS to be used is not using r2, r2 can be used as an address variable register or a data variable register. Table 3-1. General-Purpose Registers Name r0 r1 r2 r3 r4 r5 Usage Zero register Assembler-reserved register Always holds 0 Working register for generating 32-bit immediate data Operation Address/data variable register (when r2 is not used by the real-time OS) Stack pointer Global pointer Text pointer Used to generate stack frame when function is called Used to access global variable in data area Register to indicate the start of the text area (where program code is allocated) r6 to r29 r30 r31 Address/data variable registers Element pointer Link pointer Base pointer when memory is accessed Used by compiler when calling function Remark For detailed descriptions of r1, r3 to r5, and r31 used by an assembler or C compiler, refer to the CA850 (C Compiler Package) Assembly Language User's Manual. (2) Program counter (PC) This register holds the instruction address during program execution. The lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to 26, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 PC Fixed to 0 26 25 Instruction address during execution 10 0 After reset 00100000H 66 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2. System Register Numbers No. System Register Name Operand Specification LDSR Instruction 0 1 2 3 4 5 6 to 15 Status saving register during interrupt (EIPC) Note 1 STSR Instruction Status saving register during interrupt (EIPSW) Status saving register during NMI (FEPC) Status saving register during NMI (FEPSW) Interrupt source register (ECR) Program status word (PSW) Note 1 x Reserved for future function expansion (operations that access these register numbers cannot be guaranteed). x x 16 17 18 19 20 21 to 31 Status saving register during CALLT execution (CTPC) Status saving register during CALLT execution (CTPSW) Status saving register during exception/debug trap (DBPC) Status saving register during exception/debug trap (DBPSW) CALLT base pointer (CTBP) Reserved for future function expansion (operations that access these register numbers cannot be guaranteed). x x Note 2 Note 2 Note 2 Note 2 Notes 1. 2. Because these registers have only one set, to enable multiple interrupts, it is necessary to save these registers by program. These registers can be accessed in the period between DBTRAP instruction execution and DBRET instruction execution. Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 by the LDSR instruction, bit 0 will be ignored when the program is returned to with the RETI instruction after interrupt servicing (because bit 0 of the PC is fixed to 0). When setting the value of EIPC, FEPC, and CTPC, use an even value (bit 0 = 0). Remark : Access allowed x: Access prohibited User's Manual U16031EJ4V1UD 67 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)). The address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to EIPC, except for some instructions (see 7.8 Period in Which CPU Does Not Acknowledge Interrupts). The current PSW contents are saved to EIPSW. Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion. When the RETI instruction is executed, the values in EIPC and EIPSW are restored to the PC and PSW, respectively. 31 EIPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 EIPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) 68 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions. The current PSW contents are saved to FEPSW. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion. When the RETI instruction has been executed, the values of FEPC and FEPSW are restored to the PC and PSW, respectively. 31 FEPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) (3) Interrupt source register (ECR) Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This register is a read-only register, and thus data cannot be written to it using the LDSR instruction. 31 ECR FECC 16 15 EICC 0 After reset 00000000H Bit position 31 to 16 15 to 0 Bit name FECC EICC Description Non-maskable interrupt (NMI) exception code Exception, maskable interrupt exception code User's Manual U16031EJ4V1UD 69 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution. Interrupt request acknowledgment is held pending while a write to the PSW is being executed by the LDSR instruction. Bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 PSW RFU 876543210 NP EP ID SAT CY OV S Z After reset 00000020H Bit position 31 to 8 7 Flag name RFU NP Reserved field. Fixed to 0. Description Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when an NMI request is acknowledged, and disables multiple interrupts. 0: NMI servicing not in progress 1: NMI servicing in progress 6 EP Indicates that exception processing is in progress. This flag is set to 1 when an exception occurs. Moreover, interrupt requests can be acknowledged even when this bit is set. 0: Exception processing not in progress 1: Exception processing in progress 5 ID Indicates whether maskable interrupt request acknowledgment is enabled. 0: Interrupt enabled (EI) 1: Interrupt disabled (DI) Note 4 SAT Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed. 0: Not saturated 1: Saturated 3 CY Indicates whether carry or borrow occurred as the result of an operation. 0: No carry or borrow occurred 1: Carry or borrow occurred Note 2 OV Indicates whether overflow occurred during an operation. 0: No overflow occurred 1: Overflow occurred. 1 S Note Indicates whether the result of an operation is negative. 0: Operation result is positive or 0. 1: Operation result is negative. 0 Z Indicates whether operation result is 0. 0: Operation result is not 0. 1: Operation result is 0. Remark Note is explained on the following page. 70 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation result status SAT Maximum positive value exceeded Maximum negative value exceeded Positive (maximum value not exceeded) Negative (maximum value not exceeded) 1 1 Holds value before operation 1 1 0 Flag status OV 0 1 0 1 S Saturated operation result 7FFFFFFFH 80000000H Actual operation result (5) CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction. The current PSW contents are saved to CTPSW. Bits 31 to 26 CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion. 31 CTPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 CTPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) User's Manual U16031EJ4V1UD 71 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. The current PSW contents are saved to DBPSW. These registers can be read or written only in the period between DBTRAP instruction execution and DBRET instruction execution. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion. When the DBRET instruction has been executed, the values of DBPC and DBPSW are restored to the PC and PSW, respectively. 31 DBPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 DBPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). Bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 CTBP 26 25 (Base address) 0 000000 0 After reset 0xxxxxxxH (x: Undefined) 72 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION 3.3 3.3.1 Operating Modes Operating modes The V850E/ME2 has the following operating modes. Mode specification is carried out using the MODE0 and MODE1 pins. (1) Normal operation mode 32-bit mode, 16-bit mode After system reset is cleared, each pin related to the bus interface enters the control mode, the SRAM cycle branches to 0100000H (reset entry address) of the external device (memory), and instruction processing starts. In the 32-bit mode, the bus interface functions as a 32-bit data bus; it functions as a 16-bit data bus in the 16-bit mode. Caution 3.3.2 Be sure to allocate external memory to address 0100000H for correct operation. Operating mode specification The operating mode is specified according to the status of the MODE0 and MODE1 pins. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation. MODE1 L L MODE0 L H Setting prohibited Operating Mode Normal operation mode 32-bit mode 16-bit mode Remarks 32-bit data bus 16-bit data bus Other than above Remark L: Low-level input H: High-level input User's Manual U16031EJ4V1UD 73 CHAPTER 3 CPU FUNCTION 3.4 3.4.1 Address Space CPU address space The CPU of the V850E/ME2 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported. Figure 3-2 shows the CPU address space. Figure 3-2. CPU Address Space CPU address space FFFFFFFFH Data area (4 GB linear) 04000000H 03FFFFFFH Program area (64 MB linear) 00000000H 74 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION 3.4.2 Image A 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address. Figure 3-3 shows the image of the virtual addressing space. Physical address x0000000H can be seen as CPU address 00000000H, and in addition, can be seen as address 10000000H, address 20000000H, ... , address E0000000H, or address F0000000H. Figure 3-3. Images on Address Space CPU address space FFFFFFFFH Image F0000000H EFFFFFFFH Image Physical address space E0000000H DFFFFFFFH Image External memory 20000000H 1FFFFFFFH Internal instruction RAM On-chip peripheral I/O Internal data RAM FFFFFFFH 0000000H Image 10000000H 0FFFFFFFH Image 00000000H User's Manual U16031EJ4V1UD 75 CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of a branch address calculation, the higher 6 bits ignore the carry or borrow. Therefore, the upper-limit address 03FFFFFFH and the lower-limit address 00000000H of the program space become contiguous addresses. Wrap-around refers to a situation like this whereby the upper-limit address and lower-limit address become contiguous. Caution The 32 KB area of 03FFF800H to 03FFFFFFH can be seen as an image of 0FFFF800H to 0FFFFFFFH. Instructions cannot be fetched from this area because it is an on-chip peripheral I/O area, internal data RAM area, or access-prohibited area. Therefore, do not execute any branch address calculation in which the result will reside in any part of this area. 00000001H 00000000H Program space (+) direction 03FFFFFFH 03FFFFFEH Program space ( ) direction (2) Data space The result of an operand address calculation that exceeds 32 bits is ignored. Therefore, the upper-limit address FFFFFFFFH and the lower-limit address 00000000H of the program space are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. 00000001H 00000000H Data space (+) direction FFFFFFFFH FFFFFFFEH Data space ( ) direction 76 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION 3.4.4 Memory map Areas are reserved in the V850E/ME2 as shown in Figure 3-4. Figure 3-4. Memory Map 32-bit mode, 16-bit mode xFFFFFFFH xFFF8000H xFFF7FFFH On-chip peripheral I/O/ internal data RAM area On-chip peripheral I/O area (4 KB) Internal data RAM area (16 KB) Access-prohibited areaNote 2 xFFFFFFFH xFFFF000H xFFFEFFFH xFFFB000H xFFFAFFFH xFFF8000H External memory area x4000000H x3FFFFFFH Note 1 x3FFF000H On-chip peripheral I/O mirror x3FFEFFFH Internal data RAM mirror x3FFB000H x3FFAFFFH Access-prohibited areaNote 2 x3FF8000H x3FF7FFFH External memory area x0100000H x00FFFFFH Program area (64 MB) Internal instruction RAM area (1 MB) x0020000H x001FFFFH x0000000H Internal instruction RAM area (128 KB) Notes 1. 2. Caution Accessing addresses 3FFF000H to 3FFFFFFH is prohibited. FFFFFFFH to access the on-chip peripheral I/O. Specify addresses FFFF000H to The operation is not guaranteed if an access-prohibited area is accessed. External memory access cannot be made to the internal data RAM, internal instruction RAM, and on-chip peripheral I/O areas. User's Manual U16031EJ4V1UD 77 CHAPTER 3 CPU FUNCTION 3.4.5 Area (1) Internal instruction RAM area (a) Memory map 1 MB of internal instruction RAM area, addresses 0000000H to 00FFFFFH, is reserved. 128 KB are provided at addresses 0000000H to 001FFFFH as physical instruction RAM. Caution External memory access cannot be made to addresses 0020000H to 0FFFFFFH. If this area is accessed, the address bus (A0 to A25) outputs a low level, the data bus (D0 to D31) goes into a high-impedance state without outputting anything, and the external bus control signal becomes inactive. 00FFFFFH 0020000H 001FFFFH Internal instruction RAM area (128 KB) 0000000H (b) Interrupt/exception table The V850E/ME2 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is allocated in the internal instruction RAM area. When an interrupt/exception request is acknowledged, execution jumps to the handler address, and the program written in that memory is executed. Table 3-3 shows the sources of interrupts/exceptions, and the corresponding addresses. Table 3-3. Interrupt/Exception Table (1/2) Start Address of Interrupt/Exception Table 00100000H 00000010H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H RESET NMI0 TRAP0n (n = 0 to F) TRAP1n (n = 0 to F) ILGOP/DBG0 INTP10 INTP11 INTP21 INTP22 INTP23 Interrupt/Exception Source Start Address of Interrupt/Exception Table 000000D0H 000000E0H 000000F0H 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H INTP24 INTP25 INTP50 INTP51 INTP52 INTP65 INTP66 INTP67 INTPD0 INTPD1 Interrupt/Exception Source 78 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table (2/2) Start Address of Interrupt/Exception Table 00000170H 00000180H 00000190H 000001A0H 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H 000002C0H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H 00000340H 00000350H 00000360H 00000370H 00000380H 00000390H 000003A0H 000003B0H INTPD2 INTPD3 INTPD4 INTPD5 INTPD6 INTPD7 INTPD8 INTPD9 INTPD10 INTPD11 INTPD12 INTPD13 INTPD14 INTPD15 INTPL0 INTPL1 INTOVC0 INTOVC1 INTOVC2 INTOVC3 INTOVC4 INTOVC5 INTPC00/INTCCC00 INTPC01/INTCCC01 INTPC10/INTCCC10 INTPC11/INTCCC11 INTPC20/INTCCC20 INTPC21/INTCCC21 INTPC30/INTCCC30 INTPC31/INTCCC31 INTCCC40 INTCCC41 INTCCC50 INTCCC51 INTCMD0 INTCMD1 INTCMD2 Interrupt/Exception Source Start Address of Interrupt/Exception Table 000003C0H 000003D0H 000003E0H 000003F0H 00000400H 00000410H 00000420H 00000430H 00000440H 00000450H 00000460H 00000470H 00000480H 00000490H 000004C0H 000004D0H 000004E0H 000004F0H 00000500H 00000510H 00000520H 00000530H 00000540H 00000550H 00000560H 00000570H 00000580H 00000590H 000005A0H 000005B0H 000005C0H 000005D0H 000005E0H 000005F0H 00000600H 00000610H INTCMD3 INTCC100 INTCC101 INTCM100 INTCM101 INTOV10 INTUD10 INTCC110 INTCC111 INTCM110 INTCM111 INTOV11 INTUD11 INTDMA0 INTDMA3 INTCSI30 INTCOVF30 INTCSI31 INTCOVF31 UBTIRE0 UBTIR0 UBTIT0 UBTIF0 UBTITO0 UBTIRE1 UBTIR1 UBTIT1 UBTIF1 UBTITO1 INTAD INTUSB0B INTUSB1B INTUSB2B USBSP2B USBSP4B INTRSUM Interrupt/Exception Source User's Manual U16031EJ4V1UD 79 CHAPTER 3 CPU FUNCTION (2) Internal data RAM area The 16 KB area of addresses FFFB000H to FFFEFFFH is provided as the internal data RAM area. The 16 KB area of 3FFB000H to 3FFEFFFH can be seen as an image of FFFB000H to FFFEFFFH. Cautions 1. External memory access cannot be made to addresses xFFF8000H to xFFFAFFFH and x3FF8000H to x3FFAFFFH. The operation is not guaranteed if external memory access is performed. 2. Do not execute the program in the internal data RAM area. FFFEFFFH Internal data RAM area (16 KB) FFFB000H FFFAFFFH Access-prohibited area FFF8000H 80 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of memory, addresses FFFF000H to FFFFFFFH, are provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFHNote. Note Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. FFFFFFFH On-chip peripheral I/O area (4 KB) FFFF000H On-chip peripheral I/O registers associated with the operating mode specification and the state monitoring for the on-chip peripheral I/O are all memory-mapped to the on-chip peripheral I/O area. Program fetches cannot be executed from this area. Cautions 1. For registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during a read operation, and the lower 8 bits of data are written to the register during a write operation. Do not access an 8-bit register in halfword units. 2. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. Addresses 3FFF000H to 3FFFFFFH cannot be specified as the source/destination address of DMA transfer. Be sure to use addresses FFFF000H to FFFFFFFH for the source/destination address of DMA transfer. (4) External memory area 256 MB are available for external memory area. The lower 64 MB can be used as program/data area and the higher 192 MB as data area. The external memory area is addresses x0100000H to xFDFFFFFH. Access to the external memory area is performed using the chip select signal assigned to each memory block (which is carried out in the CS unit set by the CSC0 and CSC1 registers). Note that the internal instruction RAM, internal data RAM, and on-chip peripheral I/O areas cannot be used as external memory areas. User's Manual U16031EJ4V1UD 81 CHAPTER 3 CPU FUNCTION 3.4.6 Recommended use of address space The architecture of the V850E/ME2 requires that a register that serves as a pointer be secured for address generation in operand data accessing of data space. Operand data access from instruction can be directly executed at the address in this pointer register 32 KB area. However, because the general-purpose registers that can be used as a pointer register are limited, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program size can be saved. In connection with the memory map of the V850E/ME2, the following usage is recommended to enhance the efficiency of pointer operation. (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Therefore, a contiguous 64 MB space, starting from address 00000000H, unconditionally corresponds to the memory map of the program space. (2) Data space To efficiently operate the resources using wrap-around of the data space, a consecutive 16 MB are used as a data space at each of the 4 GB CPU address spaces of 00000000H to 00FFFFFFH and FF000000H to FFFFFFFFH. With the V850E/ME2, a 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. The highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits. (a) Application of wrap-around When R = r0 (zero register) is specified with the LD/ST disp16[R] instruction, an addressing range of 00000000H 32 KB can be referenced with the sign-extended disp16. The zero register (r0) is a register fixed to 0 by the hardware, and eliminates the need for additional registers for the pointer. 0001FFFFH 00007FFFH Internal instruction RAM area (R=) 00000000H FFFFF000H FFFFEFFFH On-chip peripheral I/O area Internal data RAM area FFFFB000H FFFFAFFFH Access-prohibited area FFFF8000H 32 KB 4 KB 16 KB 12 KB 82 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION Figure 3-5. Recommended Memory Map Program space FFFFFFFFH Data space On-chip peripheral I/O FFFFF000H FFFFEFFFH FFFFB000H FFFFAFFFH FFFF8000H FFFF7FFFH Internal data RAM Access prohibitedNote 2 On-chip peripheral I/O xFFFF000H xFFFEFFFH xFFFB000H xFFFAFFFH xFFF8000H xFFF7FFFH xFFFFFFFH Internal data RAM Access prohibitedNote 2 04000000H 03FFFFFFH On-chip peripheral I/ONote 1 03FFF000H 03FFEFFFH 03FFB000H 03FFAFFFH 03FF8000H 03FF7FFFH Internal data RAM Access prohibitedNote 2 External memory External memory Program space 64 MB External memory x0100000H x00FFFFFH Internal instruction RAM 00100000H 000FFFFFH x0020000H x001FFFFH x0000000H 00020000H 0001FFFFH 00000000H Internal instruction RAM Internal instruction RAM Notes 1. 2. Remark This area is access-prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. The operation is not guaranteed if an access-prohibited area is accessed. The arrows indicate the recommended area. User's Manual U16031EJ4V1UD 83 CHAPTER 3 CPU FUNCTION 3.4.7 On-chip peripheral I/O registers (1/26) Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit 8 Bits 16 Bits Undefined Undefined 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH FFH FFH FFH FFH 0002H 02H 00H 03FFH FFH 03H 0000H 00H 00H FFH 00H After Reset Address FFFFF000H FFFFF000H FFFFF001H FFFFF002H FFFFF002H FFFFF003H FFFFF006H FFFFF006H FFFFF007H FFFFF008H FFFFF00AH FFFFF00CH FFFFF00EH FFFFF020H FFFFF020H FFFFF021H FFFFF022H FFFFF022H FFFFF023H FFFFF026H FFFFF026H FFFFF027H FFFFF028H FFFFF02AH FFFFF02CH FFFFF02EH FFFFF040H FFFFF040H FFFFF041H FFFFF042H FFFFF042H FFFFF043H FFFFF046H FFFFF046H FFFFF047H FFFFF048H FFFFF049H Port AL Port ALL Port ALH Port AH Port AHL Port AHH Port DH Port DHL Port DHH Port CS Port CT Port CM Port CD Port AL mode register Port AL mode register L Port AL mode register H Port AH mode register Port AH mode register L Port AH mode register H Port DH mode register Port DH mode register L Port DH mode register H Port CS mode register Port CT mode register Port CM mode register Port CD mode register Port AL mode control register Port AL mode control register L Port AL mode control register H Port AH mode control register Port AH mode control register L Port AH mode control register H Port DH mode control register Port DH mode control register L Port DH mode control register H Port CS mode control register Port CS function control register PAL PALL PALH PAH PAHL PAHH PDH PDHL PDHH PCS PCT PCM PCD PMAL PMALL PMALH PMAH PMAHL PMAHH PMDH PMDHL PMDHH PMCS PMCT PMCM PMCD PMCAL PMCALL PMCALH PMCAH PMCAHL PMCAHH PMCDH PMCDHL PMCDHH PMCCS PFCCS User's Manual U16031EJ4V1UD R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W 84 CHAPTER 3 CPU FUNCTION (2/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF04AH FFFFF04BH FFFFF04CH FFFFF04DH FFFFF04EH FFFFF056H FFFFF056H FFFFF057H FFFFF058H FFFFF060H FFFFF062H FFFFF068H FFFFF06AH FFFFF06EH FFFFF070H FFFFF070H FFFFF071H FFFFF074H FFFFF080H FFFFF082H FFFFF084H FFFFF086H FFFFF088H FFFFF08AH FFFFF08CH FFFFF08EH FFFFF090H FFFFF092H FFFFF094H FFFFF096H FFFFF098H FFFFF09AH FFFFF09CH Port CT mode control register Port CT function control register Port CM mode control register Port CM function control register Port CD mode control register Port DH function control register Port DH function control register L Port DH function control register H Port AL function control register L Chip area select control register 0 Chip area select control register 1 Endian configuration register Cache configuration register System wait control register Instruction cache control register Instruction cache control register L Instruction cache control register H Instruction cache data configuration register DMA source address register 0L DMA source address register 0H DMA destination address register 0L DMA destination address register 0H DMA source address register 1L DMA source address register 1H DMA destination address register 1L DMA destination address register 1H DMA source address register 2L DMA source address register 2H DMA destination address register 2L DMA destination address register 2H DMA source address register 3L DMA source address register 3H DMA destination address register 3L PMCCT PFCCT PMCCM PFCCM PMCCD PFCDH PFCDHL PFCDHH PFCALL CSC0 CSC1 BEC BHC VSWC ICC ICCL ICCH ICD DSA0L DSA0H DDA0L DDA0H DSA1L DSA1H DDA1L DDA1H DSA2L DSA2H DDA2L DDA2H DSA3L DSA3H DDA3L R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits BFH 00H 3DH 00H 0FH 0000H 00H 00H 03H 2C11H 2C11H 0000H 0000H 77H 0003H 03H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note 1 After Reset Note 2 Notes 1. 2. This register is set to 0003H and the tag is automatically initialized when the reset signal becomes active. When initialization of the tag is completed, the register is cleared to 0000H. This register is set to 03H and the tag is automatically initialized when the reset signal becomes active. When initialization of the tag is completed, the register is cleared to 00H. User's Manual U16031EJ4V1UD 85 CHAPTER 3 CPU FUNCTION (3/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF09EH FFFFF0C0H FFFFF0C2H FFFFF0C4H FFFFF0C6H FFFFF0D0H FFFFF0D2H FFFFF0D4H FFFFF0D6H FFFFF0E0H FFFFF0E2H FFFFF0E4H FFFFF0E6H FFFFF100H FFFFF100H FFFFF101H FFFFF102H FFFFF102H FFFFF103H FFFFF104H FFFFF104H FFFFF105H FFFFF106H FFFFF106H FFFFF107H FFFFF108H FFFFF108H FFFFF109H FFFFF10AH FFFFF10AH FFFFF10BH FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH DMA destination address register 3H DMA transfer count register 0 DMA transfer count register 1 DMA transfer count register 2 DMA transfer count register 3 DMA addressing control register 0 DMA addressing control register 1 DMA addressing control register 2 DMA addressing control register 3 DMA channel control register 0 DMA channel control register 1 DMA channel control register 2 DMA channel control register 3 Interrupt mask register 0 Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1 Interrupt mask register 1L Interrupt mask register 1H Interrupt mask register 2 Interrupt mask register 2L Interrupt mask register 2H Interrupt mask register 3 Interrupt mask register 3L Interrupt mask register 3H Interrupt mask register 4 Interrupt mask register 4L Interrupt mask register 4H Interrupt mask register 5 Interrupt mask register 5L Interrupt mask register 5H Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 Interrupt control register 6 DDA3H DBC0 DBC1 DBC2 DBC3 DADC0 DADC1 DADC2 DADC3 DCHC0 DCHC1 DCHC2 DCHC3 IMR0 IMR0L IMR0H IMR1 IMR1L IMR1H IMR2 IMR2L IMR2H IMR3 IMR3L IMR3H IMR4 IMR4L IMR4H IMR5 IMR5L IMR5H P1IC0 P1IC1 P2IC1 P2IC2 P2IC3 P2IC4 P2IC5 User's Manual U16031EJ4V1UD After Reset 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined 0000H 0000H 0000H 0000H 00H 00H 00H 00H FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH 47H 47H 47H 47H 47H 47H 47H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 86 CHAPTER 3 CPU FUNCTION (4/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H FFFFF15AH FFFFF15CH FFFFF15EH FFFFF160H FFFFF162H FFFFF164H FFFFF166H FFFFF168H Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Interrupt control register 16 Interrupt control register 17 Interrupt control register 18 Interrupt control register 19 Interrupt control register 20 Interrupt control register 21 Interrupt control register 22 Interrupt control register 23 Interrupt control register 24 Interrupt control register 25 Interrupt control register 26 Interrupt control register 27 Interrupt control register 28 Interrupt control register 29 Interrupt control register 30 Interrupt control register 31 Interrupt control register 32 Interrupt control register 33 Interrupt control register 34 Interrupt control register 35 Interrupt control register 36 Interrupt control register 37 Interrupt control register 38 Interrupt control register 39 Interrupt control register 40 Interrupt control register 41 Interrupt control register 42 Interrupt control register 43 Interrupt control register 44 P5IC0 P5IC1 P5IC2 P6IC5 P6IC6 P6IC7 PDIC0 PDIC1 PDIC2 PDIC3 PDIC4 PDIC5 PDIC6 PDIC7 PDIC8 PDIC9 PDIC10 PDIC11 PDIC12 PDIC13 PDIC14 PDIC15 PLIC0 PLIC1 OVCIC0 OVCIC1 OVCIC2 OVCIC3 OVCIC4 OVCIC5 CCC0IC0 CCC0IC1 CCC1IC0 CCC1IC1 CCC2IC0 CCC2IC1 CCC3IC0 CCC3IC1 User's Manual U16031EJ4V1UD After Reset 8 Bits 16 Bits 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 87 CHAPTER 3 CPU FUNCTION (5/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF16AH FFFFF16CH FFFFF16EH FFFFF170H FFFFF172H FFFFF174H FFFFF176H FFFFF178H FFFFF17AH FFFFF17CH FFFFF17EH FFFFF180H FFFFF182H FFFFF184H FFFFF186H FFFFF188H FFFFF18AH FFFFF18CH FFFFF18EH FFFFF190H FFFFF192H FFFFF194H FFFFF196H FFFFF198H FFFFF19AH FFFFF19CH FFFFF19EH FFFFF1A0H FFFFF1A2H FFFFF1A4H FFFFF1A6H FFFFF1A8H FFFFF1AAH FFFFF1ACH FFFFF1AEH FFFFF1B0H FFFFF1B2H FFFFF1B4H Interrupt control register 45 Interrupt control register 46 Interrupt control register 47 Interrupt control register 48 Interrupt control register 49 Interrupt control register 50 Interrupt control register 51 Interrupt control register 52 Interrupt control register 53 Interrupt control register 54 Interrupt control register 55 Interrupt control register 56 Interrupt control register 57 Interrupt control register 58 Interrupt control register 59 Interrupt control register 60 Interrupt control register 61 Interrupt control register 62 Interrupt control register 63 Interrupt control register 64 Interrupt control register 65 Interrupt control register 66 Interrupt control register 67 Interrupt control register 68 Interrupt control register 69 Interrupt control register 70 Interrupt control register 71 Interrupt control register 72 Interrupt control register 73 Interrupt control register 74 Interrupt control register 75 Interrupt control register 76 Interrupt control register 77 Interrupt control register 78 Interrupt control register 79 Interrupt control register 80 Interrupt control register 81 Interrupt control register 82 CCC4IC0 CCC4IC1 CCC5IC0 CCC5IC1 CMDIC0 CMDIC1 CMDIC2 CMDIC3 CC10IC0 CC10IC1 CM10IC0 CM10IC1 OV1IC0 UD1IC0 CC11IC0 CC11IC1 CM11IC0 CM11IC1 OV1IC1 UD1IC1 DMAIC0 DMAIC1 DMAIC2 DMAIC3 CSI3IC0 COVF3IC0 CSI3IC1 COVF3IC1 UREIC0 URIC0 UTIC0 UIFIC0 UTOIC0 UREIC1 URIC1 UTIC1 UIFIC1 UTOIC1 User's Manual U16031EJ4V1UD After Reset 8 Bits 16 Bits 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 88 CHAPTER 3 CPU FUNCTION (6/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF1B6H FFFFF1B8H FFFFF1BAH FFFFF1BCH FFFFF1BEH FFFFF1C0H FFFFF1C2H FFFFF1FAH FFFFF1FCH FFFFF1FEH FFFFF200H FFFFF201H FFFFF202H FFFFF210H FFFFF211H FFFFF212H FFFFF213H FFFFF214H FFFFF215H FFFFF216H FFFFF217H FFFFF218H FFFFF219H FFFFF21AH FFFFF21BH FFFFF21CH FFFFF21DH FFFFF21EH FFFFF21FH FFFFF220H FFFFF402H FFFFF404H FFFFF40AH FFFFF40CH FFFFF40EH FFFFF422H FFFFF424H FFFFF42AH Interrupt control register 83 Interrupt control register 84 Interrupt control register 85 Interrupt control register 86 Interrupt control register 87 Interrupt control register 88 Interrupt control register 89 In-service priority register Command register Power-save control register A/D converter mode register 0 A/D converter mode register 1 A/D converter mode register 2 A/D conversion result register 0 A/D conversion result register 0H A/D conversion result register 1 A/D conversion result register 1H A/D conversion result register 2 A/D conversion result register 2H A/D conversion result register 3 A/D conversion result register 3H A/D conversion result register 4 A/D conversion result register 4H A/D conversion result register 5 A/D conversion result register 5H A/D conversion result register 6 A/D conversion result register 6H A/D conversion result register 7 A/D conversion result register 7H ADC trigger select register Port 1 Port 2 Port 5 Port 6 Port 7 Port 1 mode register Port 2 mode register Port 5 mode register ADIC US0BIC US1BIC US2BIC USP2IC USP4IC RSUMIC ISPR PRCMD PSC ADM0 ADM1 ADM2 ADCR0 ADCR0H ADCR1 ADCR1H ADCR2 ADCR2H ADCR3 ADCR3H ADCR4 ADCR4H ADCR5 ADCR5H ADCR6 ADCR6H ADCR7 ADCR7H ADTS P1 P2 P5 P6 P7 PM1 PM2 PM5 User's Manual U16031EJ4V1UD After Reset 8 Bits 16 Bits 47H 47H 47H 47H 47H 47H 47H 00H Undefined 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00H Undefined Undefined Undefined Undefined Undefined FFH FFH FFH R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 89 CHAPTER 3 CPU FUNCTION (7/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF42CH FFFFF42EH FFFFF442H FFFFF444H FFFFF44AH FFFFF44CH FFFFF44EH FFFFF462H FFFFF464H FFFFF46AH FFFFF46CH FFFFF46EH FFFFF480H FFFFF482H FFFFF484H FFFFF486H FFFFF488H FFFFF48AH FFFFF48CH FFFFF48EH FFFFF490H FFFFF492H FFFFF494H FFFFF496H FFFFF498H FFFFF49AH FFFFF49CH FFFFF4A4H FFFFF4A6H FFFFF4ACH FFFFF4AEH FFFFF4B0H FFFFF4B2H FFFFF4B8H FFFFF4BAH Port 6 mode register Port 7 mode register Port 1 mode control register Port 2 mode control register Port 5 mode control register Port 6 mode control register Port 7 mode control register Port 1 function control register Port 2 function control register Port 5 function control register Port 6 function control register Port 7 function control register Bus cycle type configuration register 0 Bus cycle type configuration register 1 Data wait control register 0 Data wait control register 1 Bus cycle control register Address setup wait control register Bus cycle period control register Local bus sizing control register Line buffer control register 0 Line buffer control register 1 DMA flyby transfer wait control register DMA flyby transfer idle control register Bus mode control register Page ROM configuration register Write access synchronization control register SDRAM configuration register 1 SDRAM refresh control register 1 SDRAM configuration register 3 SDRAM refresh control register 3 SDRAM configuration register 4 SDRAM refresh control register 4 SDRAM configuration register 6 SDRAM refresh control register 6 PM6 PM7 PMC1 PMC2 PMC5 PMC6 PMC7 PFC1 PFC2 PFC5 PFC6 PFC7 BCT0 BCT1 DWC0 DWC1 BCC ASC BCP LBS LBC0 LBC1 FWC FIC BMC PRC WAS SCR1 RFS1 SCR3 RFS3 SCR4 RFS4 SCR6 RFS6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits FFH FFH 00H 01H 00H 00H 00H 00H 00H 00H 00H 00H 8888H 8888H 7777H 7777H FFFFH FFFFH 00H 5555H/AAAAHNote 0000H 0000H 7777H 3333H 00H 7000H Undefined 30C0H 0000H 30C0H 0000H 30C0H 0000H 30C0H 0000H After Reset Note 32-bit mode: AAAAH 16-bit mode: 5555H For details of 32-bit mode and 16-bit mode, see 3.3.1 Operating modes. 90 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (8/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF540H FFFFF542H FFFFF544H FFFFF550H FFFFF552H FFFFF554H FFFFF560H FFFFF562H FFFFF564H FFFFF570H FFFFF572H FFFFF574H FFFFF5A0H FFFFF5A2H FFFFF5A4H FFFFF5A6H FFFFF5A8H FFFFF5AAH FFFFF5ABH FFFFF5ACH FFFFF5ADH FFFFF5AEH FFFFF5AFH FFFFF5C0H FFFFF5D0H FFFFF5D2H FFFFF5D4H FFFFF5D6H FFFFF5D8H FFFFF5DAH FFFFF5DBH FFFFF5DCH FFFFF5DDH FFFFF5DEH FFFFF5DFH FFFFF5F0H FFFFF600H FFFFF602H Timer D0 Compare register D0 Timer mode control register D0 Timer D1 Compare register D1 Timer mode control register D1 Timer D2 Compare register D2 Timer mode control register D2 Timer D3 Compare register D3 Timer mode control register D3 Timer ENC10 Compare register 100 Compare register 101 Capture/compare register 100 Capture/compare register 101 Capture/compare control register 10 Timer unit mode register 10 Timer control register 10 Valid edge select register 10 Prescaler mode register 10 Status register 10 Noise elimination width setting register 10 Timer ENC11 Compare register 110 Compare register 111 Capture/compare register 110 Capture/compare register 111 Capture/compare control register 11 Timer unit mode register 11 Timer control register 11 Valid edge select register 11 Prescaler mode register 11 Status register 11 Noise elimination width setting register 11 Timer C0 Capture/compare register C00 TMD0 CMD0 TMCD0 TMD1 CMD1 TMCD1 TMD2 CMD2 TMCD2 TMD3 CMD3 TMCD3 TMENC10 CM100 CM101 CC100 CC101 CCR10 TUM10 TMC10 SESA10 PRM10 STATUS10 NCW10 TMENC11 CM110 CM111 CC110 CC111 CCR11 TUM11 TMC11 SESA11 PRM11 STATUS11 NCW11 TMC0 CCC00 User's Manual U16031EJ4V1UD After Reset 8 Bits 16 Bits 0000H 0000H 00H 0000H 0000H 00H 0000H 0000H 00H 0000H 0000H 00H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 07H 00H 02H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 07H 00H 02H 0000H 0000H R R/W R/W R R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 91 CHAPTER 3 CPU FUNCTION (9/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF604H FFFFF606H FFFFF608H FFFFF609H FFFFF610H FFFFF620H FFFFF622H FFFFF624H FFFFF626H FFFFF628H FFFFF629H FFFFF630H FFFFF640H FFFFF642H FFFFF644H FFFFF646H FFFFF648H FFFFF649H FFFFF650H FFFFF660H FFFFF662H FFFFF664H FFFFF666H FFFFF668H FFFFF669H FFFFF670H FFFFF680H FFFFF682H FFFFF684H FFFFF686H FFFFF688H FFFFF6A0H FFFFF6A2H FFFFF6A4H FFFFF6A6H FFFFF6A8H FFFFF6C0H FFFFF80AH Capture/compare register C01 Timer mode control register C00 Timer mode control register C01 Valid edge select register C0 Noise elimination width setting register C0 Timer C1 Capture/compare register C10 Capture/compare register C11 Timer mode control register C10 Timer mode control register C11 Valid edge select register C1 Noise elimination width setting register C1 Timer C2 Capture/compare register C20 Capture/compare register C21 Timer mode control register C20 Timer mode control register C21 Valid edge select register C2 Noise elimination width setting register C2 Timer C3 Capture/compare register C30 Capture/compare register C31 Timer mode control register C30 Timer mode control register C31 Valid edge select register C3 Noise elimination width setting register C3 Timer C4 Capture/compare register C40 Capture/compare register C41 Timer mode control register C40 Timer mode control register C41 Timer C5 Capture/compare register C50 Capture/compare register C51 Timer mode control register C50 Timer mode control register C51 Oscillation stabilization time select register Internal instruction RAM mode register CCC01 TMCC00 TMCC01 SESC0 NCWC0 TMC1 CCC10 CCC11 TMCC10 TMCC11 SESC1 NCWC1 TMC2 CCC20 CCC21 TMCC20 TMCC21 SESC2 NCWC2 TMC3 CCC30 CCC31 TMCC30 TMCC31 SESC3 NCWC3 TMC4 CCC40 CCC41 TMCC40 TMCC41 TMC5 CCC50 CCC51 TMCC50 TMCC51 OSTS IRAMM R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits 0000H 00H 20H 00H 02H 0000H 0000H 0000H 00H 20H 00H 02H 0000H 0000H 0000H 00H 20H 00H 02H 0000H 0000H 0000H 00H 20H 00H 02H 0000H 0000H 0000H 00H 20H 0000H 0000H 0000H 00H 20H 04H 03H After Reset 92 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (10/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF80CH FFFFF810H FFFFF812H FFFFF814H FFFFF816H FFFFF820H FFFFF822H FFFFF824H FFFFF82CH FFFFF82EH FFFFF836H FFFFF8A0H FFFFF8A8H FFFFFA00H FFFFFA02H FFFFFA04H FFFFFA06H FFFFFA06H FFFFFA08H FFFFFA0AH FFFFFA0BH FFFFFA0CH NMI reset status register DMA trigger factor register 0 DMA trigger factor register 1 DMA trigger factor register 2 DMA trigger factor register 3 Power-save mode register Clock control register Lock register Clock source select register USB clock control register SSCG control register DMA terminal count output control register DMA interface control register UARTB0 control register 0 UARTB0 control register 2 UARTB0 status register UARTB0 receive data register AP UARTB0 receive data register UARTB0 transmit data register UARTB0 FIFO control register 0 UARTB0 FIFO control register 1 UARTB0 FIFO control register 2 Note 2 After Reset 8 Bits 16 Bits 00H 00H 00H 00H 00H 00H 03H 01H 00H 00H Note 1 01H 00H 10H FFFFH 00H 00FFH FFH FFH 00H 00H 0000H 00H 00H 00H 10H 10H FFFFH 00H 00FFH FFH FFH 00H 00H NRS DTFR0 DTFR1 DTFR2 DTFR3 PSMR CKC LOCKR CKS UCKC SSCGC DTOC DIFC UB0CTL0 UB0CTL2 UB0STR UB0RXAP UB0RX UB0TX UB0FIC0 UB0FIC1 UB0FIC2 UB0FIC2L UB0FIC2H UB0FIS0 UB0FIS1 UB1CTL0 UB1CTL2 UB1STR Note 2 R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R W R/W R/W R/W R/W R/W R R R/W R/W R/W R R W R/W R/W FFFFFA0CH UARTB0 FIFO control register 2L FFFFFA0DH UARTB0 FIFO control register 2H FFFFFA0EH FFFFFA0FH FFFFFA20H FFFFFA22H FFFFFA24H FFFFFA26H FFFFFA26H FFFFFA28H FFFFFA2AH FFFFFA2BH UARTB0 FIFO status register 0 UARTB0 FIFO status register 1 UARTB1 control register 0 UARTB1 control register 2 UARTB1 status register UARTB1 receive data register AP UARTB1 receive data register UARTB1 transmit data register UARTB1 FIFO control register 0 UARTB1 FIFO control register 1 UB1RXAP UB1RX UB1TX UB1FIC0 UB1FIC1 Notes 1. 2. For details, see 8.3.3 SSCG control register (SSCGC). This register can be used only in FIFO mode. User's Manual U16031EJ4V1UD 93 CHAPTER 3 CPU FUNCTION (11/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFA2CH FFFFFA2CH FFFFFA2DH FFFFFA2EH FFFFFA2FH FFFFFB00H FFFFFB02H FFFFFB02H FFFFFB03H FFFFFB10H FFFFFB12H FFFFFB12H FFFFFB13H FFFFFC02H UARTB1 FIFO control register 2 UARTB1 FIFO control register 2L UARTB1 FIFO control register 2H UARTB1 FIFO status register 0 UARTB1 FIFO status register 1 PWM control register 0 PWM modulo register 0 PWM modulo register L0 PWM modulo register H0 PWM control register 1 PWM modulo register 1 PWM modulo register L1 PWM modulo register H1 External interrupt falling edge specification register 1 External interrupt falling edge specification register 2 External interrupt falling edge specification register 5 External interrupt falling edge specification register 6 External interrupt falling edge specification register AL External interrupt falling edge specification register DH External interrupt falling edge specification register DHL External interrupt falling edge specification register DHH External interrupt rising edge specification register 1 External interrupt rising edge specification register 2 External interrupt rising edge specification register 5 External interrupt rising edge specification register 6 External interrupt rising edge specification register AL UB1FIC2 UB1FIC2L UB1FIC2H UB1FIS0 UB1FIS1 PWMC0 PWM0 PWML0 PWMH0 PWMC1 PWM1 PWML1 PWMH1 INTF1 R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits 0000H 00H 00H 00H 10H 08H 0000H 00H 00H 08H 0000H 00H 00H 00H After Reset FFFFFC04H INTF2 R/W 00H FFFFFC0AH INTF5 R/W 00H FFFFFC0CH INTF6 R/W 00H FFFFFC10H INTFAL R/W 00H FFFFFC16H INTFDH R/W 0000H FFFFFC16H INTFDHL R/W 00H FFFFFC17H INTFDHH R/W 00H FFFFFC22H INTR1 R/W 03H FFFFFC24H INTR2 R/W 3FH FFFFFC2AH INTR5 R/W 07H FFFFFC2CH INTR6 R/W E0H FFFFFC30H INTRAL R/W 03H 94 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (12/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFC36H External interrupt rising edge specification register DH FFFFFC36H External interrupt rising edge specification register DHL External interrupt rising edge specification register DHH Clocked serial interface mode register 30 Clocked serial interface clock select register 30 Receive data buffer register 30 Receive data buffer register 30L Receive data buffer register 30H Transmit data CSI buffer register 30 Transmit data CSI buffer register 30L Transmit data CSI buffer register 30H CSIBUF status register 30 Transfer data length select register 30 Transfer data number specification register 30 Clocked serial interface mode register 31 Clocked serial interface clock select register 31 Receive data buffer register 31 Receive data buffer register 31L Receive data buffer register 31H Transmit data CSI buffer register 31 Transmit data CSI buffer register 31L Transmit data CSI buffer register 31H CSIBUF status register 31 Transfer data length select register 31 Transfer data number specification register 31 USB function 0 DMA channel select register USB function 0 buffer control register UF0 EP0NAK register UF0 EP0NAKALL register UF0 EPNAK register UF0 EPNAK mask register UF0 SNDSIE register UF0 CLR request register UF0 SET request register UF0 EP status 0 register INTRDHL R/W FFH INTRDH R/W 8 Bits 16 Bits FFFFH After Reset FFFFFC37H INTRDHH R/W FFH FFFFFD00H FFFFFD01H FFFFFD02H FFFFFD02H FFFFFD03H FFFFFD06H FFFFFD06H FFFFFD07H FFFFFD08H FFFFFD09H FFFFFD0CH FFFFFD20H FFFFFD21H FFFFFD22H FFFFFD22H FFFFFD23H FFFFFD26H FFFFFD26H FFFFFD27H FFFFFD28H FFFFFD29H FFFFFD2CH FFFFFDF0H FFFFFDF2H FFFFFE00H FFFFFE01H FFFFFE02H FFFFFE03H FFFFFE04H FFFFFE05H FFFFFE06H FFFFFE07H CSIM30 CSIC30 SIRB30 SIRB30L SIRB30H SFDB30 SFDB30L SFDB30H SFA30 CSIL30 SFN30 CSIM31 CSIC31 SIRB31 SIRB31L SIRB31H SFDB31 SFDB31L SFDB31H SFA31 CSIL31 SFN31 UF0CS UF0BC UF0E0N UF0E0NA UF0EN UF0ENM UF0SDS UF0CLR UF0SET UF0EPS0 R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R 00H 07H 0000H 00H 00H 0000H 00H 00H 20H 00H 00H 00H 07H 0000H 00H 00H 0000H 00H 00H 20H 00H 00H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H User's Manual U16031EJ4V1UD 95 CHAPTER 3 CPU FUNCTION (13/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFE08H FFFFFE09H FFFFFE10H FFFFFE11H FFFFFE12H FFFFFE13H FFFFFE14H FFFFFE17H FFFFFE18H FFFFFE19H FFFFFE1AH FFFFFE1BH FFFFFE1EH FFFFFE1FH FFFFFE20H FFFFFE21H FFFFFE22H FFFFFE26H FFFFFE27H FFFFFE28H FFFFFE30H FFFFFE31H FFFFFE35H FFFFFE37H FFFFFE3AH FFFFFE3CH FFFFFE40H FFFFFE41H FFFFFE42H FFFFFE43H FFFFFE44H FFFFFE45H FFFFFE46H FFFFFE49H FFFFFE4AH FFFFFE80H FFFFFE81H FFFFFE82H UF0 EP status 1 register UF0 EP status 2 register UF0 INT status 0 register UF0 INT status 1 register UF0 INT status 2 register UF0 INT status 3 register UF0 INT status 4 register UF0 INT mask 0 register UF0 INT mask 1 register UF0 INT mask 2 register UF0 INT mask 3 register UF0 INT mask 4 register UF0 INT clear 0 register UF0 INT clear 1 register UF0 INT clear 2 register UF0 INT clear 3 register UF0 INT clear 4 register UF0 INT & DMARQ register UF0 DMA status 0 register UF0 DMA status 1 register UF0 FIFO clear 0 register UF0 FIFO clear 1 register UF0 data end register UF0 GPR register UF0 mode control register UF0 mode status register UF0 active interface number register UF0 active alternative setting register UF0 alternative setting status register UF0 endpoint 1 interface mapping register UF0 endpoint 2 interface mapping register UF0 endpoint 3 interface mapping register UF0 endpoint 4 interface mapping register UF0 endpoint 7 interface mapping register UF0 endpoint 8 interface mapping register UF0 EP0 read register UF0 EP0 length register UF0 EP0 setup register UF0EPS1 UF0EPS2 UF0IS0 UF0IS1 UF0IS2 UF0IS3 UF0IS4 UF0IM0 UF0IM1 UF0IM2 UF0IM3 UF0IM4 UF0IC0 UF0IC1 UF0IC2 UF0IC3 UF0IC4 UF0IDR UF0DMS0 UF0DMS1 UF0FIC0 UF0FIC1 UF0DEND UF0GPR UF0MODC UF0MODS UF0AIFN UF0AAS UF0ASS UF0E1IM UF0E2IM UF0E3IM UF0E4IM UF0E7IM UF0E8IM UF0E0R UF0E0L UF0E0ST User's Manual U16031EJ4V1UD After Reset 8 Bits 16 Bits 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Undefined 00H 00H R R R R R R R R/W R/W R/W R/W R/W W W W W W R/W R R W W R/W W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R R R 96 CHAPTER 3 CPU FUNCTION (14/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFE83H FFFFFE84H FFFFFE85H FFFFFE86H FFFFFE87H FFFFFE88H FFFFFE89H FFFFFE8AH FFFFFE8BH FFFFFEA2H FFFFFEA6H FFFFFEA8H FFFFFEAAH FFFFFEACH FFFFFEAEH FFFFFEB4H FFFFFEB6H FFFFFEC0H FFFFFEC1H FFFFFEC2H FFFFFEC3H FFFFFEC4H FFFFFEC5H FFFFFEC6H FFFFFED0H FFFFFED1H FFFFFED2H FFFFFED3H FFFFFED4H FFFFFED5H FFFFFED6H FFFFFED7H FFFFFED8H FFFFFED9H FFFFFEDAH FFFFFEDBH FFFFFEDCH FFFFFEDDH UF0 EP0 write register UF0 bulk out 1 register UF0 bulk out 1 length register UF0 bulk out 2 register UF0 bulk out 2 length register UF0 bulk in 1 register UF0 bulk in 2 register UF0 interrupt 1 register UF0 interrupt 2 register UF0 device status register L UF0 EP0 status register L UF0 EP1 status register L UF0 EP2 status register L UF0 EP3 status register L UF0 EP4 status register L UF0 EP7 status register L UF0 EP8 status register L UF0 address register UF0 configuration register UF0 interface 0 register UF0 interface 1 register UF0 interface 2 register UF0 interface 3 register UF0 interface 4 register UF0 descriptor length register UF0 device descriptor register 0 UF0 device descriptor register 1 UF0 device descriptor register 2 UF0 device descriptor register 3 UF0 device descriptor register 4 UF0 device descriptor register 5 UF0 device descriptor register 6 UF0 device descriptor register 7 UF0 device descriptor register 8 UF0 device descriptor register 9 UF0 device descriptor register 10 UF0 device descriptor register 11 UF0 device descriptor register 12 UF0E0W UF0BO1 UF0BO1L UF0BO2 UF0BO2L UF0BI1 UF0BI2 UF0INT1 UF0INT2 UF0DSTL UF0E0SL UF0E1SL UF0E2SL UF0E3SL UF0E4SL UF0E7SL UF0E8SL UF0ADRS UF0CNF UF0IF0 UF0IF1 UF0IF2 UF0IF3 UF0IF4 UF0DSCL UF0DD0 UF0DD1 UF0DD2 UF0DD3 UF0DD4 UF0DD5 UF0DD6 UF0DD7 UF0DD8 UF0DD9 UF0DD10 UF0DD11 UF0DD12 User's Manual U16031EJ4V1UD After Reset 8 Bits 16 Bits Undefined Undefined 00H Undefined 00H Undefined Undefined Undefined Undefined 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined W R R R R W W W W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 97 CHAPTER 3 CPU FUNCTION (15/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFEDEH FFFFFEDFH FFFFFEE0H FFFFFEE1H FFFFFEE2H FFFFFEE3H UF0 device descriptor register 13 UF0 device descriptor register 14 UF0 device descriptor register 15 UF0 device descriptor register 16 UF0 device descriptor register 17 UF0 configuration/interface/ endpoint descriptor register 0 UF0 configuration/interface/ endpoint descriptor register 1 UF0 configuration/interface/ endpoint descriptor register 2 UF0 configuration/interface/ endpoint descriptor register 3 UF0 configuration/interface/ endpoint descriptor register 4 UF0 configuration/interface/ endpoint descriptor register 5 UF0 configuration/interface/ endpoint descriptor register 6 UF0 configuration/interface/ endpoint descriptor register 7 UF0 configuration/interface/ endpoint descriptor register 8 UF0 configuration/interface/ endpoint descriptor register 9 UF0 configuration/interface/ endpoint descriptor register 10 UF0 configuration/interface/ endpoint descriptor register 11 UF0 configuration/interface/ endpoint descriptor register 12 UF0 configuration/interface/ endpoint descriptor register 13 UF0 configuration/interface/ endpoint descriptor register 14 UF0 configuration/interface/ endpoint descriptor register 15 UF0 configuration/interface/ endpoint descriptor register 16 UF0 configuration/interface/ endpoint descriptor register 17 UF0 configuration/interface/ endpoint descriptor register 18 UF0DD13 UF0DD14 UF0DD15 UF0DD16 UF0DD17 UF0CIE0 R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined After Reset FFFFFEE4H UF0CIE1 R/W Undefined FFFFFEE5H UF0CIE2 R/W Undefined FFFFFEE6H UF0CIE3 R/W Undefined FFFFFEE7H UF0CIE4 R/W Undefined FFFFFEE8H UF0CIE5 R/W Undefined FFFFFEE9H UF0CIE6 R/W Undefined FFFFFEEAH UF0CIE7 R/W Undefined FFFFFEEBH UF0CIE8 R/W Undefined FFFFFEECH UF0CIE9 R/W Undefined FFFFFEEDH UF0CIE10 R/W Undefined FFFFFEEEH UF0CIE11 R/W Undefined FFFFFEEFH UF0CIE12 R/W Undefined FFFFFEF0H UF0CIE13 R/W Undefined FFFFFEF1H UF0CIE14 R/W Undefined FFFFFEF2H UF0CIE15 R/W Undefined FFFFFEF3H UF0CIE16 R/W Undefined FFFFFEF4H UF0CIE17 R/W Undefined FFFFFEF5H UF0CIE18 R/W Undefined 98 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (16/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFEF6H UF0 configuration/interface/ endpoint descriptor register 19 FFFFFEF7H UF0 configuration/interface/ endpoint descriptor register 20 UF0 configuration/interface/ endpoint descriptor register 21 UF0 configuration/interface/ endpoint descriptor register 22 UF0 configuration/interface/ endpoint descriptor register 23 UF0 configuration/interface/ endpoint descriptor register 24 UF0 configuration/interface/ endpoint descriptor register 25 UF0 configuration/interface/ endpoint descriptor register 26 UF0 configuration/interface/ endpoint descriptor register 27 UF0 configuration/interface/ endpoint descriptor register 28 UF0 configuration/interface/ endpoint descriptor register 29 UF0 configuration/interface/ endpoint descriptor register 30 UF0 configuration/interface/ endpoint descriptor register 31 UF0 configuration/interface/ endpoint descriptor register 32 UF0 configuration/interface/ endpoint descriptor register 33 UF0 configuration/interface/ endpoint descriptor register 34 UF0 configuration/interface/ endpoint descriptor register 35 UF0 configuration/interface/ endpoint descriptor register 36 UF0 configuration/interface/ endpoint descriptor register 37 UF0 configuration/interface/ endpoint descriptor register 38 UF0 configuration/interface/ endpoint descriptor register 39 UF0 configuration/interface/ endpoint descriptor register 40 UF0CIE20 R/W Undefined UF0CIE19 R/W 8 Bits 16 Bits Undefined After Reset FFFFFEF8H UF0CIE21 R/W Undefined FFFFFEF9H UF0CIE22 R/W Undefined FFFFFEFAH UF0CIE23 R/W Undefined FFFFFEFBH UF0CIE24 R/W Undefined FFFFFEFCH UF0CIE25 R/W Undefined FFFFFEFDH UF0CIE26 R/W Undefined FFFFFEFEH UF0CIE27 R/W Undefined FFFFFEFFH UF0CIE28 R/W Undefined FFFFFF00H UF0CIE29 R/W Undefined FFFFFF01H UF0CIE30 R/W Undefined FFFFFF02H UF0CIE31 R/W Undefined FFFFFF03H UF0CIE32 R/W Undefined FFFFFF04H UF0CIE33 R/W Undefined FFFFFF05H UF0CIE34 R/W Undefined FFFFFF06H UF0CIE35 R/W Undefined FFFFFF07H UF0CIE36 R/W Undefined FFFFFF08H UF0CIE37 R/W Undefined FFFFFF09H UF0CIE38 R/W Undefined FFFFFF0AH UF0CIE39 R/W Undefined FFFFFF0BH UF0CIE40 R/W Undefined User's Manual U16031EJ4V1UD 99 CHAPTER 3 CPU FUNCTION (17/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFF0CH UF0 configuration/interface/ endpoint descriptor register 41 FFFFFF0DH UF0 configuration/interface/ endpoint descriptor register 42 UF0 configuration/interface/ endpoint descriptor register 43 UF0 configuration/interface/ endpoint descriptor register 44 UF0 configuration/interface/ endpoint descriptor register 45 UF0 configuration/interface/ endpoint descriptor register 46 UF0 configuration/interface/ endpoint descriptor register 47 UF0 configuration/interface/ endpoint descriptor register 48 UF0 configuration/interface/ endpoint descriptor register 49 UF0 configuration/interface/ endpoint descriptor register 50 UF0 configuration/interface/ endpoint descriptor register 51 UF0 configuration/interface/ endpoint descriptor register 52 UF0 configuration/interface/ endpoint descriptor register 53 UF0 configuration/interface/ endpoint descriptor register 54 UF0 configuration/interface/ endpoint descriptor register 55 UF0 configuration/interface/ endpoint descriptor register 56 UF0 configuration/interface/ endpoint descriptor register 57 UF0 configuration/interface/ endpoint descriptor register 58 UF0 configuration/interface/ endpoint descriptor register 59 UF0 configuration/interface/ endpoint descriptor register 60 UF0 configuration/interface/ endpoint descriptor register 61 UF0 configuration/interface/ endpoint descriptor register 62 UF0CIE42 R/W Undefined UF0CIE41 R/W 8 Bits 16 Bits Undefined After Reset FFFFFF0EH UF0CIE43 R/W Undefined FFFFFF0FH UF0CIE44 R/W Undefined FFFFFF10H UF0CIE45 R/W Undefined FFFFFF11H UF0CIE46 R/W Undefined FFFFFF12H UF0CIE47 R/W Undefined FFFFFF13H UF0CIE48 R/W Undefined FFFFFF14H UF0CIE49 R/W Undefined FFFFFF15H UF0CIE50 R/W Undefined FFFFFF16H UF0CIE51 R/W Undefined FFFFFF17H UF0CIE52 R/W Undefined FFFFFF18H UF0CIE53 R/W Undefined FFFFFF19H UF0CIE54 R/W Undefined FFFFFF1AH UF0CIE55 R/W Undefined FFFFFF1BH UF0CIE56 R/W Undefined FFFFFF1CH UF0CIE57 R/W Undefined FFFFFF1DH UF0CIE58 R/W Undefined FFFFFF1EH UF0CIE59 R/W Undefined FFFFFF1FH UF0CIE60 R/W Undefined FFFFFF20H UF0CIE61 R/W Undefined FFFFFF21H UF0CIE62 R/W Undefined 100 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (18/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFF22H UF0 configuration/interface/ endpoint descriptor register 63 FFFFFF23H UF0 configuration/interface/ endpoint descriptor register 64 UF0 configuration/interface/ endpoint descriptor register 65 UF0 configuration/interface/ endpoint descriptor register 66 UF0 configuration/interface/ endpoint descriptor register 67 UF0 configuration/interface/ endpoint descriptor register 68 UF0 configuration/interface/ endpoint descriptor register 69 UF0 configuration/interface/ endpoint descriptor register 70 UF0 configuration/interface/ endpoint descriptor register 71 UF0 configuration/interface/ endpoint descriptor register 72 UF0 configuration/interface/ endpoint descriptor register 73 UF0 configuration/interface/ endpoint descriptor register 74 UF0 configuration/interface/ endpoint descriptor register 75 UF0 configuration/interface/ endpoint descriptor register 76 UF0 configuration/interface/ endpoint descriptor register 77 UF0 configuration/interface/ endpoint descriptor register 78 UF0 configuration/interface/ endpoint descriptor register 79 UF0 configuration/interface/ endpoint descriptor register 80 UF0 configuration/interface/ endpoint descriptor register 81 UF0 configuration/interface/ endpoint descriptor register 82 UF0 configuration/interface/ endpoint descriptor register 83 UF0 configuration/interface/ endpoint descriptor register 84 UF0CIE64 R/W Undefined UF0CIE63 R/W 8 Bits 16 Bits Undefined After Reset FFFFFF24H UF0CIE65 R/W Undefined FFFFFF25H UF0CIE66 R/W Undefined FFFFFF26H UF0CIE67 R/W Undefined FFFFFF27H UF0CIE68 R/W Undefined FFFFFF28H UF0CIE69 R/W Undefined FFFFFF29H UF0CIE70 R/W Undefined FFFFFF2AH UF0CIE71 R/W Undefined FFFFFF2BH UF0CIE72 R/W Undefined FFFFFF2CH UF0CIE73 R/W Undefined FFFFFF2DH UF0CIE74 R/W Undefined FFFFFF2EH UF0CIE75 R/W Undefined FFFFFF2FH UF0CIE76 R/W Undefined FFFFFF30H UF0CIE77 R/W Undefined FFFFFF31H UF0CIE78 R/W Undefined FFFFFF32H UF0CIE79 R/W Undefined FFFFFF33H UF0CIE80 R/W Undefined FFFFFF34H UF0CIE81 R/W Undefined FFFFFF35H UF0CIE82 R/W Undefined FFFFFF36H UF0CIE83 R/W Undefined FFFFFF37H UF0CIE84 R/W Undefined User's Manual U16031EJ4V1UD 101 CHAPTER 3 CPU FUNCTION (19/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFF38H UF0 configuration/interface/ endpoint descriptor register 85 FFFFFF39H UF0 configuration/interface/ endpoint descriptor register 86 UF0 configuration/interface/ endpoint descriptor register 87 UF0 configuration/interface/ endpoint descriptor register 88 UF0 configuration/interface/ endpoint descriptor register 89 UF0 configuration/interface/ endpoint descriptor register 90 UF0 configuration/interface/ endpoint descriptor register 91 UF0 configuration/interface/ endpoint descriptor register 92 UF0 configuration/interface/ endpoint descriptor register 93 UF0 configuration/interface/ endpoint descriptor register 94 UF0 configuration/interface/ endpoint descriptor register 95 UF0 configuration/interface/ endpoint descriptor register 96 UF0 configuration/interface/ endpoint descriptor register 97 UF0 configuration/interface/ endpoint descriptor register 98 UF0 configuration/interface/ endpoint descriptor register 99 UF0 configuration/interface/ endpoint descriptor register 100 UF0 configuration/interface/ endpoint descriptor register 101 UF0 configuration/interface/ endpoint descriptor register 102 UF0 configuration/interface/ endpoint descriptor register 103 UF0 configuration/interface/ endpoint descriptor register 104 UF0 configuration/interface/ endpoint descriptor register 105 UF0 configuration/interface/ endpoint descriptor register 106 UF0CIE86 R/W Undefined UF0CIE85 R/W 8 Bits 16 Bits Undefined After Reset FFFFFF3AH UF0CIE87 R/W Undefined FFFFFF3BH UF0CIE88 R/W Undefined FFFFFF3CH UF0CIE89 R/W Undefined FFFFFF3DH UF0CIE90 R/W Undefined FFFFFF3EH UF0CIE91 R/W Undefined FFFFFF3FH UF0CIE92 R/W Undefined FFFFFF40H UF0CIE93 R/W Undefined FFFFFF41H UF0CIE94 R/W Undefined FFFFFF42H UF0CIE95 R/W Undefined FFFFFF43H UF0CIE96 R/W Undefined FFFFFF44H UF0CIE97 R/W Undefined FFFFFF45H UF0CIE98 R/W Undefined FFFFFF46H UF0CIE99 R/W Undefined FFFFFF47H UF0CIE100 R/W Undefined FFFFFF48H UF0CIE101 R/W Undefined FFFFFF49H UF0CIE102 R/W Undefined FFFFFF4AH UF0CIE103 R/W Undefined FFFFFF4BH UF0CIE104 R/W Undefined FFFFFF4CH UF0CIE105 R/W Undefined FFFFFF4DH UF0CIE106 R/W Undefined 102 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (20/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFF4EH UF0 configuration/interface/ endpoint descriptor register 107 FFFFFF4FH UF0 configuration/interface/ endpoint descriptor register 108 UF0 configuration/interface/ endpoint descriptor register 109 UF0 configuration/interface/ endpoint descriptor register 110 UF0 configuration/interface/ endpoint descriptor register 111 UF0 configuration/interface/ endpoint descriptor register 112 UF0 configuration/interface/ endpoint descriptor register 113 UF0 configuration/interface/ endpoint descriptor register 114 UF0 configuration/interface/ endpoint descriptor register 115 UF0 configuration/interface/ endpoint descriptor register 116 UF0 configuration/interface/ endpoint descriptor register 117 UF0 configuration/interface/ endpoint descriptor register 118 UF0 configuration/interface/ endpoint descriptor register 119 UF0 configuration/interface/ endpoint descriptor register 120 UF0 configuration/interface/ endpoint descriptor register 121 UF0 configuration/interface/ endpoint descriptor register 122 UF0 configuration/interface/ endpoint descriptor register 123 UF0 configuration/interface/ endpoint descriptor register 124 UF0 configuration/interface/ endpoint descriptor register 125 UF0 configuration/interface/ endpoint descriptor register 126 UF0 configuration/interface/ endpoint descriptor register 127 UF0 configuration/interface/ endpoint descriptor register 128 UF0CIE108 R/W Undefined UF0CIE107 R/W 8 Bits 16 Bits Undefined After Reset FFFFFF50H UF0CIE109 R/W Undefined FFFFFF51H UF0CIE110 R/W Undefined FFFFFF52H UF0CIE111 R/W Undefined FFFFFF53H UF0CIE112 R/W Undefined FFFFFF54H UF0CIE113 R/W Undefined FFFFFF55H UF0CIE114 R/W Undefined FFFFFF56H UF0CIE115 R/W Undefined FFFFFF57H UF0CIE116 R/W Undefined FFFFFF58H UF0CIE117 R/W Undefined FFFFFF59H UF0CIE118 R/W Undefined FFFFFF5AH UF0CIE119 R/W Undefined FFFFFF5BH UF0CIE120 R/W Undefined FFFFFF5CH UF0CIE121 R/W Undefined FFFFFF5DH UF0CIE122 R/W Undefined FFFFFF5EH UF0CIE123 R/W Undefined FFFFFF5FH UF0CIE124 R/W Undefined FFFFFF60H UF0CIE125 R/W Undefined FFFFFF61H UF0CIE126 R/W Undefined FFFFFF62H UF0CIE127 R/W Undefined FFFFFF63H UF0CIE128 R/W Undefined User's Manual U16031EJ4V1UD 103 CHAPTER 3 CPU FUNCTION (21/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFF64H UF0 configuration/interface/ endpoint descriptor register 129 FFFFFF65H UF0 configuration/interface/ endpoint descriptor register 130 UF0 configuration/interface/ endpoint descriptor register 131 UF0 configuration/interface/ endpoint descriptor register 132 UF0 configuration/interface/ endpoint descriptor register 133 UF0 configuration/interface/ endpoint descriptor register 134 UF0 configuration/interface/ endpoint descriptor register 135 UF0 configuration/interface/ endpoint descriptor register 136 UF0 configuration/interface/ endpoint descriptor register 137 UF0 configuration/interface/ endpoint descriptor register 138 UF0 configuration/interface/ endpoint descriptor register 139 UF0 configuration/interface/ endpoint descriptor register 140 UF0 configuration/interface/ endpoint descriptor register 141 UF0 configuration/interface/ endpoint descriptor register 142 UF0 configuration/interface/ endpoint descriptor register 143 UF0 configuration/interface/ endpoint descriptor register 144 UF0 configuration/interface/ endpoint descriptor register 145 UF0 configuration/interface/ endpoint descriptor register 146 UF0 configuration/interface/ endpoint descriptor register 147 UF0 configuration/interface/ endpoint descriptor register 148 UF0 configuration/interface/ endpoint descriptor register 149 UF0 configuration/interface/ endpoint descriptor register 150 UF0CIE130 R/W Undefined UF0CIE129 R/W 8 Bits 16 Bits Undefined After Reset FFFFFF66H UF0CIE131 R/W Undefined FFFFFF67H UF0CIE132 R/W Undefined FFFFFF68H UF0CIE133 R/W Undefined FFFFFF69H UF0CIE134 R/W Undefined FFFFFF6AH UF0CIE135 R/W Undefined FFFFFF6BH UF0CIE136 R/W Undefined FFFFFF6CH UF0CIE137 R/W Undefined FFFFFF6DH UF0CIE138 R/W Undefined FFFFFF6EH UF0CIE139 R/W Undefined FFFFFF6FH UF0CIE140 R/W Undefined FFFFFF70H UF0CIE141 R/W Undefined FFFFFF71H UF0CIE142 R/W Undefined FFFFFF72H UF0CIE143 R/W Undefined FFFFFF73H UF0CIE144 R/W Undefined FFFFFF74H UF0CIE145 R/W Undefined FFFFFF75H UF0CIE146 R/W Undefined FFFFFF76H UF0CIE147 R/W Undefined FFFFFF77H UF0CIE148 R/W Undefined FFFFFF78H UF0CIE149 R/W Undefined FFFFFF79H UF0CIE150 R/W Undefined 104 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (22/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFF7AH UF0 configuration/interface/ endpoint descriptor register 151 FFFFFF7BH UF0 configuration/interface/ endpoint descriptor register 152 UF0 configuration/interface/ endpoint descriptor register 153 UF0 configuration/interface/ endpoint descriptor register 154 UF0 configuration/interface/ endpoint descriptor register 155 UF0 configuration/interface/ endpoint descriptor register 156 UF0 configuration/interface/ endpoint descriptor register 157 UF0 configuration/interface/ endpoint descriptor register 158 UF0 configuration/interface/ endpoint descriptor register 159 UF0 configuration/interface/ endpoint descriptor register 160 UF0 configuration/interface/ endpoint descriptor register 161 UF0 configuration/interface/ endpoint descriptor register 162 UF0 configuration/interface/ endpoint descriptor register 163 UF0 configuration/interface/ endpoint descriptor register 164 UF0 configuration/interface/ endpoint descriptor register 165 UF0 configuration/interface/ endpoint descriptor register 166 UF0 configuration/interface/ endpoint descriptor register 167 UF0 configuration/interface/ endpoint descriptor register 168 UF0 configuration/interface/ endpoint descriptor register 169 UF0 configuration/interface/ endpoint descriptor register 170 UF0 configuration/interface/ endpoint descriptor register 171 UF0 configuration/interface/ endpoint descriptor register 172 UF0CIE152 R/W Undefined UF0CIE151 R/W 8 Bits 16 Bits Undefined After Reset FFFFFF7CH UF0CIE153 R/W Undefined FFFFFF7DH UF0CIE154 R/W Undefined FFFFFF7EH UF0CIE155 R/W Undefined FFFFFF7FH UF0CIE156 R/W Undefined FFFFFF80H UF0CIE157 R/W Undefined FFFFFF81H UF0CIE158 R/W Undefined FFFFFF82H UF0CIE159 R/W Undefined FFFFFF83H UF0CIE160 R/W Undefined FFFFFF84H UF0CIE161 R/W Undefined FFFFFF85H UF0CIE162 R/W Undefined FFFFFF86H UF0CIE163 R/W Undefined FFFFFF87H UF0CIE164 R/W Undefined FFFFFF88H UF0CIE165 R/W Undefined FFFFFF89H UF0CIE166 R/W Undefined FFFFFF8AH UF0CIE167 R/W Undefined FFFFFF8BH UF0CIE168 R/W Undefined FFFFFF8CH UF0CIE169 R/W Undefined FFFFFF8DH UF0CIE170 R/W Undefined FFFFFF8EH UF0CIE171 R/W Undefined FFFFFF8FH UF0CIE172 R/W Undefined User's Manual U16031EJ4V1UD 105 CHAPTER 3 CPU FUNCTION (23/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFF90H UF0 configuration/interface/ endpoint descriptor register 173 FFFFFF91H UF0 configuration/interface/ endpoint descriptor register 174 UF0 configuration/interface/ endpoint descriptor register 175 UF0 configuration/interface/ endpoint descriptor register 176 UF0 configuration/interface/ endpoint descriptor register 177 UF0 configuration/interface/ endpoint descriptor register 178 UF0 configuration/interface/ endpoint descriptor register 179 UF0 configuration/interface/ endpoint descriptor register 180 UF0 configuration/interface/ endpoint descriptor register 181 UF0 configuration/interface/ endpoint descriptor register 182 UF0 configuration/interface/ endpoint descriptor register 183 UF0 configuration/interface/ endpoint descriptor register 184 UF0 configuration/interface/ endpoint descriptor register 185 UF0 configuration/interface/ endpoint descriptor register 186 UF0 configuration/interface/ endpoint descriptor register 187 UF0 configuration/interface/ endpoint descriptor register 188 UF0 configuration/interface/ endpoint descriptor register 189 UF0 configuration/interface/ endpoint descriptor register 190 UF0 configuration/interface/ endpoint descriptor register 191 UF0 configuration/interface/ endpoint descriptor register 192 UF0 configuration/interface/ endpoint descriptor register 193 UF0 configuration/interface/ endpoint descriptor register 194 UF0CIE174 R/W Undefined UF0CIE173 R/W 8 Bits 16 Bits Undefined After Reset FFFFFF92H UF0CIE175 R/W Undefined FFFFFF93H UF0CIE176 R/W Undefined FFFFFF94H UF0CIE177 R/W Undefined FFFFFF95H UF0CIE178 R/W Undefined FFFFFF96H UF0CIE179 R/W Undefined FFFFFF97H UF0CIE180 R/W Undefined FFFFFF98H UF0CIE181 R/W Undefined FFFFFF99H UF0CIE182 R/W Undefined FFFFFF9AH UF0CIE183 R/W Undefined FFFFFF9BH UF0CIE184 R/W Undefined FFFFFF9CH UF0CIE185 R/W Undefined FFFFFF9DH UF0CIE186 R/W Undefined FFFFFF9EH UF0CIE187 R/W Undefined FFFFFF9FH UF0CIE188 R/W Undefined FFFFFFA0H UF0CIE189 R/W Undefined FFFFFFA1H UF0CIE190 R/W Undefined FFFFFFA2H UF0CIE191 R/W Undefined FFFFFFA3H UF0CIE192 R/W Undefined FFFFFFA4H UF0CIE193 R/W Undefined FFFFFFA5H UF0CIE194 R/W Undefined 106 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (24/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFFA6H UF0 configuration/interface/ endpoint descriptor register 195 FFFFFFA7H UF0 configuration/interface/ endpoint descriptor register 196 UF0 configuration/interface/ endpoint descriptor register 197 UF0 configuration/interface/ endpoint descriptor register 198 UF0 configuration/interface/ endpoint descriptor register 199 UF0 configuration/interface/ endpoint descriptor register 200 UF0 configuration/interface/ endpoint descriptor register 201 UF0 configuration/interface/ endpoint descriptor register 202 UF0 configuration/interface/ endpoint descriptor register 203 UF0 configuration/interface/ endpoint descriptor register 204 UF0 configuration/interface/ endpoint descriptor register 205 UF0 configuration/interface/ endpoint descriptor register 206 UF0 configuration/interface/ endpoint descriptor register 207 UF0 configuration/interface/ endpoint descriptor register 208 UF0 configuration/interface/ endpoint descriptor register 209 UF0 configuration/interface/ endpoint descriptor register 210 UF0 configuration/interface/ endpoint descriptor register 211 UF0 configuration/interface/ endpoint descriptor register 212 UF0 configuration/interface/ endpoint descriptor register 213 UF0 configuration/interface/ endpoint descriptor register 214 UF0 configuration/interface/ endpoint descriptor register 215 UF0 configuration/interface/ endpoint descriptor register 216 UF0CIE196 R/W Undefined UF0CIE195 R/W 8 Bits 16 Bits Undefined After Reset FFFFFFA8H UF0CIE197 R/W Undefined FFFFFFA9H UF0CIE198 R/W Undefined FFFFFFAAH UF0CIE199 R/W Undefined FFFFFFABH UF0CIE200 R/W Undefined FFFFFFACH UF0CIE201 R/W Undefined FFFFFFADH UF0CIE202 R/W Undefined FFFFFFAEH UF0CIE203 R/W Undefined FFFFFFAFH UF0CIE204 R/W Undefined FFFFFFB0H UF0CIE205 R/W Undefined FFFFFFB1H UF0CIE206 R/W Undefined FFFFFFB2H UF0CIE207 R/W Undefined FFFFFFB3H UF0CIE208 R/W Undefined FFFFFFB4H UF0CIE209 R/W Undefined FFFFFFB5H UF0CIE210 R/W Undefined FFFFFFB6H UF0CIE211 R/W Undefined FFFFFFB7H UF0CIE212 R/W Undefined FFFFFFB8H UF0CIE213 R/W Undefined FFFFFFB9H UF0CIE214 R/W Undefined FFFFFFBAH UF0CIE215 R/W Undefined FFFFFFBBH UF0CIE216 R/W Undefined User's Manual U16031EJ4V1UD 107 CHAPTER 3 CPU FUNCTION (25/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFFBCH UF0 configuration/interface/ endpoint descriptor register 217 FFFFFFBDH UF0 configuration/interface/ endpoint descriptor register 218 UF0 configuration/interface/ endpoint descriptor register 219 UF0 configuration/interface/ endpoint descriptor register 220 UF0 configuration/interface/ endpoint descriptor register 221 UF0 configuration/interface/ endpoint descriptor register 222 UF0 configuration/interface/ endpoint descriptor register 223 UF0 configuration/interface/ endpoint descriptor register 224 UF0 configuration/interface/ endpoint descriptor register 225 UF0 configuration/interface/ endpoint descriptor register 226 UF0 configuration/interface/ endpoint descriptor register 227 UF0 configuration/interface/ endpoint descriptor register 228 UF0 configuration/interface/ endpoint descriptor register 229 UF0 configuration/interface/ endpoint descriptor register 230 UF0 configuration/interface/ endpoint descriptor register 231 UF0 configuration/interface/ endpoint descriptor register 232 UF0 configuration/interface/ endpoint descriptor register 233 UF0 configuration/interface/ endpoint descriptor register 234 UF0 configuration/interface/ endpoint descriptor register 235 UF0 configuration/interface/ endpoint descriptor register 236 UF0 configuration/interface/ endpoint descriptor register 237 UF0 configuration/interface/ endpoint descriptor register 238 UF0CIE218 R/W Undefined UF0CIE217 R/W 8 Bits 16 Bits Undefined After Reset FFFFFFBEH UF0CIE219 R/W Undefined FFFFFFBFH UF0CIE220 R/W Undefined FFFFFFC0H UF0CIE221 R/W Undefined FFFFFFC1H UF0CIE222 R/W Undefined FFFFFFC2H UF0CIE223 R/W Undefined FFFFFFC3H UF0CIE224 R/W Undefined FFFFFFC4H UF0CIE225 R/W Undefined FFFFFFC5H UF0CIE226 R/W Undefined FFFFFFC6H UF0CIE227 R/W Undefined FFFFFFC7H UF0CIE228 R/W Undefined FFFFFFC8H UF0CIE229 R/W Undefined FFFFFFC9H UF0CIE230 R/W Undefined FFFFFFCAH UF0CIE231 R/W Undefined FFFFFFCBH UF0CIE232 R/W Undefined FFFFFFCCH UF0CIE233 R/W Undefined FFFFFFCDH UF0CIE234 R/W Undefined FFFFFFCEH UF0CIE235 R/W Undefined FFFFFFCFH UF0CIE236 R/W Undefined FFFFFFD0H UF0CIE237 R/W Undefined FFFFFFD1H UF0CIE238 R/W Undefined 108 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION (26/26) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFFD2H UF0 configuration/interface/ endpoint descriptor register 239 FFFFFFD3H UF0 configuration/interface/ endpoint descriptor register 240 UF0 configuration/interface/ endpoint descriptor register 241 UF0 configuration/interface/ endpoint descriptor register 242 UF0 configuration/interface/ endpoint descriptor register 243 UF0 configuration/interface/ endpoint descriptor register 244 UF0 configuration/interface/ endpoint descriptor register 245 UF0 configuration/interface/ endpoint descriptor register 246 UF0 configuration/interface/ endpoint descriptor register 247 UF0 configuration/interface/ endpoint descriptor register 248 UF0 configuration/interface/ endpoint descriptor register 249 UF0 configuration/interface/ endpoint descriptor register 250 UF0 configuration/interface/ endpoint descriptor register 251 UF0 configuration/interface/ endpoint descriptor register 252 UF0 configuration/interface/ endpoint descriptor register 253 UF0 configuration/interface/ endpoint descriptor register 254 UF0 configuration/interface/ endpoint descriptor register 255 UF0CIE240 R/W Undefined UF0CIE239 R/W 8 Bits 16 Bits Undefined After Reset FFFFFFD4H UF0CIE241 R/W Undefined FFFFFFD5H UF0CIE242 R/W Undefined FFFFFFD6H UF0CIE243 R/W Undefined FFFFFFD7H UF0CIE244 R/W Undefined FFFFFFD8H UF0CIE245 R/W Undefined FFFFFFD9H UF0CIE246 R/W Undefined FFFFFFDAH UF0CIE247 R/W Undefined FFFFFFDBH UF0CIE248 R/W Undefined FFFFFFDCH UF0CIE249 R/W Undefined FFFFFFDDH UF0CIE250 R/W Undefined FFFFFFDEH UF0CIE251 R/W Undefined FFFFFFDFH UF0CIE252 R/W Undefined FFFFFFE0H UF0CIE253 R/W Undefined FFFFFFE1H UF0CIE254 R/W Undefined FFFFFFE2H UF0CIE255 R/W Undefined User's Manual U16031EJ4V1UD 109 CHAPTER 3 CPU FUNCTION 3.4.8 Specific registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The V850E/ME2 has four specific registers, the power-save control register (PSC) (see 8.6.2 (3) Power-save control register (PSC)), clock control register (CKC) (see 8.3.1 Clock control register (CKC)), clock source select register (CKS) (see 8.3.2 Clock source select register (CKS)), and SSCG control register (SSCGC) (see 8.3.3 SSCG control register (SSCGC)). Disable DMA transfer when writing to a specific register. There is also the command register (PRCMD), a protection register supporting write operations for specific registers to avoid an unexpected stoppage of the application system due to erroneous program execution (see 8.6.2 (2) Command register (PRCMD)). 3.4.9 System wait control register (VSWC) The VSWC register is a register that controls the bus access wait for the on-chip peripheral I/O registers. Access to on-chip peripheral I/O registers is made in 3 clocks (without wait), however, in the V850E/ME2 waits may be required depending on the operation frequency. Set the values described in the table below to the VSWC in accordance with the operation frequency used. This register can be read or written in 1-bit or 8-bit units (address: FFFFF06EH, initial value: 77H). Operation Frequency (fX) 10.00 MHz fX 25.00 MHz 25.00 MHz < fX 34.00 MHz 34.00 MHz < fX 68.00 MHz 68.00 MHz < fX 75.00 MHz 75.00 MHz < fX 103.00 MHz 103.00 MHz < fX 125.00 MHz 125.00 MHz < fX 150.00 MHz Number of Waits 0 1 2 3 4 5 6 VSWC Setting Value 00H 10H 11H 12H 22H 23H 33H Remark If the timing of changing a count value contend with the timing of accessing a register when accessing a register having status flags that indicate the status of the on-chip peripheral functions (such as UBnSTR) or a register that indicates the count value of a timer (such as TMCn), the register access is retried. As a result, it may take a longer time to access an on-chip peripheral I/O register. 110 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION 3.4.10 Initialization sequence Initialize the V850E/ME2 in the following sequence. <1> Automatically branch to address 100000H after reset is cleared Set the following registers that affect the external bus access performance using the program allocated at address 100000H. Execution automatically branches to 100000H when the reset signal is input in the power-on status. * System wait control register (VSWC) Setting of a wait cycle for accessing the on-chip peripheral I/O * Data wait control registers 0 and 1 (DWC0 and DWC1) Setting of a data wait cycle of the external bus * Address setup wait control register (ASC) Setting of an address setup wait cycle of the external bus * Bus cycle control register (BCC) Setting of an idle state of the external bus As necessary, set chip area select control registers 0 and 1 (CSC0 and CSC1), bus cycle type configuration registers 0 and 1 (BCT0 and BCT1), the local bus sizing control register (LBS), the endian configuration register (BEC), line buffer control registers 0 and 1 (LBC0 and LBC1), the page ROM configuration register (PRC), port DH function control register (PFCDH), and port CS function control register (PFCCS). Cautions 1. Disable all interrupts from when the reset signal is cleared until when the program code is completely transferred to the internal instruction RAM (while steps <1> to <3> of the initialization sequence are being executed). Maskable interrupts are masked by default and do not have to be disabled. 2. Set SDRAM configuration registers 1, 3, 4, and 6 (SCR1, SCR3, SCR4, and SCR6) after the processing of step <2>. <2> Checking LOCK bit of lock register (LOCKR) After setting the registers in <1> above, check whether the LOCK bit of the LOCKR register is cleared to 0 (PLL is locked), and set the registers as follows. (i) System wait control register (VSWC) Set to x7H (x: Value set in <1>) For example, if 11H is set in <1>, set 17H here. (ii) Bus mode control register (BMC) Set the frequency division value of the external bus. (iii) System wait control register (VSWC) Re-set the value set in <1>. (iv) Clock control register (CKC) Set the internal system clock frequency (fCLK) division value. (v) Clock source select register (CKS) Switch from OSC output to SSCG output (switch the clock supply to the CPU from the input frequency to the X1 and X2 pins to the frequency multiplied by 8 by the PLL). Remark The CKC and CKS registers must be rewritten in a special sequence because they are specific registers. User's Manual U16031EJ4V1UD 111 CHAPTER 3 CPU FUNCTION <3> Transferring program code to internal instruction RAM Transfer the program code to the internal instruction RAM by program processing or using the DMA function. When using the DMA function, check the completion of DMA transfer by polling bit 7 (DMAIFn) of the DMA interrupt control register (DMAICn), without using the DMA transfer end interrupt (INTDMAn) (n = 0 to 3). After transferring the program code, set the internal instruction RAM in the read mode using the following procedure. (i) Set the read mode by using (clearing to 0) the IRAMM0 bit of the internal instruction RAM mode register (IRAMM). Note that the setting of the IRAMM0 bit must not be changed before it is cleared here. (ii) After clearing the IRAMM0 bit of the IRAMM register to 0, read the IRAMM0 bit that has been cleared to 0 to confirm that the read mode has been set (to prevent speculative instruction execution by pipeline operation). (iii) Branch to the internal instruction RAM area by executing a branch instruction. Cautions 1. After the reset signal has been cleared, the NMI input is masked by hardware. The NMI is unmasked as soon as the IRAMM0 bit of the IRAMM register is cleared in step <3> of the initialization sequence. 2. If it is necessary to confirm NMI input immediately after the reset signal has been cleared and before the internal instruction RAM is set in the read mode, read the NMIRS bit of the NMI reset status register (NRS). If this bit is set to 1, it indicates that the NMI valid edge has been input. Execute the NMI servicing routine as necessary. The NRS register is used only to check NMI input after the reset signal has been cleared and before the internal instruction RAM is set in the read mode. This register is not cleared after the reset signal has been cleared. 3. The software exception and exception trap cannot be masked. Do not execute the TRAP and DBTRAP instructions until the program code has been transferred to the internal instruction RAM. Remarks 1. The NMIRS bit of the NRS register is also set to 1 if an NMI is input after the internal instruction RAM has been set in the read mode. NMIRS bit. 2. The NMI input mask function is valid after the reset signal has been cleared and before the internal instruction RAM is set in the read mode. 3. To write data to instruction RAM bank 0 of the internal instruction RAM in the middle of program execution, set the NP bit of the PSW to 1 to disable NMI and maskable interrupts, so that the software exception and exception trap do not occur. Clear the NP bit after the program has been rewritten, and after it has been confirmed that the IRAMM0 bit of the IRAMM register has been set to 1 and the read mode has been set. 4. NMI and maskable interrupt requests that are generated while the NP bit of the PSW is set to 1 are held pending. An NMI request is acknowledged immediately after the NP bit has been cleared to 0. A maskable interrupt is acknowledged immediately after the NP bit has been cleared to 0 if interrupts are not disabled (DI status) and the interrupt request is not cleared (by clearing the xxIFn bit of the interrupt control register (xxICn) to 0) before the NP bit is cleared to 0, and if the xxMKn bit of the interrupt control register is not set to 1. However, only one of the NMI and maskable interrupt requests is held pending for each interrupt source, and only one interrupt request is acknowledged even if the same interrupt request is generated two times or more. In this case, execution automatically branches to the NMI servicing routine and it is not necessary to confirm the status of the 112 User's Manual U16031EJ4V1UD CHAPTER 3 CPU FUNCTION 3.4.11 Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> * ld instruction: * sld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu sld.b, sld.h, sld.w, sld.bu, sld.hu * Multiplication instruction: mul, mulh, mulhi, mulu Instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 * * * not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 If the decode operation of the mov instruction User's Manual U16031EJ4V1UD 113 CHAPTER 3 CPU FUNCTION 3.5 Cautions Cautions concerning the CPU function are shown below. (1) Allocation to address 0100000H Be sure to allocate external memory to address 0100000H for correct operation. (2) Program execution in internal data RAM area Do not execute the program in the internal data RAM area. (3) Source/destination address of DMA transfer Be sure to use addresses FFFF000H to FFFFFFFH for the source/destination address of DMA transfer. (4) Initialization sequence Disable all interrupts from when the reset signal is released until when the program code is completely transferred to the internal instruction RAM. (5) Program code transfer to internal instruction RAM Do not execute the TRAP and DBTRAP instructions until the program code has been transferred to the internal instruction RAM. 114 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION The V850E/ME2 is provided with an external bus interface function by which external I/O and memories, such as ROM and RAM, can be connected. 4.1 Features * 32-bit/16-bit/8-bit data bus sizing function * 8-space chip select function * Wait function * Programmable wait function, through which up to 7 wait states can be inserted for each memory block * External wait function via WAIT pin * Idle state insertion function * Bus mastership arbitration function * Bus hold function * External device connection enabled via bus control/port alternate function pins 4.2 Bus Control Pins The following pins are used for connection to external devices. Bus Control Pin (Function When in Control Mode) Function When in Port Mode - PDH0 to PDH15 (Port DH) PAL0, PAL1 (Port AL) PAH0 to PAH9 (Port AH) PCS0 to PCS7 (Port CS) PCD0 (Port CD) PCD1 (Port CD) PCD2, PCD3 (Port CD) PCT0 to PCT5 (Port CT) PMCCT PMCDH PMCAL PMCAH PMCCS PMCCD Register for Port/Control Mode Switching Data bus (D0 to D15) Data bus (D16 to D31) Address bus (A0, A1) Address bus (A16 to A25) Chip select (CS0 to CS7, IOWR, IORD) SDRAM sync control (SDCKE) Bus clock (BUSCLK) SDRAM control (SDCAS, SDRAS) Read/write control (LLWR/LLBE/LLDQM, LUWR/LUBE/LUDQM, ULWR/ULBE/ULDQM, UUDQM/UUBE/UUWR, RD, WE/WR) Bus cycle start (BCYST) External wait control (WAIT) Bus hold control (HLDRQ, HLDAK) SDRAM refresh control (REFRQ) Self-refresh control (SELFREF) PCT7 (Port CT) PCM0 (Port CM) PCM2, PCM3 (Port CM) PCM4 (Port CM) PCM5 (Port CM) PMCCM - Remark When the system is reset, each bus control pin becomes unconditionally valid. (However, D16 to D31, ULWR/ULBE/ULDQM, and UUWR/UUBE/UUDQM are valid only in 32-bit mode.) User's Manual U16031EJ4V1UD 115 CHAPTER 4 BUS CONTROL FUNCTION 4.2.1 Pin status during internal instruction RAM, internal data RAM, and on-chip peripheral I/O access While accessing internal instruction RAM (in the read mode), internal data RAM, and on-chip peripheral I/O, the address bus outputs low level, and the data bus outputs nothing and enters the high-impedance state. The external bus control signals become inactive. When the internal instruction RAM is accessed (in the write mode), the address bus and data bus output data. The external bus control signals other than UUWR, ULWR, LUWR, LLWR, and WR become active. If output of the IOWR signal is enabled by setting the IOEN bit of the bus cycle period control register (BCP) to 1, the IOWR signal becomes inactive. 116 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.3 Memory Block Function The 256 MB memory space is divided into four areas including seven 2 MB memory blocks and one 1 MB memory block. The area that can be used as program area is the 64 MB space of addresses 0000000H to 3FFFFFFH. FFFFFFFH FE00000H FDFFFFFH CS7, CS6, CS5 Block 7 (2 MB) Block 6 (2 MB) Block 5 (2 MB) Block 4 (2 MB) FC00000H FBFFFFFH Area 3 FA00000H F9FFFFFH F800000H F7FFFFFH FFFF000H FFFEFFFH Internal data RAM area (16 KB) FFFB000H FFFAFFFH Note 2 Access-prohibited area FFF8000H On-chip peripheral I/O area (4 KB) FFFFFFFH CS6 C000000H BFFFFFFH CS4 Area 2 8000000H 7FFFFFFH CS3 Area 1 External memory area 4000000H 3FFFFFFH 3FFF000H 3FFEFFFH CS1 3FFB000H 3FFAFFFH 3FF8000H 3FF7FFFH 0800000H 07FFFFFH Area 0 On-chip peripheral I/O mirrorNote 1 (4 KB) Internal data RAM mirror (16 KB) Access-prohibited areaNote 2 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0100000H 00FFFFFH 0000000H Block 3 (2 MB) Block 2 (2 MB) Block 1 (2 MB) Block 0 (1 MB) Internal instruction RAM area (1 MB) CS2, CS1, CS0 Notes 1. 2. Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. The operation is not guaranteed if an access-prohibited area is accessed. User's Manual U16031EJ4V1UD 117 CHAPTER 4 BUS CONTROL FUNCTION 4.3.1 Chip select control function Each memory block can be divided by the CSC0 and CSC1 registers to control the chip select signal. The memory area can be effectively used by dividing it into memory blocks using the chip select control function. The priority order is described below. (1) Chip area select control registers 0, 1 (CSC0, CSC1) These registers can be read or written in 16-bit units and become valid by setting each bit to 1. If different chip select signal outputs are set to the same block, the priority order is controlled as follows. CSC0: CS0 > CS2 > CS1 CSC1: CS7 > CS5 > CS6 If the CS0n and CS2n bits of the CSC0 register are cleared to 00, CS1 is output to the corresponding block (n = 0 to 3). Similarly, if the CS5n and CS7n bits of the CSC1 register are cleared to 00, CS6 is output to the corresponding block (n = 0 to 3). Caution Write to the CSC0 and CSC1 registers after reset, and then do not change the set value. 118 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 15 CSC0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF060H After reset 2C11H CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 15 CSC1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF062H After reset 2C11H CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60 CS73 CS72 CS71 CS70 Bit position 15 to 0 Bit name CSnm (n = 0 to 7) (m = 0 to 3) CS00 CS01 CS02 CS03 CS10 to CS13 CS20 CS21 CS22 CS23 CS30 to CS33 CS40 to CS43 CS50 CS51 CS52 CS53 CS60 to CS63 CS70 CS71 CS72 CS73 Function Chip select is enabled by setting the CSnm bit to 1. CSnm CS operation CS0 output during block 0 access CS0 output during block 1 access. CS0 output during block 2 access. CS0 output during block 3 access. Setting has no meaning. CS2 output during block 0 access. CS2 output during block 1 access. CS2 output during block 2 access. CS2 output during block 3 access. Setting has no meaning. Setting has no meaning. CS5 output during block 7 access. CS5 output during block 6 access. CS5 output during block 5 access. CS5 output during block 4 access. Setting has no meaning. CS7 output during block 7 access. CS7 output during block 6 access. CS7 output during block 5 access. CS7 output during block 4 access. The following diagram shows the CS signal that is enabled for area 0 when the CSC0 register is set to 0F03H. When the CSC0 register is set to 0F03H, CS0 and CS2 are output to block 0 and block 1, but since CS0 has priority over CS2, CS0 is output if the addresses of block 0 and block 1 are accessed. If the addresses of block 2 and block 3 are accessed, CS2 is output. If the addresses of area 0 other than blocks 0 to 3 are accessed, CS1 is output. The following shows an example when the CSC0 register is set to 0803H and the CSC1 register is set to 0601H. User's Manual U16031EJ4V1UD 119 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-1. Example When CSC0 Register Is Set to 0803H and CSC1 Register Is Set to 0601H FFFFFFFH 2 MB FE00000H FDFFFFFH FC00000H FBFFFFFH Area 3 Block 7 (2 MB) Block 6 (2 MB) Block 5 (2 MB) Block 4 (2 MB) 4 MB FA00000H F9FFFFFH F800000H F7FFFFFH 58 MB C000000H BFFFFFFH 64 MB Area 2 8000000H 7FFFFFFH 64 MB Area 1 4000000H 3FFFFFFH 56 MB 0800000H 07FFFFFH 2 MB Area 0 2 MB 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0100000H 00FFFFFH 0000000H Block 3 (2 MB) Block 2 (2 MB) Block 1 (2 MB) Block 0 (1 MB) Fixed area (1 MB) 3 MB CS7 is output. CS5 is output. CS6 is output. CS4 is output. CS3 is output. CS1 is output. CS2 is output. CS1 is output. CS0 is output. Internal instruction RAM area 120 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.4 Bus Cycle Type Control Function In the V850E/ME2, the following external devices can be connected directly to each memory block. * SRAM, external ROM, external I/O * Page ROM * SDRAM Connected external devices are specified by the BCT0 and BCT1 registers. (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) These registers can be read or written in 16-bit units. Be sure to clear bits 14, 10, 6, and 2 to 0. If they are set to 1, the operation is not guaranteed. Caution Write to the BCT0 and BCT1 registers after reset, and then do not change the set value (however, the MEn bit value can be changed). Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the BCT0 and BCT1 registers is complete. However, it is possible to access external memory areas whose initialization settings are complete. 15 BCT0 ME3 CSn signal 14 0 13 12 11 10 0 9 8 7 6 0 5 4 3 2 0 1 0 Address FFFFF480H After reset 8888H BT31 BT30 ME2 BT21 BT20 ME1 CS2 BT11 BT10 ME0 CS1 BT01 BT00 CS0 CS3 15 14 0 13 12 11 10 0 9 8 7 6 0 5 4 3 2 0 1 0 Address FFFFF482H After reset 8888H BCT1 ME7 CSn signal BT71 BT70 ME6 BT61 BT60 ME5 CS6 BT51 BT50 ME4 CS5 BT41 BT40 CS4 CS7 Bit position 15, 11, 7, 3 Bit name MEn Function Sets memory controller operation enable for each chip select. 0: Operation disabled 1: Operation enabled 13, 12, 9, 8, 5, 4, 1, 0 BTn1, BTn0 Specifies the device to be connected to the CSn signal. BTn1 0 0 1 1 BTn0 0 1 0 1 External device connected to CSn signal SRAM, external I/O Page ROM Setting prohibited n = 1, 3, 4, 6: SDRAM n = 0, 2, 5, 7: Setting prohibited Remark n = 0 to 7 User's Manual U16031EJ4V1UD 121 CHAPTER 4 BUS CONTROL FUNCTION 4.5 Bus Access 4.5.1 Number of access clocks The number of base clocks necessary for accessing each resource is as follows. Bus Cycle Configuration Resource (Bus Width) Internal instruction RAM (32 bits) Internal data RAM (32 bits) 1 - Instruction Fetch Operand Data Access Read 1 1 Write 2 Note Note Since the internal instruction RAM (in the write mode) is accessed using BUSCLK (internal instruction RAM (in the read mode) is accessed using the internal system clock (fCLK)), programmable waits, address setup waits, and idle states can be inserted for the CS0 space. Remark Unit: Clock/access 122 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 Bus sizing function The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using the LBS register. (1) Local bus sizing control register (LBS) This register can be read or written in 16-bit units. Cautions 1. Write to the LBS register after reset, and then do not change the set value. Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the LBS register is complete. However, it is possible to access external memory areas whose initialization settings are complete. 2. When the data bus width is specified as 8 bits, only the signal shown below becomes active. LLWR: When accessing SRAM, external ROM, or external I/O (write cycle) 3. When the data bus width is specified as 16 bits, only the signals shown below become active. LLWR, LUWR: When accessing SRAM, external ROM, or external I/O (write cycle) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF48EH After resetNote 5555H/ AAAAH LBS LB71 LB70 LB61 LB60 LB51 LB50 LB41 LB40 LB31 LB30 LB21 LB20 LB11 LB10 LB01 LB00 CSn signal CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Note When in 32-bit mode: AAAAH When in 16-bit mode: 5555H For details of 32-bit mode and 16-bit mode, see 3.3.1 Operating modes. Bit position 15 to 0 Bit name LBn1, LBn0 Function Sets the data bus width of the CSn space. LBn1 0 0 1 1 LBn0 0 1 0 1 8 bits 16 bits 32 bits Data bus width of CSn space Remark n = 0 to 7 User's Manual U16031EJ4V1UD 123 CHAPTER 4 BUS CONTROL FUNCTION 4.5.3 Endian control function The endian control function can be used to set processing of word data in memory using either the big endian method or the little endian method for each CS space selected with the chip select signals (CS0 to CS7). Switching of the endian method is specified using the BEC register. Caution In the following areas, the data processing method is fixed to little endian, so the setting of the BEC register is invalid. * On-chip peripheral I/O area * Internal instruction RAM area * Internal data RAM area * Area same as internal data RAM area of addresses 3FF8000H to 3FFBFFFH * Program fetch area for external memory (1) Endian configuration register (BEC) This register can be read or written in 16-bit units. Be sure to clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. If they are set to 1, the operation is not guaranteed. Caution Write to the BEC register after reset, and then do not change the set value. 15 BEC CSn signal 0 14 BE70 13 0 12 BE60 11 0 10 BE50 9 0 8 BE40 7 0 6 BE30 5 0 4 BE20 3 0 2 BE10 1 0 0 BE00 Address FFFFF068H After reset 0000H CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit position 14, 12, 10, 8, 6, 4, 2, 0 Bit name BEn0 Specifies the endian method. 0: Little endian method 1: Big endian method Function Remark n = 0 to 7 124 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION Figure 4-2. Big Endian Addresses Within Word 31 0008H 24 23 0009H 16 15 000AH 87 000BH 0 0004H 0005H 0006H 0007H 0000H 0001H 0002H 0003H Figure 4-3. Little Endian Addresses Within Word 31 24 23 16 15 87 0 000BH 0007H 0003H 000AH 0006H 0002H 0009H 0005H 0001H 0008H 0004H 0000H 4.5.4 Big endian method usage restrictions in NEC Electronics development tools (1) When using a debugger (ID850) The big endian method is supported only in the memory window display. (2) When using a compiler (CA850) (a) Restrictions in C language (i) There are restrictions for variables allocated to/located in the big endian space, as shown below. * union cannot be used. * bitfield cannot be used. * Access with cast (changing access size) cannot be used. * Variables with initial values cannot be used. (ii) It is necessary to specify the following optimization inhibit options because optimization may cause a change in the access size. * For global optimization part (opt850)... -Wo, -XTb * For optimization depending on model part (impr850)... -Wi, +arg_reg_opt=OFF, +stld_trans_opt=OFF The specification of the optimization inhibit options shown above is not necessary, however, if the access is not an access with cast or with masking/shiftingNote. Note This is on the condition that a pattern that may cause the following optimization is not used. However, because it is very difficult for users to check the patterns completely in cases such as when several patterns are mixed (especially for optimization depending on model part), it is recommended that the optimization inhibit options shown above be specified. User's Manual U16031EJ4V1UD 125 CHAPTER 4 BUS CONTROL FUNCTION [Related global optimization part] * 1-bit set using bit or int i; i ^=1; * 1-bit clear using bit and i &= ~1; * 1-bit not using bit xor i ^= 1; * 1-bit test using bit and if(i & 1); [Related optimization depending on model part] Accessing the same variable in a different size * Cast * Mask * Shift Example int i, *ip; char c; . . . c=*((char*)ip); . . . c = 0xff & i; . . . i = (i<<24) >>24; (b) Restrictions in assembly language For variables allocated in the big endian space, a quasi directive that secures an area of other than byte size (.hword, .word, .float, .shword) cannot be used. 126 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.5.5 Bus width The V850E/ME2 accesses on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. All data is accessed in order starting from the lower order side. (1) Byte access (8 bits) (a) When the data bus width is 32 bits (little endian) <1> Access to address (4n) Address 31 31 <2> Access to address (4n + 1) Address <3> Access to address (4n + 2) Address 31 <4> Access to address (4n + 3) Address 31 4n + 3 24 23 24 23 24 23 4n + 2 24 23 16 15 16 15 4n + 1 16 15 16 15 7 8 7 4n 7 8 7 7 8 7 7 8 7 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus (b) When the data bus width is 16 bits (little endian) <1> Access to address (4n) Address 15 <2> Access to address (4n + 1) Address 15 4n + 1 <3> Access to address (4n + 2) Address 15 <4> Access to address (4n + 3) Address 15 4n + 3 7 8 7 4n 7 8 7 7 8 7 4n + 2 7 8 7 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus User's Manual U16031EJ4V1UD 127 CHAPTER 4 BUS CONTROL FUNCTION (c) When the data bus width is 8 bits (little endian) <1> Access to address (4n) Address 7 7 <2> Access to address (4n + 1) Address 7 4n <3> Access to address (4n + 2) Address 7 <4> Access to address (4n + 3) Address 7 7 7 4n + 1 7 4n + 2 4n + 3 0 Byte data 0 0 Byte data 0 0 Byte data 0 External data bus 0 Byte data 0 External data bus External data bus External data bus (d) When the data bus width is 32 bits (big endian) <1> Access to address (4n) Address 31 4n 24 23 24 23 4n + 1 24 23 24 23 <2> Access to address (4n + 1) Address 31 <3> Access to address (4n + 2) Address 31 <4> Access to address (4n + 3) Address 31 16 15 16 15 16 15 4n + 2 16 15 7 8 7 7 8 7 7 8 7 7 8 7 4n + 3 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus (e) When the data bus width is 16 bits (big endian) <1> Access to address (4n) Address 15 4n 7 8 7 <2> Access to address (4n + 1) Address 15 <3> Access to address (4n + 2) Address 15 4n + 2 <4> Access to address (4n + 3) Address 15 7 8 7 4n + 1 7 8 7 7 8 7 4n + 3 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus 128 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (f) When the data bus width is 8 bits (big endian) <1> Access to address (4n) Address 7 7 <2> Access to address (4n + 1) Address 7 4n <3> Access to address (4n + 2) Address 7 <4> Access to address (4n + 3) Address 7 7 4n + 1 7 4n + 2 7 4n + 3 0 Byte data 0 0 Byte data 0 External data bus 0 Byte data 0 External data bus 0 Byte data 0 External data bus External data bus User's Manual U16031EJ4V1UD 129 CHAPTER 4 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) When the data bus width is 32 bits (little endian) <1> Access to address (4n) Address 31 <2> Access to address (4n + 1) Address 31 24 23 24 23 4n + 2 15 16 15 4n + 1 15 16 15 4n + 1 8 7 8 7 4n 8 7 8 7 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus <3> Access to address (4n + 2) <4> Access to address (4n + 3) 1st access 2nd access Address 31 31 Address Address 31 4n + 3 24 23 4n + 2 15 16 15 15 16 15 24 23 4n + 3 24 23 15 16 15 8 7 8 7 8 7 8 7 8 7 8 7 4n + 4 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 130 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 16 bits (little endian) <1> Access to address (4n) <2> Access to address (4n + 1) 1st access Address 15 15 4n + 1 8 7 8 7 4n 0 Halfword data 0 External data bus 2nd access Address Address 15 4n + 1 15 15 15 8 7 8 7 8 7 8 7 4n + 2 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus <3> Access to address (4n + 2) <4> Access to address (4n + 3) 1st access 2nd access Address 15 15 4n + 3 8 7 8 7 8 7 8 7 4n + 4 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 15 15 Address Address 15 15 4n + 3 8 7 8 7 4n + 2 0 Halfword data 0 External data bus User's Manual U16031EJ4V1UD 131 CHAPTER 4 BUS CONTROL FUNCTION (c) When the data bus width is 8 bits (little endian) <1> Access to address (4n) 1st access 15 Address 7 4n 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 15 Address 7 4n + 1 0 Halfword data <2> Access to address (4n + 1) 1st access 15 Address 15 2nd access 2nd access 8 7 8 7 8 7 7 4n + 1 8 7 Address 7 4n + 2 0 External data bus 0 Halfword data 0 External data bus <3> Access to address (4n + 2) 1st access 15 Address 15 <4> Access to address (4n + 3) 1st access 15 15 2nd access 2nd access 8 7 7 4n + 2 8 7 Address 7 4n + 3 8 7 Address 7 4n + 3 8 7 Address 7 4n + 4 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 132 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (d) When the data bus width is 32 bits (big endian) <1> Access to address (4n) Address 31 4n 24 23 4n + 1 15 16 15 15 16 15 4n + 2 8 7 8 7 8 7 8 7 24 23 4n + 1 31 <2> Access to address (4n + 1) Address 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus <3> Access to address (4n + 2) <4> Access to address (4n + 3) 1st access 2nd access Address 31 31 4n + 4 Address Address 31 24 23 24 23 24 23 15 16 15 4n + 2 15 16 15 15 16 15 8 7 8 7 4n + 3 8 7 8 7 4n + 3 8 7 8 7 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus User's Manual U16031EJ4V1UD 133 CHAPTER 4 BUS CONTROL FUNCTION (e) When the data bus width is 16 bits (big endian) <1> Access to address (4n) <2> Access to address (4n + 1) 1st access Address 15 15 4n 8 7 8 7 4n + 1 0 Halfword data 0 External data bus 2nd access Address Address 15 15 15 15 4n + 2 8 7 8 7 4n + 1 8 7 8 7 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus <3> Access to address (4n + 2) <4> Access to address (4n + 3) 1st access 2nd access Address 15 Address 15 Address 15 15 4n + 2 8 7 8 7 4n + 3 0 Halfword data 0 External data bus 15 15 4n + 4 8 7 8 7 4n + 3 8 7 8 7 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 134 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (f) When the data bus width is 8 bits (big endian) <1> Access to address (4n) 1st access 15 Address 15 <2> Access to address (4n + 1) 1st access 15 15 2nd access 2nd access 8 7 7 4n 8 7 Address 7 4n + 1 8 7 Address 7 4n + 1 8 7 Address 7 4n + 2 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus <3> Access to address (4n + 2) 1st access 15 Address 15 <4> Access to address (4n + 3) 1st access 15 15 2nd access 2nd access 8 7 7 4n + 2 8 7 Address 7 4n + 3 8 7 Address 7 4n + 3 8 7 Address 7 4n + 4 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus User's Manual U16031EJ4V1UD 135 CHAPTER 4 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) When the data bus width is 32 bits (little endian) <1> Access to address (4n) <2> Access to address (4n + 1) 1st access Address 31 2nd access Address Address 31 31 4n + 3 31 31 4n + 3 31 24 23 24 23 4n + 2 24 23 24 23 4n + 2 24 23 24 23 16 15 16 15 4n + 1 16 15 16 15 4n + 1 16 15 16 15 8 7 8 7 4n 8 7 8 7 8 7 8 7 4n + 4 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus <3> Access to address (4n + 2) 1st access Address 31 <4> Access to address (4n + 3) 1st access Address 31 2nd access Address 31 2nd access Address 31 31 4n + 3 31 31 4n + 3 31 24 23 24 23 4n + 2 24 23 24 23 24 23 24 23 24 23 24 23 4n + 6 16 15 16 15 16 15 16 15 4n + 5 16 15 16 15 16 15 16 15 4n + 5 8 7 8 7 8 7 8 7 4n + 4 8 7 8 7 8 7 8 7 4n + 4 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 136 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 16 bits (little endian) (1/2) <1> Access to address (4n) 1st access 31 2nd access 31 24 23 Address 15 24 23 Address 15 16 15 16 15 4n + 1 8 7 8 7 4n + 3 8 7 8 7 4n 0 0 4n + 2 0 0 Word data External data bus Word data External data bus <2> Access to address (4n + 1) 1st access 31 2nd access 31 3rd access 31 24 23 Address 15 24 23 Address 15 24 23 Address 15 16 15 16 15 16 15 4n + 1 8 7 8 7 4n + 3 8 7 8 7 8 7 4n + 2 8 7 4n + 4 0 0 0 0 0 0 Word data External data bus Word data External data bus Word data External data bus User's Manual U16031EJ4V1UD 137 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 16 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 31 2nd access 31 24 23 Address 15 24 23 Address 15 16 15 16 15 4n + 3 8 7 8 7 4n + 5 8 7 8 7 4n + 2 0 0 4n + 4 0 0 Word data External data bus Word data External data bus <4> Access to address (4n + 3) 1st access 31 2nd access 31 3rd access 31 24 23 Address 15 24 23 Address 15 24 23 Address 15 16 15 16 15 16 15 4n + 3 8 7 8 7 4n + 5 8 7 8 7 8 7 4n + 4 8 7 4n + 6 0 0 0 0 0 Word data 0 External data bus Word data External data bus Word data External data bus 138 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (c) When the data bus width is 8 bits (little endian) (1/2) <1> Access to address (4n) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 4n 8 7 Address 7 4n + 1 8 7 Address 7 4n + 2 8 7 Address 7 4n + 3 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus <2> Access to address (4n + 1) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 4n + 1 8 7 Address 7 4n + 2 8 7 Address 7 4n + 3 8 7 Address 7 4n + 4 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus User's Manual U16031EJ4V1UD 139 CHAPTER 4 BUS CONTROL FUNCTION (c) When the data bus width is 8 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 4n + 2 8 7 Address 7 4n + 3 8 7 Address 7 4n + 4 8 7 Address 7 4n + 5 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus <4> Access to address (4n + 3) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 4n + 3 8 7 Address 7 4n + 4 8 7 Address 7 4n + 5 8 7 Address 7 4n + 6 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 140 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (d) When the data bus width is 32 bits (big endian) <1> Access to address (4n) <2> Access to address (4n + 1) 1st access Address 31 31 31 Address 2nd access Address 31 31 31 4n + 4 4n 24 23 24 23 24 23 24 23 4n + 1 24 23 24 23 4n + 1 16 15 16 15 16 15 16 15 4n + 2 16 15 16 15 4n + 2 8 7 8 7 8 7 8 7 8 7 8 7 4n + 3 0 0 0 Word data 4n + 3 0 External data bus 0 Word data 0 External data bus Word data External data bus <3> Access to address (4n + 2) 1st access Address 31 <4> Access to address (4n + 3) 1st access Address 31 2nd access Address 31 2nd access Address 31 31 31 4n + 4 31 31 4n + 4 24 23 24 23 24 23 24 23 4n + 5 24 23 24 23 24 23 24 23 4n + 5 16 15 16 15 4n + 2 16 15 16 15 16 15 16 15 16 15 16 15 4n + 6 8 7 8 7 4n + 3 8 7 8 7 8 7 8 7 4n + 3 8 7 8 7 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus User's Manual U16031EJ4V1UD 141 CHAPTER 4 BUS CONTROL FUNCTION (e) When the data bus width is 16 bits (big endian) (1/2) <1> Access to address (4n) 1st access 31 2nd access 31 24 23 Address 4n 8 7 8 7 4n + 1 0 Word data 0 External data bus 24 23 Address 15 16 15 16 15 16 15 4n + 2 8 7 8 7 4n + 3 0 0 Word data External data bus <2> Access to address (4n + 1) 1st access 31 2nd access 31 3rd access 31 24 23 Address 15 24 23 16 15 Address 4n + 2 24 23 Address 15 16 15 16 15 16 15 4n + 4 8 7 8 7 8 7 8 7 8 7 4n + 1 8 7 4n + 3 0 0 0 Word data 0 External data bus 0 0 Word data External data bus Word data External data bus 142 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (e) When the data bus width is 16 bits (big endian) (2/2) <3> Access to address (4n + 2) 1st access 31 2nd access 31 24 23 16 15 Address 4n + 2 8 7 8 7 4n + 3 0 Word data 0 External data bus 24 23 Address 15 16 15 16 15 4n + 4 8 7 8 7 4n + 5 0 0 Word data External data bus <4> Access to address (4n + 3) 1st access 31 2nd access 31 3rd access 31 24 23 Address 15 24 23 16 15 Address 4n + 4 24 23 Address 15 16 15 16 15 16 15 4n + 6 8 7 8 7 8 7 8 7 8 7 4n + 3 8 7 4n + 5 0 0 0 Word data 0 External data bus 0 0 Word data External data bus Word data External data bus User's Manual U16031EJ4V1UD 143 CHAPTER 4 BUS CONTROL FUNCTION (f) When the data bus width is 8 bits (big endian) (1/2) <1> Access to address (4n) 1st access 31 2nd access 31 3rd access 31 4th access 31 24 23 24 23 24 23 24 23 16 15 16 15 Address 16 15 Address 16 15 Address 8 7 7 4n 8 7 7 4n + 1 8 7 7 4n + 2 8 7 Address 7 4n + 3 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus <2> Access to address (4n + 1) 1st access 31 2nd access 31 3rd access 31 4th access 31 24 23 24 23 24 23 24 23 16 15 16 15 Address 16 15 Address 16 15 Address 8 7 7 4n + 1 8 7 7 4n + 2 8 7 7 4n + 3 8 7 Address 7 4n + 4 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 144 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (f) When the data bus width is 8 bits (big endian) (2/2) <3> Access to address (4n + 2) 1st access 31 2nd access 31 3rd access 31 4th access 31 24 23 24 23 24 23 24 23 16 15 16 15 Address 16 15 Address 16 15 Address 8 7 7 4n + 2 8 7 7 4n + 3 8 7 7 4n + 4 8 7 Address 7 4n + 5 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus <4> Access to address (4n + 3) 1st access 31 2nd access 31 3rd access 31 4th access 31 24 23 24 23 24 23 24 23 16 15 16 15 Address 16 15 Address 16 15 Address 8 7 7 4n + 3 8 7 7 4n + 4 8 7 7 4n + 5 8 7 Address 7 4n + 6 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus User's Manual U16031EJ4V1UD 145 CHAPTER 4 BUS CONTROL FUNCTION 4.5.6 Data read control function (1) Line buffer control registers 0, 1 (LBC0, LBC1) The V850E/ME2 has a read buffer. The LBC0 and LBC1 registers set the operating conditions of the read buffer in each CS space. These registers can be read or written in 16-bit units. Be sure to clear bits 15, 14, 11, 10, 7, 6, 3, and 2 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. Be sure to write data to the LBC0 and LBC1 registers after reset. After writing data to these registers, do not change their values. 2. When the speculative read function is set for each CSn space, do not insert an idle state in the CSn space for which the speculative read function is enabled by the BCC register (n = 0 to 7). If an idle state is required to be inserted in the CSn space for which the speculative read function is enabled, enable the speculative read function for all CSn spaces (set the LBC0 and LBC1 registers to 3333H) or disable the speculative read function for all CSn spaces (set the LBC0 and LBC1 registers to 0000H). 3. Do not enable the speculative read function for SDRAM that is accessed via a 32-bit bus. 15 LBC0 CSn signal 15 LBC1 CSn signal 0 0 14 0 13 12 11 0 10 0 9 8 7 0 6 0 5 4 3 0 2 0 1 0 Address FFFFF490H After reset 0000H RB31 RB30 CS3 RB21 RB20 CS2 RB11 RB10 CS1 RB01 RB00 CS0 14 0 13 12 11 0 10 0 9 8 7 0 6 0 5 4 3 0 2 0 1 0 Address FFFFF492H After reset 0000H RB71 RB70 CS7 RB61 RB60 CS6 RB51 RB50 CS5 RB41 RB40 CS4 Bit position 13, 12, 9, 8, 5, 4, 1, 0 Bit name RBn1, RBn0 Function These bits set the operating conditions of the read buffer (timing of speculative read) in each CSn space. RBn1 0 0 1 1 RBn0 0 1 0 1 Timing of speculative read Without speculative read (operation of read buffer is prohibited) Setting prohibited In all cycles (including data access) Remarks 1. n = 0 to 7 2. If the setting of the RBn1 and RBn0 bits is changed, the data in the read buffer is immediately invalidated. 146 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (a) Speculative read function (read buffer function) The V850E/ME2 has speculative read buffers consisting of 4 words (128 bits). If the operating conditions set by the LBC0 or LBC1 register are satisfied when a read request is issued from the CPU or DMA controller to a CSn space, the requested address is read and the remaining three words of data are read (speculatively) to the read buffers, regardless of whether a request is issued from the CPU or DMA controller. Data is read to the read buffers in the sequence of critical first access. Example of transfer: For speculative reading of 32 bits (i) xxxxx00H xxxxx04H xxxxx08H xxxxx0CH (ii) xxxxx04H xxxxx08H xxxxx0CH xxxxx00H (iii) xxxxx01H xxxxx05H xxxxx09H xxxxx0DHNote Note If the lower 2 bits of an address are not used in the 32-bit mode, the operation is the same as (i) above. The four words of data that have been read are held in the read buffers. If the following conditions are satisfied, the data in the buffers is lost. * Speculative read miss hit (read request to external memory area not stored in read buffer) * Writing BCT0 or BCT1 register * Writing LBS register * Writing LBC0 or LBC1 register * Generation of bus hold * Generation of DMA flyby cycle (not dependent on CS space) * Memory write access to speculatively read line address If the CPU or DMA controller requests reading the data held in the read buffers, the data is transferred to the CPU or DMA controller without generating an external memory cycle. Remark If the speculative read function is enabled in the 32-bit mode (with a 32-bit data bus width) and the LD.W instruction is executed at address xxxxx0DH, the following bus cycles are successively generated. xxxxx0CH xxxxx00H xxxxx04H xxxxx08H Penalty cycle due to speculative reading xxxxx10H xxxxx14H xxxxx18H xxxxx1CH Penalty cycle due to speculative reading The CPU reads the following data when it stores data in the read buffer. xxxxx0DH (8 bits) xxxxx0EH (16 bits) xxxxx10H (8 bits) User's Manual U16031EJ4V1UD 147 CHAPTER 4 BUS CONTROL FUNCTION The speculative read operation is outlined below. Figure 4-4. Outline of Speculative Read Operation <2> CPU or DMA controller Read buffer 1 (32 bits) Read buffer 2 (32 bits) <1> <3> <4> <5> External interface <6> Read buffer 3 (32 bits) Read buffer 4 (32 bits) (A) A read cycle to the address requested by the CPU or DMA controller is executed (<1>). (B) The CPU or DMA controller reads the data loaded to read buffer 1 (<2>). (C) Read buffers 2 to 4 are speculatively read, and a read cycle of the remaining three words is executed (<3> to <5>). (D) If the CPU or DMA controller generates a read request to an address that has already been speculatively read, data is read from read buffers 2 to 4 (a read access to the external memory does not occur) (<6>). Remarks 1. (B) and (C) are executed in parallel ((D) is also executed in parallel if data is stored in the read buffers). 2. If the CPU or DMA controller issues a read request to an address that is not speculatively read in (C) in the cycle of (D), the operation is kept waiting until the operation of (C) is completed. After completion of the operation of (C), all data in the read buffers is discarded, and an operation in response to the next address request is executed starting from (A) (miss hit operation of the speculative read function). (b) Write buffer function The V850E/ME2 has an on-chip write buffer of 4 words (128 bits). The write buffer stores data if a write cycle cannot be executed while the external bus is occupiedNote. The next instructions are speculatively executed until the write buffer becomes full. The write buffer is valid for all the external memory areas. If a write request is generated while the write buffer is full, the next instruction execution is postponed until there is a vacancy in the write buffer. While data is being stored in the write buffer (when a write operation to the external memory has not been completed), DMA flyby and bus hold requests are not acknowledged (DMA flyby and bus hold requests are acknowledged and an enable signal is generated after all the data of the write buffers has been written to the external memory). Note The external bus is occupied when there is a bus cycle currently under execution. If instruction fetch cycles are successively executed, all write cycles for the write data stored in the write buffer are always generated after the bus cycle currently under execution (instruction fetch cycle) is completed. 148 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION Cautions 1. Because the write buffer consists of four stages, the write buffer becomes full after 4 bytes (32 bits) when a byte write operation is executed (while a write operation to the external memory is standing by). Similarly, the conditions under which the write buffer becomes full vary due to an address miss-align access, etc. 2. When data is written to an external device, the write operation to the external device may not be executed even when a CPU write operation has been completed by the write buffer. The CPU can access the on-chip peripheral I/O registers after the write operation has been completed even if data exist in the write buffer. Therefore, if it is necessary to change the value of an on-chip peripheral I/O register after completion of execution of an external memory cycle, write the same value as the default value to the LBC0 or LBC1 register or write 00H to the WAS register before writing the onchip peripheral I/O register whose value is to be changed. When writing an on-chip peripheral I/O register other than the LBC0 or LBC1 register without writing the same value as the default value to the LBC0 or LBC1 register, or writing an on-chip peripheral I/O register other than the WAS register without writing 00H to the WAS register, the register value may be changed before completion of the external memory cycle. Although rewriting the LBC0 and LBC1 registers is prohibited, the same value can be rewritten to the registers in this case. operation is not guaranteed. 3. If an read access to the external device occurs when data exist in the write buffer, reading from the external device is executed after the writing all data in the write buffer to the external device. 4. During 2-cycle transfer that writes data to the external device, the write operation to the external device may not be completed even if TCn bit of DCHCn register = 1 (DMA transfer completion) is read by the write buffer (n = 0 to 3). If it is necessary to change the value of an on-chip peripheral I/O register after completion of DMA transfer (completion of a write operation to the external device), perform either of the following operations. * Monitor the TCn signal (the TCn signal becomes active in synchronization with a write operation to the external device). * After detecting setting (to 1) of the TCn bit, write 00H to the WAS register or write the same value as the default value to the LBC0 or LBC1 register, and then change the value of the on-chip peripheral I/O register. If the value of an on-chip peripheral I/O register other than the LBC0 and LBC1 registers is changed without writing the same value to LBC0 or LBC1 or the value of an on-chip peripheral I/O register other than the WAS register is changed without writing 00H to the WAS register, the value of the on-chip peripheral I/O register may be changed before completion of DMA transfer. Although rewriting the LBC0 and LBC1 registers is prohibited, the same value can be rewritten to the registers in this case. However, if a value different from the default value is written to the LBC0 or LBC1 register, the operation is not guaranteed. However, if a value different from the default value is written to the LBC0 or LBC1 register, the User's Manual U16031EJ4V1UD 149 CHAPTER 4 BUS CONTROL FUNCTION (2) Write access synchronization control register (WAS) When an external device is written, even if the write operation by the CPU via the write buffer is complete, writing to the external device may not be complete. The WAS register is used to complete writing all data in the write buffer to the external device. See 4.5.6 (1) (b) Write buffer function for details. This register is write-only, in 8-bit units. 7 WAS 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFF49CH After reset Undefined Caution Be sure to write 00H to the WAS register. Operation cannot be guaranteed if value other than 00H is written. 150 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.6 Bus Clock Control Function (1) Bus mode control register (BMC) This register sets the division rate of the bus clock (BUSCLK) with respect to the internal system clock (fCLK). Writing the BMC register stops BUSCLK once at low level. BUSCLK resumes operation with the set divided clock after it has been stopped. While BUSCLK is stopped, the operation of the SDRAM refresh control register (RFSn) of SDRAM is also stopped (n = 1, 3, 4, 6). This register can be read or written in 8-bit units. Be sure to clear bits 7 to 2 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. Write the BMC register after reset, and then do not change the value that has been written. 2. Before writing to the BMC register, be sure to set the VSWC register to x7H (x: VSWC register value before the set value of the BMC register is changed). Even if the VSWC register value is x7H before the set value of the BMC register was changed, be sure to set the VSWC register to x7H. After changing the set value of the BMC register, re-set the value of the VSWC register to the value before the set value of the BMC register was changed (see 3.4.10 Initialization sequence). 3. Set the number of waits (using the DWk2 to DWk0 bits of the DWCm register) or address setup waits (using the ACk1 and ACk0 bits of the ASC register) for all the CS spaces in which an SRAM or page-ROM interface cycle is activated to 1 or more when the same clock is used as the internal system clock (fCLK) and bus clock (CKM1 and CKM0 bits = 00) and the speculative read function is enabled (RBk1 and RBk0 bits of LBCm register = 11) (m = 0, 1, k = 0 to 7). 4. The maximum operating frequency of BUSCLK is 66 MHz. Set the BMC register so that BUSCLK does not exceed 66 MHz. 7 BMC 6 0 5 0 4 0 3 0 2 0 1 CKM1 0 CKM0 Address FFFFF498H After reset 00H 0 Bit position 1, 0 Bit name CKM1, CKM0 Function These bits set the division ratio of the bus clock (BUSCLK) with respect to the internal system clock (fCLK). CKM1 0 0 1 1 CKM0 0 1 0 1 fCLK fCLK/2 fCLK/3 fCLK/4 Division ratio of BUSCLK vs. fCLK Remark fCLK: Internal system clock User's Manual U16031EJ4V1UD 151 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-5. BMC Register Switching Timing Internal system clock (fCLK) Within fCLK x 12 clocks fCLK x 12 clocks T0Note 1 T1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) Note 2 (output) D0 to D31 (I/O) BMC register changed Notes 1. 2. Remark State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE The broken lines indicate the high-impedance state. 152 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.7 Wait Function 4.7.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory and I/Os, it is possible to insert up to 7 data wait states in the starting bus cycle for each CS space. The number of wait states can be specified by program using DWC0 and DWC1 registers. Just after system reset, all blocks have 7 data wait states inserted. These registers can be read or written in 16-bit units. Cautions 1. The internal instruction RAM area (in the read mode) and internal data RAM area are not subject to programmable waits and ordinarily no wait access is carried out. When the internal instruction RAM area is accessed (in the write mode), the programmable wait value set for the CS0 space becomes valid. The on-chip peripheral I/O area is not subject to programmable waits, with wait control performed by each peripheral function only. 2. In the following cases, the settings of the DWC0 and DWC1 registers are invalid (wait control is performed by each memory controller). * Page ROM on-page access * SDRAM access 3. Write to the DWC0 and DWC1 registers after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the DWC0 and DWC1 registers is complete. However, it is possible to access external memory areas whose initialization settings are complete. User's Manual U16031EJ4V1UD 153 CHAPTER 4 BUS CONTROL FUNCTION 15 DWC0 CSn signal 15 DWC1 CSn signal 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF484H After reset 7777H 0 DW32 DW31 DW30 0 DW22 DW21 DW20 0 DW12 DW11 DW10 0 DW02 DW01 DW00 CS3 14 13 12 11 10 CS2 9 8 7 6 CS1 5 4 3 2 CS0 1 0 Address FFFFF486H After reset 7777H 0 DW72 DW71 DW70 0 DW62 DW61 DW60 0 DW52 DW51 DW50 0 DW42 DW41 DW40 CS7 CS6 CS5 CS4 Bit position 14 to 12, 10 to 8, 6 to 4, 2 to 0 Bit name DWn2 to DWn0 Function Specifies the number of wait states inserted in the CSn space. DWn2 0 0 0 0 1 1 1 1 DWn1 0 0 1 1 0 0 1 1 DWn0 0 1 0 1 0 1 0 1 Number of wait states inserted in CSn space Not inserted 1 2 3 4 5 6 7 Remark n = 0 to 7 154 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (2) Address setup wait control register (ASC) The V850E/ME2 allows insertion of address setup wait states before the SRAM/page ROM cycle (the setting of the ASC register in the SDRAM cycle is invalid). The number of address setup wait states can be set with the ASC register for each CS space. This register can be read or written in 16-bit units. Cautions 1. The internal instruction RAM area (in the read mode), internal data RAM area, and onchip peripheral I/O area are not subject to address setup wait insertion. When the internal instruction RAM area is accessed (in the write mode), the address setup wait value set for the CS0 space becomes valid. 2. During an address setup wait, the WAIT pin-based external wait function is disabled. 3. Write to the ASC register after reset, and then do not change the set value. 4. Be sure to set the number of waits to 1 or more if the CSn signal is delayed using the PFCCS register. 5. The address setup wait setting value is valid during DMA flyby transfer. 15 ASC CSn signal 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF48AH After reset FFFFH AC71 AC70 AC61 AC60 AC51 AC50 AC41 AC40 AC31 AC30 AC21 AC20 AC11 AC10 AC01 AC00 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit position 15 to 0 Bit name ACn1, ACn0 Function Specifies the number of address setup wait states inserted before the SRAM/page ROM cycle for each CSn space. ACn1 0 0 1 1 ACn0 0 1 0 1 Not inserted 1 2 3 Number of wait states Remark n = 0 to 7 User's Manual U16031EJ4V1UD 155 CHAPTER 4 BUS CONTROL FUNCTION (3) Bus cycle period control register (BCP) With the V850E/ME2, the operations of IORD and IOWR can be enabled or disabled in the SRAM, external ROM, and external I/O cycles. This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 7 to 4 and 2 to 0 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. During a flyby DMA transfer for SRAM, external ROM, or external I/O, the IORD and IOWR signals are always output, irrespective of the IOEN bit setting. Flyby transfer from external I/O to external memory: IORD and WR signals become active. Flyby transfer from external memory to external I/O: IOWR and RD signals become active. In page ROM cycle, on the other hand, the IOEN bit setting has no meaning. 2. Write to the BCP register after reset, and then do not change the set values. 3. If the internal instruction RAM is accessed while the IOEN bit is set (1) (in the write mode), the IOWR signal becomes inactive. 7 6 0 5 0 4 0 3 IOEN 2 0 1 0 0 0 Address FFFFF48CH After reset 00H BCP 0 Bit position 3 Bit name IOEN Function Specifies whether to enable/disable the operation of IORD and IOWR in SRAM, external ROM, and external I/O cycles. IOEN 0 Enable/disable IORD and IOWR operation Disables the operation of IORD and IOWR in SRAM, external ROM, and external I/O cycles. 1 Enables the operation of IORD and IOWR in SRAM, external ROM, and external I/O cycles. 156 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (4) DMA flyby transfer wait control register (FWC) The FWC register sets the number of data wait cycles during DMA flyby transfer for each channel n (see the timing chart in 6.5.2 Flyby transfer) (n = 0 to 3). The set value of this register is valid during DMA flyby transfer, and the set values of the DWC0, DWC1, and PRC registers are invalid. This register can be read or written in 16-bit units. Cautions 1. The internal instruction RAM area and internal data RAM area are not subject to the programmable wait operation and are always accessed with no wait cycle. The on-chip peripheral I/O area is also not subject to the programmable wait operation, and is subject only to wait control by each peripheral function. 2. Write to the FWC register after reset, and then do not change the set values. 15 FWC 14 13 12 11 0 10 9 8 7 0 6 5 4 3 0 2 1 0 Address FFFFF494H After reset 7777H 0 FW32 FW31 FW30 FW22 FW21 FW20 FW12 FW11 FW10 FW02 FW01 FW00 Bit position 14 to 12, 10 to 8, 6 to 4, 2 to 0 Bit name FWn2 to FWn0 Function These bits set the number of data wait cycles to each channel n during DMA flyby transfer. FWn2 FWn1 FWn0 Number of data wait cycles When SDRAM is not accessed 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Not inserted 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 When SDRAM is accessed Remark n = 0 to 3 User's Manual U16031EJ4V1UD 157 CHAPTER 4 BUS CONTROL FUNCTION 4.7.2 External wait function When an extremely slow memory, I/O, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device. Just as with programmable waits, accessing internal instruction RAM (in the read mode), internal data RAM, and on-chip peripheral I/O areas cannot be controlled by external waits. The external WAIT signal can be input asynchronously to BUSCLK and is sampled at the rising edge of BUSCLK immediately after the T1 and TW states of a bus cycle. If the setup/hold time in the sampling timing is not satisfied, the wait state may or may not be inserted in the next state. 4.7.3 Relationship between programmable wait and external wait A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the programmable wait and the wait cycle controlled by the WAIT pin. Programmable wait Wait control Wait by WAIT pin For example, if the timings of the programmable wait and the WAIT pin signal are as illustrated below, three wait states will be inserted in the bus cycle. Figure 4-6. Example of Wait Insertion T1 TW TW TW T2 BUSCLK WAIT pin Wait by WAIT pin Programmable wait Wait control Remark The circle indicates the sampling timing. 158 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.7.4 Bus cycles in which wait function is valid In the V850E/ME2, the number of waits can be specified according to the memory type specified for each memory block. The following shows the bus cycles in which the wait function is valid and the registers used for wait setting. Table 4-1. Bus Cycles in Which Wait Function Is Valid Bus Cycle Type of Wait Programmable Wait Setting Register Bit Wait Count 0 to 3 0 to 7 0 to 3 0 to 7 0 to 7 1 to 3 0 to 7 0 to 3 1 to 3 1 to 8 1 to 3 1 to 8 Wait from WAIT pin - (invalid) (valid) - (invalid) (valid) (valid) - (invalid) (valid) - (invalid) - (invalid) - (invalid) - (invalid) - (invalid) SRAM, external ROM, external I/O cycles Page ROM cycle Off-page On-page SDRAM cycle DMA flyby transfer cycle External I/O SRAM Address setup wait Data access wait Address setup wait Data access wait Data access wait Row address precharge Flyby transfer wait Address setup wait ASC DWC0, DWC1 ASC DWC0, DWC1 PRC SCRm FWC ASC SCRm FWC SCRm FWC ACn1, ACn0 DWn2 to DWn0 ACn1, ACn0 DWn2 to DWn0 PRW2 to PRW0 BCWm1, BCWm0 FWa2 to FWa0 ACn1, ACn0 BCWm1, BCWm0 FWa2 to FWa0 BCWm1, BCWm0 FWa2 to FWa0 External I/O SDRAM Off-page Row address precharge Flyby transfer wait On-page Row address precharge Flyby transfer wait Remark n = 0 to 7, m = 1, 3, 4, 6, a = 0 to 3 User's Manual U16031EJ4V1UD 159 CHAPTER 4 BUS CONTROL FUNCTION 4.8 Idle State Insertion Function (1) Bus cycle control register (BCC) To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the current bus cycle after the T2 state to meet the data output float delay time on memory read access for each CS space. The bus cycle following the T2 state starts after the idle state is inserted. An idle state is inserted at the timing shown below. * After read/write cycles for SRAM, external I/O, or external ROM * After a read cycle for page ROM * After a read cycle for SDRAM The idle state insertion setting can be specified by program using the BCC register. Immediately after the system reset, idle state insertion is automatically programmed for all memory blocks. For the timing when an idle state is inserted, see the memory access timings in Chapter 5. This register can be read or written in 16-bit units. Cautions 1. The internal instruction RAM area (in the read mode), internal data RAM area, and onchip peripheral I/O area are not subject to idle state insertion. When the internal instruction RAM area is accessed (in the write mode), the idle state value set for the CS0 space becomes valid. 2. Write to the BCC register after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the BCC register is complete. However, it is possible to access external memory areas whose initialization settings are complete. 3. The chip select signal (CSn) does not become active in the idle state (n = 0 to 7). 15 BCC CSn signal 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF488H After reset FFFFH BC71 BC70 BC61 BC60 BC51 BC50 BC41 BC40 BC31 BC30 BC21 BC20 BC11 BC10 BC01 BC00 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit position 15 to 0 Bit name BCn1, BCn0 Function Specifies the insertion of an idle state in the CSn space. BCn1 0 0 1 1 BCn0 0 1 0 1 Not inserted 1 2 3 Idle state in CSn space Remark n = 0 to 7 160 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (2) DMA flyby transfer idle control register (FIC) The FIC register sets the number of idle states during DMA flyby transfer for each DMA channel n (see the timing chart in 6.5.2 Flyby transfer) (n = 0 to 3). The idle state is inserted at the end of DMA flyby transfer. During DMA flyby transfer, the set value of this register is valid, and the set value of the BCC register is invalid. This register can be read or written in 16-bit units. Cautions 1. The internal instruction RAM area, internal data RAM area, and on-chip peripheral I/O area are not subject to idle state insertion. 2. Write to the FIC register after reset, and then do not change the set values. 15 FIC 14 0 13 12 11 0 10 0 9 8 7 0 6 0 5 4 3 0 2 0 1 0 Address FFFFF496H After reset 3333H 0 FI31 FI30 FI21 FI20 FI11 FI10 FI01 FI00 Bit position 13, 12, 9, 8, 5, 4, 1, 0 Bit name FIn1, FIn0 Function These bits specify the number of idle states during DMA flyby transfer for each channel n. FIn1 0 0 1 1 FIn0 0 1 0 1 Idle state during DMA flyby transfer Not inserted 1 2 3 Remark n = 0 to 3 User's Manual U16031EJ4V1UD 161 CHAPTER 4 BUS CONTROL FUNCTION 4.9 Instruction Cache Function The V850E/ME2 has an 8 KB 2-way set associative instruction cache. This instruction cache uses an LRU (Least Recently Used) algorithm. This cache uses two ways as the cache, with the way to be replaced in case of a miss hit determined by the internal LRU bit. If the way is specified as a cacheable area, a 4-word burst sequential read cycle is issued (when the external 32-bit bus operates) (when the external 16-bit bus operates, an 8-halfword burst read cycle is issued). Set the instruction cache using the following procedure, after system reset. <1> Wait until the value of the ICC register reaches "0000H" (until the tag is initialized). <2> Make the setting of the instruction cache cacheable by using the BHC register. Caution Be sure to set the BHC register in an uncached area (instructions cannot be fetched correctly if it is set from a cacheable area). 4.9.1 Cache configuration register (BHC) (1) Cache configuration register (BHC) This register can set the configuration of the cache memory in each CS space selected by the chip select signals (CS0 to CS2). Setting a cacheable area becomes valid immediately after the BHC register has been set. This register can be read or written in 16-bit units. Be sure to clear bits 15 to 5 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. Write the BHC register after reset, and then do not change the set values. 2. The area that includes the instruction that sets the BHC register cannot be set from an uncached area to a cacheable area, or from a cacheable area to an uncached area. In this case, branch to area 1 and then set area 0 to a cacheable area by an instruction in area 1. If necessary, branch to area 0 again. An uncached area and a cacheable area can be set in any CS space in the internal instruction RAM area. (Example of prohibited setting) * If the instruction that sets the BHC register is in area 0 Before setting BHC Area 0 Area 1 Uncached area Uncached area After setting BHC (area 0 is set as cacheable area in area 0) Area 0 Area 1 Cacheable area Uncached area 162 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION Cautions 3. If adjacent memory areas are a cacheable area and an uncached area, only a branch instruction can be used to successively access this memory boundary. The operation is not guaranteed if this memory boundary is successively accessed by an instruction other than a branch instruction. (Operation example) * An access from area 0 to area 1 can be made only by a branch instruction. * Successive accesses can be made from area 1 to area 2. Area 0 Area 1 Area 2 Uncached area Cacheable area Cacheable area 15 BHC CSn signal 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 BH20 CS2 3 0 2 BH10 CS1 1 0 0 BH00 Address FFFFF06AH After reset 0000H CS0 Bit position 4, 2, 0 Bit name BHn0 Function These bits set the instruction cache placed in the CSn space. 0: Uncached 1: Cacheable Remark n = 0 to 2 User's Manual U16031EJ4V1UD 163 CHAPTER 4 BUS CONTROL FUNCTION 4.9.2 8 KB 2-way set associative cache The data memory of the 8 KB 2-way set associative cache has two ways each consisting of 4-word lines and blocks of 256 entries, and has a total capacity of 8 KB. If a cache miss occurs, the data memory is refilled in 1-line units. Only the instructions related to data access of the cacheable area can be cached in the instruction cache. Figure 4-7. Configuration of 8 KB 2-Way Set Associative Instruction Cache 25 TAG 14 12 11 INDEX 8 43 21 0 2 Tag 1 word Data (4 words) 1 word 1 word 1 word . . . . . . . . . . . . 256 entries 14 14 Internal bus 32 Comparator Internal bus 32 Way select control signal when a hit occurs Selector 32 IIHIT Instruction data 4.9.3 LRU algorithm This algorithm is used to record accesses to blocks and replace the block that has not been used for the longest time, so that information that may be necessary is not discarded immediately. 164 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.9.4 Instruction cache control function (1) Instruction cache control register (ICC) This register sets two types of functions, tag clear and auto fill. This register can be read or written in 16-bit units. If the higher 8 bits of the ICC register are used as an ICCH register, and the lower 8 bits, as an ICCL register, these registers can be read or written in 8-bit or 1-bit units. Bit 12 can only be read and cleared. Be sure to clear bits 15 to 13, 11 to 5, 3, and 2 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. Do not forcibly clear bits 0, 1, and 4 when they are set to 1. 2. Do not set bit 4 to 1 at the same time as the other bits. 3. Do not set bit 12 to 1. This bit can only be cleared to 0. 4. Be sure to set the ICC register in an uncached area (except setting of bit 4). 15 ICC 0 14 0 13 0 12 LOCKI0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 FILL0 3 0 2 1 0 Address FFFFF070H After reset 0003HNote 0 TCLR1TCLR0 Note The value of this register is 0003H when the reset signal becomes active, and initialization of the tag is automatically started. When initialization of the tag has been completed, the value of this register is cleared to 0000H. Bit position 12 Bit name LOCKI0 Function Indicates the cache lock status of way 0. The cache is locked when way 0 is filled, and this bit is automatically set to 1. When this bit is cleared to 0, cache lock of way 0 is cleared. 0: Way 0 is not locked. 1: Way 0 is locked. 4 FILL0 Sets auto fill of way 0. When this bit is set to 1, way 0 is automatically filled. When auto fill has been completed, this bit is automatically cleared to 0. 0: Filling way 0 is completed. 1: Way 0 is being filled. 1 TCLR1 Sets tag clear of way 1. When this bit is set to 1, the tag of way 1 is cleared (invalidated). When clearing the tag has been completed, this bit is automatically cleared to 0. 0: Clearing tag of way 1 is completed. 1: Tag of way 1 is being cleared. 0 TCLR0 Sets tag clear of way 0. When this bit is set to 1, the tag of way 0 is cleared (invalidated). When clearing the tag has been completed, this bit is automatically cleared to 0. 0: Clearing tag of way 0 is completed. 1: Tag of way 0 is being cleared. User's Manual U16031EJ4V1UD 165 CHAPTER 4 BUS CONTROL FUNCTION (2) Instruction cache data configuration register (ICD) This register sets the address of the memory area that is automatically filled by the auto fill function. This register can be read or written in 16-bit units. Be sure to clear bit 0 to 0. If it is set to 1, the operation is not guaranteed. Cautions 1. Do not rewrite the ICD register during the auto fill operation. guaranteed if it is rewritten. 2. Because the default value of the ICD register is undefined, be sure to set a value to the ICD register when the auto fill function is used, and then set the FILL0 bit of the ICC register to 1. If the FILL0 bit of the ICC register is set to 1 without setting a value to the ICD register, the operation is not guaranteed. The operation is not 15 ICD 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Address FFFFF074H After reset Undefined ICD ICD ICD ICD ICD ICD ICD ICD ICD ICD ICD ICD ICD ICD 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit position 14 to 1 Bit name ICD14 to ICD1 Function Set the higher 14 bits of tag information (bits 25 to 12 of the first address of the memory area to be automatically filled). 166 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.9.5 Tag clear function The tag of one way is cleared (invalidated). After reset, all the ways, tags, and LRU are automatically cleared (invalidated). The instruction cache tag is cleared using the following procedure. <1> The ICC register is read to confirm that both the TCLR0 and TCLR1 bits are cleared to 0. <2> The ICC register is read to confirm that the LOCKI0 bit is cleared to 0. Bit 13 of the ICC register is always cleared to 0. <3> The TCLR0 and TCLR1 bits of the ICC register are set as follows. Cautions 1. Perform operations <1> to <3> above (tag clear) in an uncached area (the tag is not cleared from a cacheable area). * To clear both ways 0 and 1 at the same time (a) Set the TCLR0 and TCLR1 bits to 1. (b) Read the TCLR0 and TCLR1 bits to confirm that they are cleared to 0. * To clear ways 0 and 1 separatelyNote (a) Set the TCLR0 bit to 1. (b) Read the TCLR0 bit to confirm that it is cleared to 0. (c) Set the TCLR1 bit to 1. (d) Read the TCLR1 bit to confirm that it is cleared to 0. Note The ways can be cleared separately also in the order of (c) - (d) - (a) - (b). 2. The counter for clearing the tag of ways 0 and 1 is shared. Therefore, clear the tag (by setting the TCLR0 or TCLR1 bit of the ICC register) when the counter for clearing the tag is stopped (when TCLR0 = TCLR1 = 0). When clearing the tags of ways 0 and 1 separately, the counter stops while a tag is being cleared if the tag of one other way is cleared while the tag of the other way is being cleared (TCLR0 or TCLR1 = 1). Consequently, the tag cannot be cleared correctly because the tag of the other way is cleared with the counter indicating a midway value. Be sure to clear the tag of one other way after confirming that the tag of the other way has been cleared (TCLR0 or TCLR1 = 0). There is no problem if both the bits are set at the same time as follows. mov LOP0: ld.h cmp bnz st.h LOP1: ld.h cmp bnz ICC[r0], r1 r0, r1 LOP1 ICC[r0], r1 r0, r1 LOP0 r2, ICC[r0] 0x3, r2 3. Do not perform other processing in parallel with clearing the tag until it is confirmed by reading the TCLR0 and TCLR1 bits of the ICC register that the tag has been cleared to 0. User's Manual U16031EJ4V1UD 167 CHAPTER 4 BUS CONTROL FUNCTION 4.9.6 Auto fill function (way 0 only) The instruction of one way is automatically filled. The way that has been filled automatically is automatically locked and prohibited from being written, and performs the same operation as ROM that can be accessed in one cycle. After the way is unlocked, it operates as an instruction cache again. The instruction cache is automatically filled using the following procedure. <1> Clear (invalidate) the tag of way 0 (see 4.9.5 Tag clear function). <2> Set information on the tag corresponding to the memory area to be automatically filled to the ICD register. <3> Branch to the cacheable area corresponding to the tag information set to the ICD register. <4> Set the FILL0 bit of the ICC register to 1. <5> When auto fill is completed, the LOCKI0 bit of the ICC register is automatically set to 1, and way 0 is locked. At this time, read the FILL0 bit of the ICC register at the same time to confirm that this bit is cleared to 0. Caution Perform the above operations in the following areas. <1>, <2>, <3> ........ Uncached area <4> ........................ Cacheable area If the FILL0 bit of the ICC register is set to 1 from an uncached area, auto fill cannot be executed (is invalidated). <5> ........................ This can be done from both an uncached area and a cacheable area. Remark 4.9.7 Cautions When a refill read cycle is activated by the occurrence of a cache miss, the instruction read in that bus cycle may be discarded without being registered in the instruction cache. When this operation occurs for a conditional branch instruction in a program loop, for example, an illegal refill read cycle occurs in the subsequent cache line each time the program loops, which degrades the system performance. The effect of performance degradation is particularly large in a small-scale loop. However, program execution is performed normally even under this circumstance and the execution result is logically correct. In order to make up for performance degradation due to the uncertain operation by the instruction cache, an instruction RAM is provided in the V850E/ME2, which assures certain instruction execution in a 1-clock pitch. Therefore, execute a routine that may cause this problem using the instruction RAM. To unlock the way, clear the LOCKI0 bit of the ICC register to 0. 168 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.10 Internal Instruction RAM Control Function The V850E/ME2 has 128 KB of instruction RAM (16 KB x 32 bits x 2 banks). While one bank is being read, the other bank can be written in parallel. 4.10.1 Internal instruction RAM mode register (IRAMM) (1) Internal instruction RAM mode register (IRAMM) This register specifies a mode in which the instruction RAM is accessed. This register can be read or written in 8-bit or 1-bit units. Cautions 1. When the setting of a mode is changed, the next access (such as code fetching) to the internal instruction RAM may be executed first because of the pipeline operation of the CPU. When the setting of the IRAMM register is changed, therefore, be sure to read the IRAMM register to confirm that writing has been executed, and then execute an access to the internal instruction RAM. 2. Data can be written to the internal instruction RAM only by a word access. 3. Address miss-align access to the internal instruction RAM is prohibited. 7 IRAMM 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFF80AH After reset 03H 0 IRAMM1 IRAMM0 Bit position 1 Bit name IRAMM1 Function Specifies the access mode of instruction RAM bank 1. 0: Read mode 1: Write mode 0 IRAMM0 Specifies the access mode of instruction RAM bank 0. 0: Read mode 1: Write mode Figure 4-8. Memory Map of Internal Instruction RAM 001FFFFH Instruction RAM bank 1 (64 KB) 0010000H 000FFFFH Instruction RAM bank 0 (64 KB) 0000000H User's Manual U16031EJ4V1UD 169 CHAPTER 4 BUS CONTROL FUNCTION 4.10.2 Operation (1) Read operation The internal instruction RAM can be read by normal RAM access without having to be aware of the banks if the read mode is selected by the IRAMM register. Cautions 1. A bank in the write mode cannot be read. 2. The internal instruction RAM (in the read mode) is accessed using the x1 internal system clock (fCLK). (2) Write operation The internal instruction RAM can be written by normal RAM access without having to be aware of the banks if the write mode is selected by the IRAMM register. Cautions 1. A bank in the read mode cannot be written. 2. Internal instruction RAM bank 0 area is allocated to interrupt and exception tables. Disable interrupts until writing an instruction code to bank 0 of the internal instruction RAM is completed. Similarly, disable interrupts when bank 0 of the internal instruction RAM is set in the write mode. For disabling maskable interrupts, refer to interrupt mask registers 0 to 5 (IMR0 to IMR5) (7.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5)). To disable the non-maskable interrupt, set the NP bit of the PSW to 1 to disable multiple interrupts (see 3.2.2 (4) Program status word (PSW)). For the NMI mask operation when reset is cleared, refer to the NMI reset status register (NRS) (7.3.6 NMI reset status register (NRS)). 3. Since the internal instruction RAM (in the write mode) is accessed using BUSCLK (internal instruction RAM (in the read mode) is accessed using internal system clock (fCLK)), programmable waits, address setup waits, and idle states can be inserted for the CS0 space. 170 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.10.3 Cautions (1) Disable all interrupts from when reset is cleared until when program codes are completely transferred to the internal instruction RAM. It is not necessary to disable maskable interrupts because they are masked by default. Because the software exception and exception trap cannot be masked, do not execute the TRAP and DBTRAP instructions until transfer of program codes to the internal instruction RAM is completed. (2) After reset has been cleared, the NMI input is masked by hardware. The NMI is unmasked as soon as the IRAMM0 bit of the IRAMM register has been cleared to 0. (3) To write data to instruction RAM bank 0 of the internal instruction RAM, set the NP bit of the PSW to 1 to disable the NMI and maskable interrupts and suppress occurrence of the software exception and exception trap. Clear the NP bit by setting the IRAMM0 bit of the IRAMM register to 1 and confirming that the read mode is set, after the program has been rewritten. (4) NMI or maskable interrupt requests that have been generated while the NP bit of the PSW is set to 1 are held pending. An NMI request is acknowledged immediately after the NP bit has been cleared to 0. A maskable interrupt is acknowledged immediately after the NP bit has been cleared to 0, if the interrupt request is not cleared (by clearing the xxIFn bit of the interrupt control register (xxICn) to 0), if interrupts are not disabled (DI status), and if the xxMKn bit of the interrupt control register is not set to 1 before the NP bit is cleared to 0. However, only one interrupt request, NMI request or a maskable interrupt request, can be held pending per interrupt source. Even if the same interrupt request is generated more than once, only the first interrupt request is acknowledged (xx: Peripheral unit identification name (see Table 7-2), n: Peripheral unit number (see Table 7-2)). (5) When the internal instruction RAM is accessed (in the write mode), the CS0 signal, address bus, and data bus output data. The external bus control signals other than UUWR, ULWR, LUWR, LLWR, and WR become active. If output of the IOWR signal is enabled by setting the IOEN bit of the BCP register to 1, the IOWR signal becomes inactive. User's Manual U16031EJ4V1UD 171 CHAPTER 4 BUS CONTROL FUNCTION 4.11 Bus Hold Function 4.11.1 Function outline If the PCM2 and PCM3 pins are specified in the control mode, the HLDAK and HLDRQ functions become valid. If it is determined that the HLDRQ pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin are shifted to high impedance and then released (bus hold state). If the HLDRQ pin becomes inactive (high level) and the bus mastership request is canceled, driving of these pins begins again. During the bus hold period, the internal operations of the V850E/ME2 continue until the external memory or an onchip peripheral I/O register is accessed. The bus hold state can be known by the HLDAK pin becoming active (low level). The period from when the HLDRQ pin becomes active (low level) to when the HLDAK pin becomes active (low level) is at least 2 clocks. In a multiprocessor configuration, etc., a system with multiple bus masters can be configured. State Data Bus Width 32 bits Access Type Timing at Which Bus Hold Request Cannot Be Acknowledged Between first and second accesses Between second and third accesses Word access for 4n+2 address Word access for 4n+3 address Between first and second accesses Between first and second accesses Between second and third accesses Halfword access for odd address 16 bits Word access for even address Word access for odd address Between first and second accesses Between first and second accesses Between second and third accesses Halfword access for odd address 8 bits Word access Between first and second accesses Between second and third accesses Between third and forth accesses Halfword access Read modify write access of bit manipulation instruction - - Between first and second accesses Between read access and write access Between first and second accesses Between first and second accesses CPU bus lock Word access for 4n+1 address Cautions 1. When an external bus master accesses SDRAM during a bus hold state, make sure that the external bus master executes the all-bank precharge command. The CPU always executes the all-bank precharge command to release a bus hold state. In a bus hold state, do not allow an external bus master to change the SDRAM command register value. 2. The HLDRQ function is invalid during a reset period. The HLDAK pin becomes active either immediately after or after the insertion of a 1-clock address cycle from when the RESET pin is set to inactive following the simultaneous activation of the RESET and HLDRQ pins. When a bus master other than the V850E/ME2 is externally connected, use the RESET signal for bus arbitration at power-on. 172 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.11.2 Bus hold procedure The procedure of the bus hold function is illustrated below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests held pending <3> End of current bus cycle <4> Transition to bus idle state <5> HLDAK = 0 Bus hold state Normal state <6> HLDRQ = 1 acknowledged <7> HLDAK = 1 <8> Pending bus cycle start requests released <9> Start of bus cycle Normal state HLDRQ (input) HLDAK (output) <1> <2> <3><4> <5> <6> <7><8><9> 4.11.3 Operation in power-save mode In the software STOP or IDLE mode, the internal system clock (fCLK) is stopped. Consequently, the bus hold state is not set since the HLDRQ pin cannot be acknowledged even if it becomes active. In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus hold state is set. When the HLDRQ pin becomes inactive after that, the HLDAK pin also becomes inactive. As a result, the bus hold state is cleared and the HALT mode is set again. User's Manual U16031EJ4V1UD 173 CHAPTER 4 BUS CONTROL FUNCTION 4.11.4 Bus hold timing (1) If bus hold request is issued when bus cycle is not generated TINote 1 BUSCLK (output) TI Note 1 TH TH TINote 1 T0Note 2 HLDRQ (input) HLDAK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Undefined Undefined RD (output) Note 3 (output) D0 to D31 (input) WAIT (input) Notes 1. 2. 3. This idle state (TI) is independent of the BCC register setting. State (T0) inserted between bus cycles LLWR/LLBE/LLDQM, UUWR/UUBE/UUDQM, LUWR/LUBE/LUDQM, ULWR/ULBE/ULDQM, WE/WR, IORD, IOWR, SDRAS, SDCAS Remarks 1. The circle indicates the sampling timing. 2. The broken lines indicate the high-impedance state. 174 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.11.5 Bus hold timing (SRAM) (1) SRAM (when read, without speculative read, no idle state inserted, BUSCLK = fCLK/2) T0 BUSCLK (output) HLDRQ (input) HLDAK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) IORD Note 3 Note 1 T1 T2 TI Note 2 TH TH T0 Note 1 Address Undefined Undefined , RD (output) Note 4 (output) WR, IOWR (output) D0 to D31 (input) WAIT (input) Data Notes 1. 2. 3. 4. State (T0) inserted between bus cycles This idle state (TI) is independent of the BCC register setting. When the IOEN bit of the BCP register is set to 1. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 175 CHAPTER 4 BUS CONTROL FUNCTION (2) SRAM (when read, with speculative read, no idle state inserted, BUSCLK = fCLK/2) T1 BUSCLK (output) HLDRQ (input) HLDAK (output) A0 to A25 (output) T2 T1 T2 TI Note 1 TH TH Address Undefined BCYST (output) CS0 to CS7 (output) IORD Note 3 , RD (output) Note 4 (output) WR, IOWR (output) D0 to D31 (input) WAIT (input) Data Data Notes 1. 2. 3. 4. This idle state (TI) is independent of the BCC register setting. State (T0) inserted between bus cycles When the IOEN bit of the BCP register is set to 1. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 176 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (3) SRAM (when written, two idle states inserted, BUSCLK = fCLK/2) T0Note 1 BUSCLK (output) HLDRQ (input) HLDAK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) IOWRNote 4, WR (output) Note 5 (output) RD, IORD (output) T1 T2 TINote 2 TINote 2 TINote 3 TH TH T0Note 1 Address Undefined Undefined D0 to D31 (input) WAIT (input) Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles This idle state (TI) is inserted by means of a BCC register setting. This idle state (TI) is independent of the BCC register setting. When the IOEN bit of the BCP register is set to 1. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 177 CHAPTER 4 BUS CONTROL FUNCTION 4.11.6 Bus hold timing (SDRAM) (1) SDRAM (when read, latency = 2, no idle state inserted) T0 BUSCLK (output) HLDRQ (input) HLDAK (output) A2 to A11 (output) A12 Note 4 Note 1 TACT TREAD TLATE TLATE TI Note 2 TH TH TI Note 2 T0 Note 1 TPRE Note 3 Row Row Bnk. Address Col. Undefined Undefined Undefined Undefined Undefined Undefined Undefined (output) Bank address (output) Note 5 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 6 (output) Note 7 (output) D0 to D31 (input) SDCKE (output) H H Address Undefined Data Notes 1. 2. 3. 4. 5. 6. 7. State (T0) inserted between bus cycles This idle state (TI) is independent of the BCC register setting. The all-bank precharge command is always executed. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) indicates the sampling timing. Remarks 1. The circle 3. n = 1, 3, 4, 6 m = 0 to 3 2. The broken lines indicate the high-impedance state. xx = UU, UL, LU, LL 4. Bnk.: Bank address Col.: Column address Row: Row address 178 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (2) SDRAM (when read, latency = 2, two idle states inserted, 32-bit bus width) T0 BUSCLK (output) HLDRQ (input) HLDAK (output) A2 to A11 (output) A12 Note 5 Note 1 TACT TREAD TLATE TLATE TI Note 2 TI Note 2 TI Note 3 TH TH TI Note 3 T0 Note 1 TPRE Note 4 Row Row Bnk. Address Col. Undefined Undefined Undefined Undefined Undefined Undefined Undefined (output) Bank address (output) Note 6 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 7 (output) Note 8 (output) D0 to D31 (input) SDCKE (output) H H Address Undefined Data Notes 1. 2. 3. 4. 5. 6. 7. 8. State (T0) inserted between bus cycles This idle state (TI) is inserted by means of a BCC register setting. This idle state (TI) is independent of the BCC register setting. The all-bank precharge command is always executed. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) indicates the sampling timing. Remarks 1. The circle 3. n = 1, 3, 4, 6 m = 0 to 3 2. The broken lines indicate the high-impedance state. xx = UU, UL, LU, LL 4. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 179 CHAPTER 4 BUS CONTROL FUNCTION (3) SDRAM (when written) T0Note 1 BUSCLK (output) TACT TWR TINote 2 TH TH TINote 2 T0Note 1 TPRENote 3 HLDRQ (input) HLDAK (output) A2 to A11 (output) A12Note 4 (output) Bank address (output) Note 5 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 6 (output) Note 7 (output) D0 to D31 (I/O) SDCKE (output) H Data Row Row Bnk.A Address Address Col. Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Notes 1. 2. 3. 4. 5. 6. 7. State (T0) inserted between bus cycles This idle state (TI) is independent of the BCC register setting. The all-bank precharge command is always executed. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) indicates the sampling timing. Remarks 1. The circle 3. n = 1, 3, 4, 6 m = 0 to 3 2. The broken lines indicate the high-impedance state. xx = UU, UL, LU, LL 4. Bnk.: Bank address Col.: Column address Row: Row address 180 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (4) SDRAM (when written, when bus hold request acknowledged during on-page access) T0 BUSCLK (output) HLDRQ (input) HLDAK (output) A2 to A11 (output) A12Note 4 (output) Bank address (output) Note 5 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 6 (output) D0 to D31 (I/O) SDCKE (output) H Note 1 TWR TI Note 2 TI Note 2 TH TH TI Note 2 T0 Note 1 TPRE Note 3 Col. Undefined Undefined Undefined Undefined Undefined Undefined Undefined Address Undefined Data Notes 1. 2. 3. 4. 5. 6. State (T0) inserted between bus cycles This idle state (TI) is independent of the BCC register setting. The all-bank precharge command is always executed. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM indicates the sampling timing. Remarks 1. The circle 3. n = 1, 3, 4, 6 2. The broken lines indicate the high-impedance state. 4. Col.: Column address User's Manual U16031EJ4V1UD 181 CHAPTER 4 BUS CONTROL FUNCTION 4.12 Bus Priority Order There are five external bus cycles: bus hold, instruction fetch, operand data access, DMA cycle, and refresh cycle. In order of priority, bus hold is the highest, followed by the refresh cycle, DMA cycle, operand data access, and instruction fetch, in that order. An instruction fetch may be inserted between a read access and write access during a read modify write access. Also, an instruction fetch may be inserted between bus accesses when the CPU bus clock is used. Table 4-2. Bus Priority Order Priority Order High External Bus Cycle Bus hold Refresh cycle DMA cycle Operand data access Low Instruction fetch Bus Master External device SDRAM controller DMA controller CPU CPU 4.13 Boundary Operation Conditions 4.13.1 Program space Branching to the on-chip peripheral I/O area is prohibited. If the above is performed, undefined data is fetched, and fetching from the external memory is not performed. 4.13.2 Data space The V850E/ME2 is provided with an address misalign function. Through this function, regardless of the data format (word or halfword), data can be allocated to all addresses. However, in the case of word data and halfword data, if the data is not subject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) External bus width: 16 bits (a) In the case of halfword-length data access When the address's LSB is 1, a byte-length bus cycle will be generated 2 times. (b) In the case of word-length data access (i) When the address's LSB is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle. (ii) When the address's lower 2 bits are 10, a halfword-length bus cycle will be generated 2 times. (2) External bus width: 32 bits (a) In the case of halfword-length data access When the address's lower 2 bits are 11, a byte-length bus cycle will be generated 2 times. (b) In the case of word-length data access When the address's lower 2 bits are 10, a halfword-length bus cycle will be generated 2 times. 182 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION 4.14 Timing at Which T0 State Is Not Inserted A T0 state is not inserted at the following timing. (1) Read During a refill operation when instruction cache is used (in the second and subsequent cycles) During speculative reading (in the second and subsequent cycles) If a read request (including a read request by instruction fetch or DMA) is generated before a write operation to the external device is completed when a read operation occurs immediately after a write operation If a read request (including a read request by instruction fetch or DMA) that is greater than the bus width of the external device is generated (in the second and subsequent cycles) [Example] * 32-bit read access with 16-bit external bus width * 32-bit or 16-bit read access with 8-bit external bus width (2) Write If a write request (including a write request by DMA) is generated before a write operation to the external device is completed when a write operation occurs immediately after a write operation, and data is stored in the write buffer (a cycle in which the data stored in the write buffer is written to the external device) If a write request (including a write request by DMA) is generated during a speculative read operation (if data is stored in the write buffer) If a write request (including a write request by DMA) greater than the bus width of the external bus is generated (after the second and subsequent cycles) [Example] * 32-bit write access with external 16-bit bus width * 32-bit or 16-bit write access with external 8-bit bus User's Manual U16031EJ4V1UD 183 CHAPTER 4 BUS CONTROL FUNCTION 4.15 Cautions Cautions concerning the bus control function are shown below. (1) Access to internal instruction RAM (in write mode) Since the internal instruction RAM (in the write mode) is accessed using BUSCLK (internal instruction RAM (in the read mode) is accessed using internal system clock (fCLK)), programmable waits, address setup waits, and idle states can be inserted in the CS0 space. (2) Cautions on setting LBCn register * When the speculative read function is set for each CSn space, do not insert an idle state in the CSn space for which the speculative read function is enabled by the BCC register (n = 0 to 7). If an idle state is required to be inserted in the CSn space for which the speculative read function is enabled, enable the speculative read function for all CSn spaces (set the LBC0 and LBC1 registers to 3333H) or disable the speculative read function for all CSn spaces (set the LBC0 and LBC1 registers to 0000H). * Do not enable the speculative read function for SDRAM that is accessed via a 32-bit bus. (3) Write operation to external device When data is written to an external device, the write operation to the external device may not be executed even when a CPU write operation has been completed by the write buffer. The CPU can access the on-chip peripheral I/O registers after the write operation has been completed even if data exist in the write buffer. Therefore, if it is necessary to change the value of an on-chip peripheral I/O register after completion of execution of an external memory cycle, write the same value as the default value to the LBC0 or LBC1 register or write 00H to the WAS register before writing the on-chip peripheral I/O register whose value is to be changed. When writing an on-chip peripheral I/O register other than the LBC0 or LBC1 register without writing the same value as the default value to the LBC0 or LBC1 register, or writing an on-chip peripheral I/O register other than the WAS register without writing 00H to the WAS register, the register value may be changed before completion of the external memory cycle. (4) 2-cycle transfer that writes data to external device During 2-cycle transfer that writes data to the external device, the write operation to the external device may not be completed even if TCn bit of DCHCn register = 1 (DMA transfer completion) is read by the write buffer (n = 0 to 3). If it is necessary to change the value of an on-chip peripheral I/O register after completion of DMA transfer (completion of a write operation to the external device), perform either of the following operations. * Monitor the TCn signal (the TCn signal becomes active in synchronization with a write operation to the external device). * After detecting setting (to 1) of the TCn bit, write 00H to the WAS register or write the same value as the default value to the LBC0 or LBC1 register, and then change the value of the on-chip peripheral I/O register. If the value of an on-chip peripheral I/O register other than the LBC0 and LBC1 registers is changed without writing the same value to LBC0 or LBC1 or the value of an on-chip peripheral I/O register other than the WAS register is changed without writing 00H to the WAS register, the value of the on-chip peripheral I/O register may be changed before completion of DMA transfer. 184 User's Manual U16031EJ4V1UD CHAPTER 4 BUS CONTROL FUNCTION (5) Caution on setting BMC register Set the number of waits (using the DWk2 to DWk0 bits of the DWCm register) or address setup waits (using the ACk1 and ACk0 bits of the ASC register) for all the CS spaces in which an SRAM or page-ROM interface cycle is activated to 1 or more when the same clock is used as the internal system clock and bus clock (CKM1 and CKM0 bits of the BMC register = 00) and the speculative read function is enabled (RBk1 and RBk0 bits of LBCm register = 11) (m = 0, 1, k = 0 to 7). (6) Caution on setting DWCn register When the internal instruction RAM area is accessed (in the write mode), the programmable wait value set for the CS0 space becomes valid. (7) Caution on setting ASC register Be sure to set the number of address setup wait states to 1 or more if the CSn signal is delayed using the PFCCS register (n = 0 to 7). (8) Caution on BCP register setting If the internal instruction RAM is accessed while the IOEN bit of the BCP register is set (1) (in the write mode), the IOWR signal becomes inactive. (9) Caution on setting BCC register The CSn signal does not become active in the idle state (n = 0 to 7). (10) Caution on setting BHC register * Be sure to set the BHC register in an uncached area (instructions cannot be fetched correctly if it is set from a cacheable area). * The area that includes the instruction that sets the BHC register cannot be set from an uncached area to a cacheable area, or from a cacheable area to an uncached area. In this case, branch to area 1 and then set area 0 to a cacheable area by an instruction in area 1. If necessary, branch to area 0 again. An uncached area and a cacheable area can be set in any CS space in the internal instruction RAM area. * If adjacent memory areas are a cacheable area and an uncached area, only a branch instruction can be used to successively access this memory boundary. The operation is not guaranteed if this memory boundary is successively accessed by an instruction other than a branch instruction. (11) Caution on setting IRAMM register * Data can be written to the internal instruction RAM only by a word access. * Address miss-align access to the internal instruction RAM is prohibited. (12) Write operation to internal instruction RAM area Internal instruction RAM bank 0 area is allocated to interrupt and exception tables. Disable interrupts until writing an instruction code to bank 0 of the internal instruction RAM is completed. Similarly, disable interrupts when bank 0 of the internal instruction RAM is set in the write mode. User's Manual U16031EJ4V1UD 185 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features * SRAM is accessed in a minimum of 2 states. * Up to 7 states of programmable data waits can be inserted by setting the DWC0 and DWC1 registers (DMA flyby transfer: FWC register). * Data wait can be controlled via WAIT pin input. * Up to 3 idle states can be inserted after a read/write cycle by setting the BCC register (DMA flyby transfer: FIC register). * Up to 3 address setup wait states can be inserted by setting the ASC register. * DMA flyby transfer can be activated (SRAM external I/O, external I/O SRAM) 186 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.2 SRAM connection Examples of connection to SRAM are shown below. Figure 5-1. Examples of Connection to SRAM (1/2) (a) When data bus width is 8 bits V850E/ME2 A2 to A18 D24 to D31 CSn RD UUWR A0 to A16 I/O1 to I/O8 SRAM CS (128 Kwords x 8 bits) OE WE A0 to A16 I/O1 to I/O8 SRAM (128 Kwords x 8 bits) CS OE WE A0 to A16 I/O1 to I/O8 SRAM CS (128 Kwords x 8 bits) OE WE A0 to A16 I/O1 to I/O8 SRAM CS (128 Kwords x 8 bits) OE WE D16 to D23 ULWR D8 to D15 LUWR D0 to D7 LLWR Remark n = 0 to 7 User's Manual U16031EJ4V1UD 187 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. Examples of Connection to SRAM (2/2) (b) When data bus width is 16 bits V850E/ME2 A2 to A19 D16 to D31 A0 to A17 I/O1 to I/O16 SRAM (256 Kwords x 16 bits) CSn RD UUBE ULBE WR CS OE HB LB WE D0 to D15 A0 to A17 I/O1 to I/O16 SRAM (256 Kwords x 16 bits) LUBE LLBE CS OE HB LB WE Remark n = 0 to 7 188 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.3 SRAM, external ROM, external I/O access Figure 5-2. SRAM, External ROM, External I/O Access Timing (1/10) (a) When read (without speculative read) T0Note 1 BUSCLK (output) T1 T2 T0Note 1 T1 TW T2 T0Note 1 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Address Address RD (output) Note 2 (output) Data Data D0 to D31 (input) WAIT (input) Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 189 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (2/10) (b) When read (without speculative read, address setup wait, idle state insertion) TASW T1 T2 TI T0Note 1 T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Address RD (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 190 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (3/10) (c) When read (with speculative read, 32-bit bus width) T0Note 1 BUSCLK (output) T1 T2 T1 T2 T1 T2 T1 T2 T0Note 1 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Address A Address A+4 Address A+8 Address A+C RD (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 191 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (4/10) (d) When read (with speculative read, access on another line) Access by CPU Read from Address (A) Read from Address (B) T2 T1 T2 T1 T2 T1 T2 T1 T2 T0Note 1 BUSCLK (output) T1 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Address A Address A+4 Address A+8 Address A+C Address B RD (output) Note 2 (output) D0 to D31 (input) WAIT (input) Speculative read cycle (fill cycle of speculative read buffer) Speculative read cycle Data Data Data Data Data Penalty cycle accompanying with another line access request Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 192 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (5/10) (e) When read (with speculative read, 32-bit bus width, address setup wait, idle state insertion) T0Note 1 TASW BUSCLK (output) Address A Address A+4 Address A+8 Address A+C T1 T2 TI TASW T1 T2 TI TASW T1 T2 TI TASW T1 T2 TI T0Note 1 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 193 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (6/10) (f) When written (1/2) Access by CPU Write to address (A) Write to address (B) T2 T0Note 1 BUSCLK (output) T1 T0Note 1 T1 TW T2 T0Note 1 A0 to A25 (output) Address A Address B BCYST (output) CS0 to CS7 (output) WR (output) Note 2 (output) D0 to D31 (output) Data Data WAIT (input) (f) When written (2/2) Access by CPU Write to address (A) Write to address (B) T2 T1 TW T2 T0Note 1 BUSCLK (output) T1 T0Note 1 A0 to A25 (output) Address A Address B BCYST (output) CS0 to CS7 (output) WR (output) Note 2 (output) D0 to D31 (output) Data Data WAIT (input) Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 194 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (7/10) (g) When written (address setup wait, idle state insertion) T0Note 1 BUSCLK (output) TASW T1 T2 TI A0 to A25 (output) Address BCYST (output) CS0 to CS7 (output) WR (output) Note 2 (output) Data D0 to D31 (output) WAIT (input) Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 195 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (8/10) (h) For read (without speculative read) write operation T0Note 1 BUSCLK (output) T1 T2 T0Note 1 T1 T2 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Address Address RD (output) WR (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 196 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (9/10) (i) For write read operation (1/2) Access by CPU Write to address (A) Read from address (B) T0Note 1 BUSCLK (output) T1 T2 T0Note 1 T1 T2 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Address A Address B RD (output) WR (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 197 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (10/10) (i) For write read operation (2/2) Access by CPU Write to address (A) Read from address (B) T0Note 1 BUSCLK (output) T1 T2 T1 T2 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) Address A Address B RD (output) WR (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 198 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2 Page ROM Controller (ROMC) The page ROM controller (ROMC) is provided for accessing ROM (page ROM) with a page access function. Addresses are compared with the immediately preceding bus cycle and wait control for normal access (off-page) and page access (on-page) is executed. This controller can handle page widths from 8 to 128 bytes. 5.2.1 Features * Direct connection to 8-bit/16-bit/32-bit page ROM supported * For 32-bit bus width: 2/4/8/16/32-word page access supported For 16-bit bus width: 4/8/16/32/64-word page access supported For 8-bit bus width: 8/16/32/64/128-word page access supported * Page ROM is accessed in a minimum of 2 states. * On-page judgment function * Addresses to be compared can be changed by setting the PRC register. * Up to 7 states of programmable data waits can be inserted by setting the following registers. During on-page cycle: PRC register During off-page cycle: DWC0 and DWC1 registers During DMA flyby cycle: FWC register * Waits can be controlled via WAIT pin input. * DMA flyby cycle can be activated (page ROM external I/O) * SRAM write cycle is started when a write cycle request is issued to a CSn space (n = 0 to 7) where page ROM is allocated User's Manual U16031EJ4V1UD 199 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.2 Page ROM connection Examples of connection to page ROM are shown below. Figure 5-3. Examples of Connection to Page ROM (a) When data bus width is 16 bits V850E/ME2 A2 to A21 D16 to D31 A0 to A19 O0 to O15 Page ROM (1 Mword x 16 bits) CSn RD CE OE D0 to D15 A0 to A19 O0 to O15 Page ROM (1 Mword x 16 bits) CE OE (b) When data bus width is 8 bits V850E/ME2 A2 to A22 D24 to D31 CSn RD A0 to A20 O0 to O7 Page ROM CE (2 Mwords x 8 bits) OE D16 to D23 A0 to A20 O0 to O7 Page ROM (2 Mwords x 8 bits) CE OE D8 to D15 A0 to A20 O0 to O7 Page ROM CE (2 Mwords x 8 bits) OE D0 to D7 A0 to A20 O0 to O7 Page ROM CE (2 Mwords x 8 bits) OE Remark n = 0 to 7 200 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.3 On-page/off-page judgment Whether a page ROM cycle is on-page or off-page is judged by latching the address of the previous cycle and comparing it with the address of the current cycle. If no speculative reading is specified (RBn1 and RBn0 bits of the LBCm register = 00, 01) or use of the instruction cache is not specified, an off-page cycle is always started, except in the following cases (m = 0, 1, n = 0 to 7). * 16/32-bit access to 8-bit bus * 32-bit access to 16-bit bus One of the addresses (A3 to A6) is set as the masking address (no comparison is made) according to the configuration of the connected page ROM and the number of continuously readable bits set by the PRC register. An example of controlling address masking when four page ROMs of 1 Mword x 8 bits are connected is shown below. Figure 5-4. Example of Control by MA6 to MA3 Bits of PRC Register Internal address latch (immediately preceding address) a25 a24 a23 a22 a21 a7 a6 a5 a4 a3 MA6 MA5 MA4 MA3 0 0 0 1 PRC register setting Comparison Note V850E/ME2 address output A25 A24 A23 A22 A21 A7 A6 A5 A4 A3 A2 A1 A0 Page ROM address A19 A5 Off-page address A4 A3 A2 A1 A0 On-page address Note Not used with a 32-bit data bus width User's Manual U16031EJ4V1UD 201 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.4 Page ROM configuration register (PRC) The masking address (no comparison is made) out of the addresses (A3 to A6) corresponding to the configuration of the connected page ROM and the number of bits that can be read continuously, as well as the number of waits corresponding to the internal system clock (fCLK), are set. This register can be read or written in 16-bit units. Caution Write to the PRC register after reset, and then do not change the set value. Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the PRC register is complete. However, it is possible to access external memory areas whose initialization settings are complete. 15 PRC 14 13 12 11 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 Address FFFFF49AH After reset 7000H 0 PRW2 PRW1 PRW0 0 MA6 MA5 MA4 MA3 Bit position 14 to 12 Bit name PRW2 to PRW0 Function Sets the number of waits corresponding to the internal system clock (fCLK). The number of waits set by these bits is inserted only for on-page access. For off-page access, the waits set by registers DWC0 and DWC1 are inserted. PRW2 0 0 0 0 1 1 1 1 PRW1 0 0 1 1 0 0 1 1 PRW0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 Number of inserted wait cycles 3 to 0 MA6 to MA3 Each respective address (A6 to A3) corresponding to MA6 to MA3 is masked (by 1). The masked address is not subject to comparison during on/off-page judgment, and is set according to the number of continuously readable bits. MA6 0 0 0 0 1 MA5 0 0 0 1 1 MA4 0 0 1 1 1 MA3 0 1 1 1 1 Number of continuously readable bits 2 x 32 bits, 4 x 16 bits, 8 x 8 bits 4 x 32 bits, 8 x 16 bits, 16 x 8 bits 8 x 32 bits, 16 x 16 bits, 32 x 8 bits 16 x 32 bits, 32 x 16 bits, 64 x 8 bits 32 x 32 bits, 64 x 16 bits, 128 x 8 bits Setting prohibited (The operation cannot be guaranteed if other bits are set.) Other than above 202 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.5 Page ROM access Figure 5-5. Page ROM Access Timing (1/6) (a) When read (without speculative read, 32-bit bus width, other than cache fill operation) T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) H Off-page address Off-page address Off-page address Off-page address T1 T2 T0Note 1 T1 T2 T0Note 1 T1 T2 T0Note 1 T1 T2 T0Note 1 WR (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 203 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (2/6) (b) When read (without speculative read, 32-bit bus width, cache fill operation) Off-page TW Note 2 On-page TO2 On-page TO1 TO2 On-page TO2 T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) Note 3 (output) D0 to D31 (input) WAIT (input) H T1 T2 TO1 TO1 T0Note 1 Address A Address A+4 Address A+8 Address A+C Data Data Data Data Notes 1. 2. 3. State (T0) inserted between bus cycles Programmable wait = 1 wait insertion UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 204 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (3/6) (c) When read (with speculative read, 32-bit bus width) Off-page T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) Address A Address A+4 Address A+8 Address A+C T1 TW TW TW T2 TO1 On-page TOW TO2 TO1 On-page TOW TO2 TO1 On-page TOW TO2 T0Note 1 WR (output) H Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 205 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (4/6) (d) When read (without speculative read, address setup wait, idle state inserted, 32-bit bus width, other than cache fill operation) T0Note 1 TASW BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) H Off-page address Off-page address Off-page address Off-page address T1 T2 TI T0Note 1 TASW T1 T2 TI T0Note 1 TASW T1 T2 TI T0Note 1 TASW T1 T2 TI T0Note 1 WR (output) Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 206 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (5/6) (e) When read (without speculative read, address setup wait, idle state inserted, 32-bit bus width, cache fill operation) Off-page T1 On-page TO1 TO2 On-page TO1 TO2 On-page TO2 T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) H TASW T2 TO1 TI Address A0 Address A+4 Address A+8 Address A+C Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 207 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (6/6) (f) When read (with speculative read, address setup wait, idle state inserted, 32-bit bus width) Off-page T0Note 1 TASW BUSCLK (output) T1 TW TW TW T2 TO1 On-page TOW TO2 TO1 On-page TOW TO2 TO1 On-page TOW TO2 TI A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) Address A Address A+4 Address A+8 Address A+C WR (output) H Note 2 (output) D0 to D31 (input) WAIT (input) Data Data Data Data Notes 1. 2. State (T0) inserted between bus cycles UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 208 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3 SDRAM Controller (SDRAMC) 5.3.1 Features * Burst length: 1 * Wrap type: Sequential * CAS latency: 1, 2, and 3 supported (only 2 and 3 supported during DMA flyby transfer) * 4 types of SDRAM can be assigned to 4 memory blocks. * Row and column address multiplex widths can be changed. * Waits (0 to 3 waits) can be inserted between the bank active command and the read/write command. * Supports CBR (auto) refresh and self-refresh. * DMA flyby cycle (from external I/O to SDRAM) can be activated. 5.3.2 SDRAM connection An example of connection to SDRAM is shown below. Figure 5-6. Example of Connection to SDRAM V850E/ME2 A2 to A13 A22, A23Note D16 to D31 A0 to A11 A12, A13 DQ0 to DQ15 SDRAM (1 Mword x 16 bits x 4 banks) BUSCLK SDCKE CSn SDRAS SDCAS UUDQM ULDQM WE CLK CKE CS RAS CAS HDQM LDQM WE A0 to A11 A12, A13 D0 to D15 DQ0 to DQ15 SDRAM (1 Mword x 16 bits x 4 banks) CLK CKE CS RAS CAS HDQM LDQM WE LUDQM LLDQM Note The address signals to be used differ depending on the SDRAM product. Remark n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 209 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.3 Address multiplex function Depending on the value of the SAWn0 and SAWn1 bits in the SCRn register, the row address output in the SDRAM cycle is multiplexed as shown in Figure 5-7 (a) (n = 1, 3, 4, 6). Depending on the value of the SSOn0 and SSOn1 bits of the SCRn register, the column address output in the SDRAM cycle is multiplexed as shown in Figure 57 (b) (n = 1, 3, 4, 6). In Figures 5-7 (a) and (b), a0 to a25 indicate the addresses output from the CPU, and A0 to A25 indicate the address pins of the V850E/ME2. Figure 5-7. Row Address/Column Address Output (1/2) (a) Row address output Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address a25 to a18 a17 a16 a15 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 (SAWn1, SAWn0 bits = 11) Row address (SAWn1, SAWn0 bits = 10) a25 to a18 a17 a16 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 Row address (SAWn1, SAWn0 bits = 01) a25 to a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 Row address (SAWn1, SAWn0 bits = 00) a25 to a18 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 Remark n = 1, 3, 4, 6 (b) Column address output (using all-bank precharge command) Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Column address a25 to a18 a17 a16 a15 a14 a13 a12 a11 1 a9 (SSOn1, SSOn0 bits = 00) Column address (SSOn1, SSOn0 bits = 01) a25 to a18 a17 a16 a15 a14 a13 a12 Column address (SSOn1, SSOn0 bits = 10) a25 to a18 a17 a16 a15 a14 a13 1 1 a10 a9 A8 a8 A7 a7 A6 A5 a6 a5 A4 a4 A3 a3 A2 A1 a2 a1 A0 a0 a8 a7 a6 a5 a4 a3 a2 a1 a0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 Remark n = 1, 3, 4, 6 (c) Column address output (using register write command) Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Column address 0 0 0 0 0 0 0 0 0 0 (SSOn1, SSOn0 bits = 00) Column address (SSOn1, SSOn0 bits = 01) Column address (SSOn1, SSOn0 bits = 10) 0 0 0 0 0 0 0 0 0 0 A8 0 A7 0 A6 A5 A4 A3 0 A2 A1 0 0 A0 0 LTM2 LTM1 LTM0 0 LTM2 LTM1 LTM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTM2 LTM1 LTM0 0 0 0 0 0 0 Remark n = 1, 3, 4, 6 210 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-7. Row Address/Column Address Output (2/2) (d) Column address output (using read/write command) Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Column address a25 to a18 a17 a16 a15 a14 a12 a11 a10 0 a9 (SSOn1, SSOn0 bits = 00) Column address (SSOn1, SSOn0 bits = 01) a25 to a18 a17 a16 a15 a14 a12 a11 Column address (SSOn1, SSOn0 bits = 10) a25 to a18 a17 a16 a15 a14 a12 0 0 a10 a9 A8 a8 A7 a7 A6 A5 a6 a5 A4 a4 A3 a3 A2 A1 a2 a1 A0 a0 a8 a7 a6 a5 a4 a3 a2 a1 a0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 Remark n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 211 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (1) Output of each address and connection of SDRAM The set contents of the SCRn register, physical address, address output from the V850E/ME2, and connection between the V850E/ME2 and SDRAM at each data bus width (8 bits or 16 bits) are described below. (a) At 8-bit data bus width An example of connecting 64 Mb SDRAM (2 Mwords x 8 bits x 4 banks) at 8-bit data bus width is shown below. * Set contents of SCRn register SSOn1, SSOn0 bits = 00: Data bus width = 8 bits RAWn1, RAWn0 bits = 01: Row address width = 12 bits SAWn1, SAWn0 bits = 01: Column address width = 9 bits * Physical address A22, A21: Bank address A20 to A9: Row address A8 to A0: Column address * Address output from V850E/ME2 A22, A21: Bank address A11 to A0: Row address (12 bits), column address (9 bits) (i) Row address, bank address output (with active command) Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 Bank address Row address (ii) Column address output (with read/write command) Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 a11 a10 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 Column address * Connection of V850E/ME2 and SDRAM A22, A21 (V850E/ME2) BA0 (A13), BA1 (A12) (SDRAM) A11 to A0 (V850E/ME2) A11 to A0 (SDRAM) 212 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (b) At 16-bit data bus width An example of connecting 512 Mb SDRAM (8 Mwords x 16 bits x 4 banks) at 16-bit data bus width is shown below. * Set contents of SCRn register SSOn1, SSOn0 bits = 01: Data bus width = 16 bits RAWn1, RAWn0 bits = 10: Row address width = 13 bits SAWn1, SAWn0 bits = 10: Column address width = 10 bits * Physical address A25, A24: A10 to A1: Bank address Column address A23 to A11: Row address * Address output from V850E/ME2 A25, A24: Bank address A13 to A1: Row address (13 bits), column address (10 bits) (i) Row address, bank address output (with active command) Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 Bank address Row address (ii) Column address output (with read/write command) Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 a11 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 Column address * Connection of V850E/ME2 and SDRAM A25, A24 (V850E/ME2) BA0 (A14), BA1 (A13) (SDRAM) A13 to A1 (V850E/ME2) A12 to A0 (SDRAM) User's Manual U16031EJ4V1UD 213 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (c) At 32-bit data bus width An example of connecting 512 Mb SDRAM (256 Mb SDRAM (4 Mwords x 16 bits x 4 banks) x 2) at 32bit data bus width is shown below. * Set contents of SCRn register SSOn1, SSOn0 bits = 10: Data bus width = 32 bits RAWn1, RAWn0 bits = 10: Row address width = 13 bits SAWn1, SAWn0 bits = 01: Column address width = 9 bits * Physical address A25, A24: A10 to A2: Bank address Column address A23 to A11: Row address * Address output from V850E/ME2 A25, A24: Bank address A14 to A2: Row address (13 bits), column address (9 bits) (i) Row address, bank address output (with active command) Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 Bank address Row address (ii) Column address output (with read/write command) Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 Column address * Connection of V850E/ME2 and SDRAM A25, A24 (V850E/ME2) BA0 (A14), BA1 (A13) (SDRAM) A14 to A2 (V850E/ME2) A12 to A0 (SDRAM) 214 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2) Bank address output The V850E/ME2 precharges a bank to access by using a bank precharge command when a row address is output immediately after page change. After bank change, it precharges the bank previously accessed when a column address is output. Therefore, a bank is precharged both when a row address is output and when a column address is output. To connect SDRAM with the contents described in 5.3.3 (1) (a) At 8-bit data bus width, always connect the pins (A22 and A21) of the V850E/ME2 that outputs bank addresses to the bank address pins (A13 and A12) of SDRAM. An example of address output by the bank precharge command when the page or bank is changed if SDRAM is connected with the contents described in 5.3.3 (1) (a) At 8-bit data bus width is shown below. (a) When page is changed (at 8-bit data bus width) When the page is changed, the precharge command outputs the physical addresses to be accessed (a20 and a18 to a9) to the A11 and A9 to A0 pins, and the bank addresses to be accessed (a22 and a21) to the A22 and A21 pins. Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a25 a24 a23 a22 a21 a20 0 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 Bank address to be accessed Row address (b) When bank is changed (at 8-bit data bus width) When the bank is changed, the bank precharge command outputs the physical addresses to be accessed (a8 to a0) to the A8 to A0 pins, and the bank addresses previously accessed (a22 and a21) to the A22 and A21 pins. Address pin A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a12 a11 a10 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 Bank address previously accessed Column address The bits that determine the precharge mode (A10: 8-bit data bus width, A11: 16-bit data bus width, A12: 32-bit data bus width) output a high level when the all bank precharge command is executed, and a low level when any other command is executed for precharging. User's Manual U16031EJ4V1UD 215 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) These registers specify the number of waits and the address multiplex width. The SCRn register corresponds to CSn (n = 1, 3, 4, 6). For example, to connect SDRAM to CS1, set the SCR1 register. These registers can be read or written in 16-bit units. Cautions 1. An SDRAM read/write cycle is not generated prior to executing a register write operation. Access SDRAM after reading the value of the SCRn register and confirming that the WCFn bit is set to 1 ( n = 1, 3, 4, 6). 2. To write to the SCRn register again following access to SDRAM, clear the MEn bit of the BCT0 and BCT1 registers to 0, and then set it to 1 again before performing access (n = 0 to 6). 3. Do not execute continuous instructions to write to the SCRn register. Be sure to insert another instruction between commands to write to the SCRn register. 4. Start accessing SDRAM after all the SCRn registers have been set. Set the RFSn register before setting the SCRn register (n = 1, 3, 4, 6). (1/3) 15 SCR1 14 13 12 11 0 10 0 9 0 8 7 6 5 4 3 2 1 0 Address FFFFF4A4H After reset 30C0H 0 LTM12 LTM11 LTM10 WCF1 BCW11 BCW10 SSO11 SSO10 RAW11 RAW10 SAW11 SAW10 SCR3 0 LTM32 LTM31 LTM30 0 0 0 WCF3 BCW31 BCW30 SSO31 SSO30 RAW31 RAW30 SAW31 SAW30 FFFFF4ACH 30C0H SCR4 0 LTM42 LTM41 LTM40 0 0 0 WCF4 BCW41 BCW40 SSO41 SSO40 RAW41 RAW40 SAW41 SAW40 FFFFF4B0H 30C0H SCR6 0 LTM62 LTM61 LTM60 0 0 0 WCF6 BCW61 BCW60 SSO61 SSO60 RAW61 RAW60 SAW61 SAW60 FFFFF4B8H 30C0H Bit position 14 to 12 Bit name LTMn2 to LTMn0 Sets the CAS latency value for reading. LTMn2 0 0 0 LTMn1 0 1 1 Other than above LTMn0 1 0 1 Function Latency 1 (setting prohibited during DMA flyby transfer) 2 3 Setting prohibited 8 WCFn Indicates that execution of a register write command on SDRAM has been completed after the SCRn register was set. This bit is set to 1 when a register write command is generated. This bit can only be read. 0: Setting not completed 1. Setting completed Remark n = 1, 3, 4, 6 216 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2/3) Bit position 7, 6 Bit name BCWn1, BCWn0 Function Specifies the number of wait states inserted from the bank active command to a read/write command, or from the precharge command to the bank active command. BCWn1 0 0 1 1 BCWn0 0 1 0 1 Number of wait states inserted Setting prohibited 1 2 3 5, 4 SSOn1, SSOn0 Specifies the address shift width during on-page judgment. If the external data bus width is set to 16 or 32 bits, the system does not use the lower address (A0 or A1, A0). Set these bits in accordance with the contents of the LBS register corresponding to CSn. SSOn1 0 0 1 1 SSOn0 0 1 0 1 Address shift width 0 bits (external data bus width: 8 bits) 1 bit (external data bus width: 16 bits) Note 2 bits (external data bus width: 32 bits) Setting prohibited Note 3, 2 RAWn1, RAWn0 Specifies the row address width. RAWn1 0 0 1 1 RAWn0 0 1 0 1 11 bits 12 bits 13 bits Note Row address width Note Setting prohibited 1, 0 SAWn1, SAWn0 Specifies the address multiplex width (column address width) during SDRAM access. SAWn1 0 0 1 1 SAWn0 0 1 0 1 8 bits 9 bits 10 bits 11 bits Note Address multiplex width (column address width) Note Remarks 1. The Note is described on the next page. 2. n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 217 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3/3) Note The following setting is prohibited because the upper limit of the address is exceeded. SSOn1 0 SSOn0 1 RAWn1 1 RAWn0 0 SAWn1 1 SAWn0 1 Data bus width: Setting 16 bits Row address width: 13 bits Column address width: 11 bits 1 0 0 1 1 1 Data bus width: 32 bits Row address width: 12 bits Column address width: 11 bits 1 0 1 0 1 0 Data bus width: 32 bits Row address width: 13 bits Column address width: 10 bits 1 Data bus width: 32 bits Row address width: 13 bits Column address width: 11 bits Remark n = 1, 3, 4, 6 218 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.5 SDRAM access During power-on or a refresh operation, the all-bank precharge command is always issued for SDRAM. When accessing SDRAM after that, therefore, the active command and read/write command are issued in that order (see <1> in Figure 5-8). If a page change occurs following this, the precharge command, active command, and read/write command are issued in that order (see <2> in Figure 5-8). If a bank change occurs, the active command and read/write command for the bank to be accessed next are issued in that order. Following this read/write command, the precharge command for the bank that was accessed before the bank currently being accessed will be issued (see <3> in Figure 5-8). Figure 5-8. State Transition of SDRAM Access All-bank precharge command (Power on/refresh) Bank A active command <1> Read/Write command (On-page access) Read/Write command (Page change) (Bank change) Bank A precharge command <2> Bank A active command Bank B active command <3> Bank B Read/Write command Bank A precharge command Bank A Read/Write command (Bank change) Bank A active command Bank A Read/Write command User's Manual U16031EJ4V1UD 219 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (1) SDRAM single read cycle The SDRAM single read cycle is a cycle for reading from SDRAM by executing a load instruction (LD) for the SDRAM area, by fetching an instruction, or by 2-cycle DMA transfer. In the SDRAM single read cycle, the active command (ACT) and read command (RD) are issued to SDRAM in that order. During on-page access, however, only the read command is issued and the precharge When a page change occurs in the same bank, the command and active command are not issued. precharge command (PRE) is issued before the active command. A one-state T0 cycle is always inserted immediately before all read commands activated by the CPU. The number of idle states (TI) set by the BCC register are inserted after the read cycle (no idle states are inserted, however, if BCn1 and BCn0 are 00) (n = 1, 3, 4, 6). The timing charts of the SDRAM single read cycle are shown below. Caution When executing a write access to SRAM or external I/O after read accessing SDRAM, data conflict may occur depending on the SDRAM data output float delay time. In such a case, avoid data conflict by inserting an idle state in the SDRAM space via a setting in the BCC register. 220 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. SDRAM Single Read Cycle (1/5) (a) During off-page access (when latency = 2, BCW = 1) T0 BUSCLK (output) Command A2 to A11 (output) A12 Note 2 Note 1 TACT TREAD TLATE TLATE T0 Note 1 ACT Row Row Bnk. Address RD Col. Address Address Address (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) D0 to D31 (input) H Data Latency = 1 Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 221 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. SDRAM Single Read Cycle (2/5) (b) During off-page access (latency = 2, idle state 2 insertion) T0 BUSCLK (output) Command A2 to A11 (output) A12 Note 2 Note 1 TACT TREAD TLATE TLATE TI TI T0 Note 1 ACT Row Row Bnk. Address RD Col. Address Address Address (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) D0 to D31 (input) H Data Latency = 2 Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address 222 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. SDRAM Single Read Cycle (3/5) (c) During off-page access (when latency = 2, page change, BCW = 1) T0 BUSCLK (output) Command A2 to A11 (output) A12 Note 2 Note 1 TACT TREAD TLATE TLATE T0 Note 1 TPREC TACT TREAD TLATE TLATE T0 Note 1 ACT Row Row Bnk. Address RD Col. Address Address Address Row PRE Row Row Bnk. Address ACT RD Col. Address Address Address (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) D0 to D31 (input) H Data Latency = 2 Data Latency = 2 Page change Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 223 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. SDRAM Single Read Cycle (4/5) (d) During off-page access (latency = 2, bank change) T0 BUSCLK (output) Command A2 to A11 (output) A12 Note 2 Note 1 TACT TREAD TLATE TLATE T0 Note 1 TACT TREAD TLATE TLATE T0 Note 1 ACT Row Row Bnk.A Address RD Col. Address Address Address ACT(Bnk.B) Row Row Bnk.B Address Col. Address Address Address RD PRE(Bnk.A) Row Address Address Bnk.A Address (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) D0 to D31 (input) H Address Data Latency = 2 Bank change Data Latency = 2 Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address 224 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. SDRAM Single Read Cycle (5/5) (e) During on-page access (when latency = 2, 32-bit bus width) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12 Note 2 TREAD TLATE TLATE T0Note 1 RD Col. Address Address Address Col. Address Address Address (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) H H Note 4 (output) D0 to D31 (input) Data Latency = 2 Notes 1. 2. 3. 4. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address User's Manual U16031EJ4V1UD 225 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2) SDRAM single write cycle The SDRAM single write cycle is a cycle for writing to SDRAM by executing a write instruction (ST) for the SDRAM area or by 2-cycle DMA transfer. In the SDRAM single write cycle, the active command (ACT) and write command (WR) are issued to SDRAM in that order. During on-page access, however, only the write command is issued and the precharge When a page change occurs in the same bank, the command and active command are not issued. precharge command (PRE) is issued before the active command. The timing charts of the SDRAM single write cycle are shown below. 226 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. SDRAM Single Write Cycle (1/6) (a) During off-page access T0 BUSCLK (output) Command A2 to A11 (output) A12 Note 2 Note 1 TACT TWR ACT(Bnk.A) Row Row Bnk.A Address Col. WR (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) D0 to D31 (I/O) Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 227 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. SDRAM Single Write Cycle (2/6) (b) Page change (1/2) Write to address (A) Access by CPU Write to address (B) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12Note 2 (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) TACT TWR TW TPREC TACT TWR ACT(Bnk.A) Row Row Bnk.A Address Col.(A) WR Address PRE(Bnk.A) ACT(Bnk.A) Row Row Bnk.A Address Col.(B) Address Address Address WR Address Address Address D0 to D31 (I/O) Data Data Page change Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address 228 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. SDRAM Single Write Cycle (3/6) (b) Page change (2/2) Access by CPU Write to address (A) Write to address (B) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12Note 2 (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) TACT TWR T0Note 1 TPREC TACT TWR ACT(Bnk.A) Row Row Bnk.A Address Col.(A) Address Address Address WR PRE(Bnk.A) ACT(Bnk.A) Row Row Bnk.A Address Col.(B) Address Address Address WR D0 to D31 (I/O) Data Data Page change Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 229 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. SDRAM Single Write Cycle (4/6) (c) Bank change (1/2) Write to address (A) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12Note 2 (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) ACT(Bnk.A) Row Row Bnk.A Address Col.(A) WR Address ACT(Bnk.B) Row Row Bnk.B Address Col.(B) Address Address Address Bnk.A Address WR PRE(Bnk.A) Row Address Address Address Address TACT Write to address (B) TWR TW TACT TWR WPRE WEND Access by CPU Address Address Address D0 to D31 (I/O) Data Bank change Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address 230 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. SDRAM Single Write Cycle (5/6) (c) Bank change (2/2) Write to address (B) TWR T0Note 1 TACT TWR WPRE WEND Access by CPU Write to address (A) T0Note 1 TACT BUSCLK (output) Command A2 to A11 (output) A12Note 2 (output) Command Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) ACT(Bnk.A) Row Row Bnk.A Address Col.(A) Address Address Address WR Address ACT(Bnk.B) Row Row Bnk.B Address Col.(B) Address Address Address Bnk.A Address WR PRE(Bnk.A) Row Address Address Address Address D0 to D31 (I/O) Data Bank change Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 231 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. SDRAM Single Write Cycle (6/6) (d) During on-page access (32-bit bus width) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12 (output) Bank address (output) Note 2 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) D0 to D31 (I/O) Data H Col. (A) Address Address Address WR TWR Notes 1. 2. 3. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address 232 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3) SDRAM access timing control The SDRAM access timing can be controlled by the SCRn register (n = 1, 3, 4, 6). For details, see 5.3.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6). Caution Wait control by the WAIT pin is not available during SDRAM access. (a) Number of waits from bank active command to read/write command The number of wait states from bank active command issue to read/write command issue can be set by setting the BCWn1 and BCWn0 bits of the SCRn register. BCWn1, BCWn0 bits = 01: 1 wait BCWn1, BCWn0 bits = 10: 2 waits BCWn1, BCWn0 bits = 11: 3 waits (b) Number of waits from precharge command to bank active command The number of wait states from precharge command issue to bank active command issue can be set by setting the BCWn1 and BCWn0 bits of the SCRn register. BCWn1, BCWn0 bits = 01: 1 wait BCWn1, BCWn0 bits = 10: 2 waits BCWn1, BCWn0 bits = 11: 3 waits (c) CAS latency setting when read The CAS latency during a read operation can be set by setting the LTMn2 to LTMn0 bits of the SCRn register. LTMn2 to LTMn0 bits = 001: Latency = 1 (setting prohibited during DMA flyby transfer) LTMn2 to LTMn0 bits = 010: Latency = 2 LTMn2 to LTMn0 bits = 011: Latency = 3 (d) Number of waits from refresh command to next command The number of wait states from refresh command issue to next command issue can be set by setting the BCWn1 and BCWn0 bits of the SCRn register. The number of wait states becomes four times the value set by BCWn1 and BCWn0 bits. BCWn1, BCWn0 bits = 01: 4 waits BCWn1, BCWn0 bits = 10: 8 waits BCWn1, BCWn0 bits = 11: 12 waits User's Manual U16031EJ4V1UD 233 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (1/9) (a) When read (with speculative read, 32-bit bus width, BCW = 2, latency = 2) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12 (output) Bank address (output) Note 2 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) Note 4 (output) D0 to D31 (input) Latency = 2 Latency = 2 Latency = 2 Latency = 2 Row Row Bnk Address ACT Col.(A) Address Address Address RD Col.(A+4) RD Col.(A+8) Address Address Address RD Col.(A+C) RD Undefined Undefined Undefined Undefined TACT TBCW TREAD TREAD TREAD TREAD TLATE TLATE H Data Data Data Data Notes 1. 2. 3. 4. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address 234 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (2/9) (b) When read (with speculative read, access on another line, 32-bit bus width, BCW = 2, latency = 2) Access by CPU T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12 (output) Bank address (output) Note 2 (outputs) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) Note 4 (output) D0 to D31 (input) Latency = 2 Latency = 2 Latency = 2 Latency = 2 Speculative read cycle (fill cycle of speculative read buffer) Speculative read cycle Row Row Bnk. Address ACT Col.(A) Address Address Address RD Col.(A+4) RD Col.(A+8) Address Address Address RD RD Col.(A+C) Undefined Undefined Undefined Undefined Col.(B) Address Address Address RD TACT Read from address (A) TBCW TREAD TREAD TREAD TREAD TLATE Read from address (B) TLATE TW TREAD H Data Data Data Data Penalty cycle accompanying request to access another line Notes 1. 2. 3. 4. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 235 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (3/9) (c) When read (16-bit bus width, cache fill operation, latency = 3) T0Note 1 BUSCLK (output) Command A1 to A10 (output) A11 (output) Bank address (output) Note 2 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) D0 to D15 (I/O) Latency = 3 Latency = 3 Latency = 3 Latency = 3 Data Data Data Data Latency = 3 Latency = 3 Latency = 3 Latency = 3 Data Data Data Data H H Col. (A) Address Address Address RD RD Col. (A+2) Address Address Address RD Col. (A+4) Address Address Address RD Col. (A+6) Address Address Address RD Col. (A+8) Address Address Address RD Col. (A+A) Address Address Address RD Col. (A+C) Address Address Address RD Col. (A+E) Address Address Address Undefined Undefined Undefined Undefined TREAD TREAD TREAD TREAD TREAD TREAD TREAD TREAD TLATE TLATE TLATE T0Note 1 Notes 1. 2. 3. State (T0) inserted between bus cycles Addresses other than the bank address, A11, and A1 to A10. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address 236 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (4/9) (d) For read write operation (with speculative read, latency = 2, 32-bit bus width) (1/2) Access by CPU Read from address (A) Note 4 Note 5 Write to address (A) Write cycle TLATE TW TWR Speculative read cycle (fill cycle of speculative read buffer) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12 (output) Bank address (output) Note 2 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) H TREAD TREAD TREAD TREAD TLATE RD Col. (A) RD Col. (A+4) RD Col. (A+8) Address Address Address RD Col. (A+C) Col. (A) Address Address Address WR D0 to D31 (I/O) Data Latency = 2 Data Data Data Data Penalty cycle accompanying with another line access request Latency = 2 Latency = 2 Latency = 2 Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Read from address (A+4) Read from address (A+8) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address User's Manual U16031EJ4V1UD 237 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (5/9) (d) For read write operation (with speculative read, latency = 2, 32-bit bus width) (2/2) Access by CPU Read from address (A) Note 4 Note 5 Note 6 Write to (A) Write cycle TLATE T0Note 1 TWR Speculative read cycle (fill cycle of speculative read buffer) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12 (output) Bank address (output) Note 2 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) D0 to D31 (I/O) Data Latency = 2 Latency = 2 Latency = 2 Latency = 2 Data Data Data H Col. (A) RD RD Col. (A+4) RD Col. (A+8) Address Address Address RD Col. (A+C) TREAD TREAD TREAD TREAD TLATE WR Col. (A) Address Address Address Data Notes 1. 2. 3. 4. 5. 6. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Read from address (A+4) Read from address (A+8) Read from address (A+C) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address 238 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (6/9) (e) When read (without speculative read, 16-bit bus width word access, page change, BCW = 2, latency = 2) T0Note 1 BUSCLK (output) Command A1 to A10 (output) A11 (output) Bank address (output) Note 2 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) Note 4 (output) D0 to D15 (input) Data Latency = 2 BCW Latency = 2 Page change BCW BCW Data Data Latency = 2 Latency = 2 Data ACT(Bnk.A) Row Row Bnk.A Address Col. Address Address Address RD Col. Address Address Address RD Undefined Undefined Undefined Undefined PRE(Bnk.A) Row Row Bnk.A Address Address Address ACT(Bnk.A) Row Row Bnk.A Col. Address Address Address RD Col. Address Address Address RD Undefined Undefined Undefined Undefined TACT TBCW TREAD TREAD TLATE TLATE T0Note 1 TPREC TBCW TACT TBCW TREAD TREAD TLATE TLATE T0Note 1 Address Address Address Notes 1. 2. 3. 4. State (T0) inserted between bus cycles Addresses other than the bank address, A11, and A1 to A10 When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) The broken lines indicate the high-impedance state. m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address Remarks 1. 2. n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 239 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (7/9) (f) When read (without speculative read, 16-bit bus width word access, bank change, BCW = 2, latency = 2) T0Note 1 BUSCLK (output) Command A1 to A10 (output) A11 (output) Bank address (output) Note 2 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) Note 4 (output) D0 to D15 (input) ACT(Bnk.A) Row Row Bnk.A Address Col. Address Address Address RD Col. Address Address Address RD Undefined Undefined Undefined Undefined ACT(Bnk.B) Row Row Bnk.B Address Col. Address Address Address RD Col. Address Address Address Bnk.A RD PRE(Bnk.A) TACT TBCW TREAD TREAD TLATE TLATE T0Note 1 TACT TBCW TREAD TREAD TLATE TLATE T0Note 1 Undefined Undefined Undefined Undefined Undefined Undefined Data Latency = 2 BCW Data Data Latency = 2 BCW Bank change Data Latency = 2 Latency = 2 Notes 1. 2. 3. 4. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address 240 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (8/9) (g) For write read operation Access by CPU T0 BUSCLK (output) Command A2 to A11 (output) A12 Note 2 Note 1 Write to (A) TACT TBCW Write to (B) TWR TW TPREC TBCW TACT TBCW TWR Read from (C) TW TACT TBCW TREAD TLATE TLATE ACT(Bnk.A) Row Row Bnk.A Address Col.(A) Address Address Address WR Address Address Address Address PRE(Bnk.A) Row Address Address Bnk.A Address Address Address ACT(Bnk.A) Row Row Bnk.A Address Col.(B) Address Address Address WR Address Address Address Address ACT(Bnk.B) Row Row Bnk.B Address Col.(C) Address Address Address RD PRE(Bnk.A) Row Address Address Bnk.A Address (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) Note 5 (output) D0 to D31 (I/O) Address Address Data BCW Page change Data BCW BCW Bank change BCW Data Latency = 2 Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles Addresses other than the bank address, A12, and A2 to A11. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. When xxWR output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTm bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 3 xx = UU, UL, LU, LL 3. Bnk.: Bank address Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 241 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-11. SDRAM Access Timing (9/9) (h) When written (during on-page continuous access) T0Note 1 BUSCLK (output) Command A2 to A11 (output) A12Note 2 (output) Bank address (output) Note 3 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) D0 to D31 (I/O) Data Data Data Data H Col. Address Address Address WR Address Address Address Address Col. Address Address Address WR Address Address Address Address Col. Address Address Address WR Address Address Address Address Col. Address Address Address WR TWR T0Note 1 TWR T0Note 1 TWR T0Note 1 TWR Notes 1. 2. 3. 4. State (T0) inserted between bus cycles This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address 242 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.6 Refresh control function The V850E/ME2 can generate a refresh cycle. The refresh cycle is set with the RFSn register (n = 1, 3, 4, 6). The RFSn register corresponds to CSn. For example, to connect SDRAM to CS1, set the RFS1 register. When another bus master occupies the external bus, the DRAM controller cannot occupy the external bus. In this case, the DRAM controller issues a refresh request to the bus master by changing the REFRQ signal to active (low level). During a refresh operation, the address bus retains the state it was in just before the refresh cycle. (1) SDRAM refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6) These registers are used to enable or disable a refresh and set the refresh interval. The refresh interval is determined by the following calculation formula. Refresh interval (s) = Refresh count clock (TRCY) x Interval factor The refresh count clock and interval factor are determined by the RCCn1 and RCCn0 bits and RIN5n to RIN0n bits, respectively. Note that n corresponds to the register number (1, 3, 4, 6) of the SCR1, SCR3, SCR4, and SCR6 registers. These registers can be read or written in 16-bit units. Cautions 1. Write to the RFS1, RFS3, RFS4, and RFS6 registers after reset, and then do not change the set values. However, when the SDRAM refresh interval needs to be changed by changing the CKC register set value (internal system clock (fCLK)), the set value of the RFS1, RFS3, RFS4, and RFS6 registers can be changed. For details, refer to Caution 2 in 8.3.1 Clock control register (CKC). Also, do not access an external memory area other than the one for this initialization routine until the initial settings of the RFS1, RFS3, RFS4, and RFS6 registers are complete. However, it is possible to access external memory areas whose initialization settings are complete. 2. To change the refresh interval, consider and set a value at which refreshing can be performed in time even while the refresh interval is changed. For details, see 8.3.1 (1) Notes on changing refresh interval. User's Manual U16031EJ4V1UD 243 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 15 RFS1 REN1 14 0 13 0 12 0 11 0 10 9 8 7 0 6 5 4 3 2 1 0 Address FFFFF4A6H After reset 0000H 0 RCC11 RCC10 0 RIN15 RIN14 RIN13 RIN12 RIN11 RIN10 RFS3 REN3 0 0 0 0 0 RCC31 RCC30 0 0 RIN35 RIN34 RIN33 RIN32 RIN31 RIN30 FFFFF4AEH 0000H RFS4 REN4 0 0 0 0 0 RCC41 RCC40 0 0 RIN45 RIN44 RIN43 RIN42 RIN41 RIN40 FFFFF4B2H 0000H RFS6 REN6 0 0 0 0 0 RCC61 RCC60 0 0 RIN65 RIN64 RIN63 RIN62 RIN61 RIN60 FFFFF4BAH 0000H Bit position 15 Bit name RENn Function Specifies whether CBR (auto) refresh is enabled or disabled. 0: Refresh disabled 1: Refresh enabled 9, 8 RCCn1, RCCn0 Specifies the refresh count clock (TRCY). RCCn1 0 0 1 1 RCCn0 0 1 0 1 32/BUSCLK 128/BUSCLK 256/BUSCLK Setting prohibited Refresh count clock (TRCY) 5 to 0 RINn5 to RINn0 Sets the interval factor of the interval timer for the generation of the refresh timing. RINn5 0 0 0 0 : 1 RINn4 0 0 0 0 : 1 RINn3 0 0 0 0 : 1 RINn2 0 0 0 0 : 1 RINn1 0 0 1 1 : 1 RINn0 0 1 0 1 : 1 1 2 3 4 : 64 Interval factor Remark n = 1, 3, 4, 6 244 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Table 5-1. Example of Interval Factor Settings Specified Refresh Interval Value (s) 15.6 32/BUSCLK 128/BUSCLK 256/BUSCLK Refresh Count Clock (TRCY) Interval Factor Value BUSCLK = 66 MHz 32 (15.5) 8 (15.5) 4 (15.5) Notes 1, 2 BUSCLK = 50 MHz 24 (15.4) 6 (15.4) 3 (15.4) Notes 1. 2. The interval factor is set by the RINn0 to RINn5 bits (n = 1, 3, 4, 6). The values in parentheses are the calculated values for the refresh interval (s). Refresh interval (s) = Refresh count clock (TRCY) x Interval factor The V850E/ME2 can automatically generate a CBR (auto) refresh cycle and a self-refresh cycle. User's Manual U16031EJ4V1UD 245 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2) CBR (auto) refresh cycle In the CBR (auto) refresh cycle, the CBR (auto) refresh command (REF) is issued four clocks after the precharge command for all banks (PALL) is issued. Figure 5-12. CBR (Auto) Refresh Cycle CBR (auto) refresh cycle TABPW TREFW TREFW TREFW BUSCLK (output) Command A2 to A11 (output) Note 1 TREF PALL Address REF A12 (output) Address Bank address (output) Note 2 (output) Address BCYST (output) H CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) SDCKE (output) D0 to D31 (I/O) H H Notes 1. 2. 3 This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 246 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3) CBR (auto) refresh timing Figure 5-13. CBR (Auto) Refresh Timing (SDRAM) TRPW BUSCLK (output) TRPW TRPW TRPW TRPW TABPW TREFW TREFW TREFW TREF TREFW TREFW TREFW TREFW TRPW TRPW T0 Note 1 T1 A2 to A11 (output) A12Note 2 (output) Bank address (output) Note 3 (output) BCYST (output) H CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 4 (output) H H BCW x 4clk SDCKE (output) Refresh counter match timing All-bank precharge command Refresh command Notes 1. 2. 3. 4. State (T0) inserted between bus cycles This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The number of wait states set by the BCWn1 and BCWn0 bits of the SCRn register x 4 clocks will be inserted in the BCW x 4clk period. 2. n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 247 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.7 Self-refresh control function In the case of transition to the IDLE or software STOP mode, or if the SELFREF signal becomes active, the DRAM controller generates the self-refresh cycle. Cautions 1. When the transition to the self-refresh cycle is caused by SELFREF signal input, releasing the self-refresh cycle is only possible by inputting an inactive level to the SELFREF pin. 2. The internal instruction RAM (only in the read mode) and internal data RAM can be accessed even in the self-refresh cycle. However, access to an on-chip peripheral I/O register or external device is held pending until the self-refresh cycle is cleared. To release the self-refresh cycle, use one of the three methods below. (1) Release by NMI input (a) In the case of self-refresh cycle in IDLE mode To release the self-refresh cycle, make the SDRAS and SDCAS signals inactive immediately. (b) In the case of self-refresh cycle in software STOP mode To release the self-refresh cycle, make the SDRAS and SDCAS signals inactive after stabilizing oscillation. (2) Release by INTP0n0 and INTP0n1 inputs (n = 0 to 3) (a) In the case of self-refresh cycle in IDLE mode To release the self-refresh cycle, make the SDRAS and SDCAS signals inactive immediately. (b) In the case of self-refresh cycle in software STOP mode To release the self-refresh cycle, make the SDRAS and SDCAS signals inactive after stabilizing oscillation. (3) Release by RESET input 248 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-14. Self-Refresh Timing (SDRAM) TRPW TRPW TRPW TRPW TRPW TABPW TREFW TREFW TREFW TREF TREFW TREFW TREFW Note 1 TREFW TREFW TREFW TRPW TRPW TRPW TRPW TRPW T0Note 2 BUSCLK (output) A2 to A11 (output) Note 3 A12 (output) Bank address (output) Note 4 (output) BCYST (output) H CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 5 (output) H SDCKE (output) Refresh NOP command command Self-refresh mode NOP command BCW x 4clk All-bank precharge command Notes 1. Shown above is the case when the self-refresh cycle is started in the IDLE or software STOP mode. If the self-refresh cycle is started by inputting the active level of the SELFREF signal, BUSCLK does not stop (SDCKE goes low). 2. 3. 4. 5. State (T0) inserted between bus cycles This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The number of wait states set by the BCWn1 and BCWn0 bits of the SCRn register x 4 clocks will be inserted in the BCW x 4clk period. 2. n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 249 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.8 SDRAM initialization sequence Be sure to initialize SDRAM when applying power. Initialize SDRAM in the following procedure. (1) Set the registers of SDRAM (other than SDRAM configuration register n (SCRn) and SDRAM refresh control register n (RFSn)). * Bus cycle type configuration registers 0 and 1 (BCT0 and BCT1) * Bus cycle control register (BCC) (2) Set other than the RENn bit of SDRAM refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6). Clear the RENn bit to 0. (3) Set SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6). When writing data to the SCRn register, the following commands are issued for SDRAM in the order shown below. * All-bank precharge command * Refresh command (8 times) * Command that is used to set a mode register (4) After confirming that all the SDRAM initialization steps have been completed using the WCFn bit of the SCRn register, set the RENn bit of the RFSn register to 1. Set the value set in step (2) to other bits than the RENn bit. Cautions 1. To set the SCR1, SCR3, SCR4, and SCR6 registers, confirm that the LOCK bit of the LOCKR register is set to 1, set the CKSSEL bit of the CKS register to 1, and change clock supply to the CPU to SSCG output (see 3.4.10 Initialization sequence). 2. If it is necessary to make the input levels of the UUDQM, ULDQM, LUDQM, and LLDQM pins high until initialization of SDRAM is completed, do not change the set values of the PFCCT3 to PFCCT0 bits of the PFCCT register and do not write the external device until initialization of SDRAM is completed. Figures 5-15 and 5-16 show examples of the SDRAM mode register setting timing. 250 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-15. SDRAM Mode Register Setting Cycle Mode register setting cycle TABPW TREFW TREFW TREFW TREF BUSCLK (output) Command A2 to A11 (output) A12 Note 1 TREFW TREGW PALL REF REGWR Valid (output) Bank address (output) Note 2 (output) BCYST (output) H CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) H SDCKE (output) H D0 to D31 (I/O) Refresh command (REF) generated 8 times Notes 1. 2. 3. This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 251 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-16. SDRAM Register Write Operation Timing TW0 TW0 TW0 TW0 TW0 TW0 TW0 TW0 TABPWTREFWTREFWTREFW TREF TREFWTREFWTREFW TREFW TREF TREFW TREFWTREFWTREGWTRPW TRPW TRPW TRPW TRPW BUSCLK (output) A2 to A11 (output) Valid A12 Note 1 (output) Bank address (output) Note 2 (output) BCYST (output) H CSn (output) SDRAS (output) SDCAS (output) WE (output) Note 3 (output) SDCKE (output) H SCRn register write All-bank precharge command Refresh interval x 1/2 Refresh command (1st time) Refresh x 7 Refresh command (2nd time) Refresh end (8th time) Register write command SDRAM access enable Refresh end (1st time) Notes 1. 2. 3. Remark This is the signal when the 32-bit external bus is used. Read it as A11 when the 16-bit bus is used, and A10 when the 8-bit bus is used. Addresses other than the bank address, A12, and A2 to A11. UUDQM, ULDQM, LUDQM, LLDQM n = 1, 3, 4, 6 252 User's Manual U16031EJ4V1UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.4 Cautions Cautions concerning the memory access control function are shown below. (1) Write access to SRAM or external I/O after read accessing SDRAM When executing a write access to SRAM or external I/O after read accessing SDRAM, data conflict may occur depending on the SDRAM data output float delay time. In such a case, avoid data conflict by inserting an idle state in the SDRAM space via a setting in the BCC register. (2) Caution on self-refresh control function The internal instruction RAM (only in the read mode) and internal data RAM can be accessed even in the self-refresh cycle. However, access to an on-chip peripheral I/O register or external device is held pending until the self-refresh cycle is cleared. User's Manual U16031EJ4V1UD 253 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/ME2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, or among memories, based on requests by interrupts from on-chip peripheral I/O (serial interface, timer/counter, and A/D converter) or DMA requests issued by the DMARQ0 to DMARQ3 pins, software triggers, or USB. Memory refers to the internal instruction RAM, internal data RAM, or external memory. However, the internal instruction RAM can be used only as the transfer destination. 6.1 Features * 4 independent DMA channels * Transfer unit: 8/16/32 bits * Maximum transfer count: 65,536 (216) * Two types of transfer * Flyby (1-cycle) transfer * 2-cycle transfer * Three transfer modes * Single transfer mode * Single-step transfer mode * Block transfer mode * Transfer requests * Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) * Requests via DMARQ0 to DMARQ3 pin input * Requests by software trigger * Requests by USB (only in the single transfer mode) * Transfer targets * Memory I/O * Memory memory * DMA transfer end output signals (TC0 to TC3) * Next address setting function 254 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.2 Configuration Internal data RAM Internal instruction RAM On-chip peripheral IO Internal bus On-chip peripheral I/O bus CPU Data control Address control DMA source address register (DSAnH/DSAnL) DMA destination address register (DDAnH/DDAnL) TCn Count control DMA transfer count register (DBCn) DMA terminal count output control register (DTOC) DMA channel control register (DCHCn) DMARQn DMAAKn Channel control DMA addressing control register (DADCn) DMA trigger factor register (DTFRn) DMA interface control register (DIFC) DMAC Bus interface External bus V850E/ME2 External I/O External RAM External ROM Remark n = 0 to 3 User's Manual U16031EJ4V1UD 255 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA transfer source address (28 bits) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL. Since these registers are buffer registers with a 2-stage FIFO format that is configured by master register and slave register, a new transfer source address for DMA transfer can be specified during DMA transfer (see 6.8 Next Address Setting Function). In this case, the newly set value of the DSAn register is transferred to the slave register and becomes valid only when DMA transfer has been completed normally and the TCn bit of the DCHCn register is set to 1, or when the INITn bit of the DCHCn register is set to 1 (n = 0 to 3). However, the set value of the DSAn register is invalid even when the Enn bit of the DCHCn register is cleared to 0 to disable DMA transfer and then the DSAn register is set. When flyby transfer is specified with the TTYPn bit of DMA addressing control register n (DADCn), the external memory addresses are set by the DSAn register, regardless of the transfer direction. At this time, the setting of DMA destination address register n (DDAn) is ignored (n = 0 to 3). (1) DMA source address registers 0H to 3H (DSA0H to DSA3H) These registers can be read or written in 16-bit units. Be sure to clear bits 14 to 12 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. When setting an address of an on-chip peripheral I/O register for the source address, be sure to specify an address between FFFF000H and FFFFFFFH. An address of the onchip peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified. 2. Do not set the DSAnH register while DMA transfer is suspended. 15 DSA0H IRS0 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF082H After reset Undefined 0 SA027 SA026 SA025 SA024 SA023 SA022 SA021 SA020 SA019 SA018 SA017 SA016 DSA1H IRS1 0 0 0 SA127 SA126 SA125 SA124 SA123 SA122 SA121 SA120 SA119 SA118 SA117 SA116 FFFFF08AH Undefined DSA2H IRS2 0 0 0 SA227 SA226 SA225 SA224 SA223 SA222 SA221 SA220 SA219 SA218 SA217 SA216 FFFFF092H Undefined DSA3H IRS3 0 0 0 SA327 SA326 SA325 SA324 SA323 SA322 SA321 SA320 SA319 SA318 SA317 SA316 FFFFF09AH Undefined Bit position 15 Bit name IRSn Function Specifies the DMA transfer source address. 0: External memory, on-chip peripheral I/O 1: Internal data RAM 11 to 0 SAn27 to SAn16 Sets the DMA transfer source address (A27 to A16). During DMA transfer, it stores the next DMA transfer source address. During flyby transfer, it stores an external memory address. Remark n = 0 to 3 256 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read or written in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF080H After reset Undefined DSA0L SA015 SA014 SA013 SA012 SA011 SA010 SA09 SA08 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 DSA1L SA115 SA114 SA113 SA112 SA111 SA110 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 FFFFF088H Undefined DSA2L SA215 SA214 SA213 SA212 SA211 SA210 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 FFFFF090H Undefined DSA3L SA315 SA314 SA313 SA312 SA311 SA310 SA39 SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 FFFFF098H Undefined Bit position 15 to 0 Bit name SAn15 to SAn0 Function Sets the DMA transfer source address (A15 to A0). During DMA transfer, it stores the next DMA transfer source address. During flyby transfer, it stores an external memory address. Remark n = 0 to 3 User's Manual U16031EJ4V1UD 257 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA transfer destination address (28 bits) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL. Since these registers are buffer registers with a 2-stage FIFO format that is configured by master register and slave register, a new transfer destination address for DMA transfer can be specified during DMA transfer (see 6.8 Next Address Setting Function). In this case, the newly set value of the DDAn register is transferred to the slave register and becomes valid only when DMA transfer has been completed normally and the TCn bit of the DCHCn register is set to 1, or when the INITn bit of the DCHCn register is set to 1 (n = 0 to 3). However, the set value of the DDAn register is invalid even when the Enn bit of the DCHCn register is cleared to 0 to disable DMA transfer and then the DDAn register is set. When flyby transfer is specified with the TTYPn bit of DMA addressing control register n (DADCn), the setting of DMA destination address register n (DDAn) is ignored, regardless of the transfer direction. (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) These registers can be read or written in 16-bit units. Be sure to clear bits 14 to 12 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. When setting an address of an on-chip peripheral I/O register for the destination address, be sure to specify an address between FFFF000H and FFFFFFFH. An address of the on-chip peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified. 2. Do not set the DDAnH register while DMA transfer is suspended. 3. When enabling the speculative read function is selected for the CS space at the DMA transfer destination, set the DMA transfer destination address so that the address on which a speculative read is performed and the line address to which the last DMA transfer data is written are not the same line address (the same line address means that A25 to A4 are the same in the same CS space). 15 DDA0H IRD0 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF086H After reset Undefined DA027 DA026 DA025 DA024 DA023 DA022 DA021 DA020 DA019 DA018 DA017 DA016 DDA1H IRD1 0 0 0 DA127 DA126 DA125 DA124 DA123 DA122 DA121 DA120 DA119 DA118 DA117 DA116 FFFFF08EH Undefined DDA2H IRD2 0 0 0 DA227 DA226 DA225 DA224 DA223 DA222 DA221 DA220 DA219 DA218 DA217 DA216 FFFFF096H Undefined DDA3H IRD3 0 0 0 DA327 DA326 DA325 DA324 DA323 DA322 DA321 DA320 DA319 DA318 DA317 DA316 FFFFF09EH Undefined Bit position 15 Bit name IRDn Function Specifies the DMA transfer destination address. 0: External memory, on-chip peripheral I/O, internal instruction RAM 1: Internal data RAM 11 to 0 DAn27 to DAn16 Sets the DMA transfer destination address (A27 to A16). During DMA transfer, it stores the next DMA transfer destination address. This setting is ignored during flyby transfer. Remark n = 0 to 3 258 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read or written in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF084H After reset Undefined DDA0L DA015 DA014 DA013 DA012 DA011 DA010 DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 DDA1L DA115 DA114 DA113 DA112 DA111 DA110 DA19 DA18 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 FFFFF08CH Undefined DDA2L DA215 DA214 DA213 DA212 DA211 DA210 DA29 DA28 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 FFFFF094H Undefined DDA3L DA315 DA314 DA313 DA312 DA311 DA310 DA39 DA38 DA37 DA36 DA35 DA34 DA33 DA32 DA31 DA30 FFFFF09CH Undefined Bit position 15 to 0 Bit name DAn15 to DAn0 Function Sets the DMA transfer destination address (A15 to A0). During DMA transfer, it stores the next DMA transfer destination address. This setting is ignored during flyby transfer. Remark n = 0 to 3 User's Manual U16031EJ4V1UD 259 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer count for DMA channel n (n = 0 to 3). They store the remaining transfer count during DMA transfer. Since these registers are buffer registers with a 2-stage FIFO format that is configured by master register and slave register, a new DMA byte transfer count for DMA transfer can be specified during DMA transfer (see 6.8 Next Address Setting Function). In this case, the newly set value of the DBCn register is transferred to the slave register and becomes valid only when DMA transfer has been completed normally and the TCn bit of the DCHCn register is set to 1, or when the INITn bit of the DCHCn register is set to 1 (n = 0 to 3). However, the set value of the DBCn register is invalid even when the Enn bit of the DCHCn register is cleared to 0 to disable DMA transfer and then the DBCn register is set. These registers are decremented by 1 for each transfer, and transfer ends when a borrow occurs. These registers can be read or written in 16-bit units. Cautions 1. If the DBCn register is read during DMA transfer after a terminal count has occurred without the register being overwritten, the value set immediately before the DMA transfer will be read out (0000H will not be read, even if DMA transfer has ended). 2. Do not set the DBCn register while DMA transfer is suspended. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF0C0H After reset Undefined DBC0 BC015 BC014 BC013 BC012 BC011 BC010 BC09 BC08 BC07 BC06 BC05 BC04 BC03 BC02 BC01 BC00 DBC1 BC115 BC114 BC113 BC112 BC111 BC110 BC19 BC18 BC17 BC16 BC15 BC14 BC13 BC12 BC11 BC10 FFFFF0C2H Undefined DBC2 BC215 BC214 BC213 BC212 BC211 BC210 BC29 BC28 BC27 BC26 BC25 BC24 BC23 BC22 BC21 BC20 FFFFF0C4H Undefined DBC3 BC315 BC314 BC313 BC312 BC311 BC310 BC39 BC38 BC37 BC36 BC35 BC34 BC33 BC32 BC31 BC30 FFFFF0C6H Undefined Bit position 15 to 0 Bit name BCn15 to BCn0 Function Sets the byte transfer count and stores the remaining byte transfer count during DMA transfer. DBCn 0000H 0001H : FFFFH 16 States Byte transfer count 1 or remaining byte transfer count Byte transfer count 2 or remaining byte transfer count : Byte transfer count 65,536 (2 ) or remaining byte transfer count Remark n = 0 to 3 260 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. These registers can be read or written in 16-bit units. Be sure to clear bits 13 to 8 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. The DSn1 and DSn0 bits set how many bits of data are to be transferred. When 8-bit data is set (DSn1 and DSn0 bits = 00), the lower bytes of the data bus (D0 to D7) are not always used. If the transfer data size is set to 16 bits, transfer is always started from an address with the lowest bit of the address aligned to "0". If the data size is set to 32 bits, transfer is started from an address with the lowest 2 bits of the address aligned to "0". In this case, transfer cannot be started from an odd address. 2. Set the DADCn register at the following timing while the target DMA channel is in operation or is not suspended (the operation is not guaranteed if the register is set at any other timing). * Period from system reset to generation of the first DMA transfer request * Period from completion of DMA transfer (after generation of terminal count) to generation of the next DMA transfer request * Period from forced termination of DMA transfer (after the INITn bit of the DCHCn register is set to 1) to generation of the next DMA transfer request 3. Do not set flyby transfer via the TTYPn bit if all the following conditions are satisfied (n = 0 to 3). * BMC register = 00H * FWn2 to FWn0 bits of FWC register = 000 * FIn1 to FIn0 bits of FIC register = 00 * ACn1 and ACn0 bits of the CSn space subject to flyby transfer by the ASC register = 00 (during transfer to/from SRAM) 4. When the flyby transfer is set by setting the TTYPn bit to 1, the address count direction of the external memory is set using the SADn1 and SADn0 bits regardless of the transfer direction (the settings of the DADn1 and DADn0 bits are ignored). User's Manual U16031EJ4V1UD 261 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (1/2) 15 14 13 0 12 0 11 0 10 0 9 0 8 0 7 6 5 4 3 2 1 0 Address FFFFF0D0H After reset 0000H DADC0 DS01 DS00 SAD01 SAD00 DAD01 DAD00 TM01 TM00 TTYP0 TDIR0 DADC1 DS11 DS10 0 0 0 0 0 0 SAD11 SAD10 DAD11 DAD10 TM11 TM10 TTYP1 TDIR1 FFFFF0D2H 0000H DADC2 DS21 DS20 0 0 0 0 0 0 SAD21 SAD20 DAD21 DAD20 TM21 TM20 TTYP2 TDIR2 FFFFF0D4H 0000H DADC3 DS31 DS30 0 0 0 0 0 0 SAD31 SAD30 DAD31 DAD30 TM31 TM30 TTYP3 TDIR3 FFFFF0D6H 0000H Bit position 15, 14 Bit name DSn1, DSn0 Function Sets the transfer data size for DMA transfer. DSn1 0 0 1 1 DSn0 0 1 0 1 8 bits 16 bits 32 bits Setting prohibited Transfer data size 7, 6 SADn1, SADn0 Sets the count direction of the source address for DMA channel n. SADn1 0 0 1 1 SADn0 0 1 0 1 Increment Decrement Fixed Setting prohibited Count direction 5, 4 DADn1, DADn0 Sets the count direction of the destination address for DMA channel n. DADn1 0 0 1 1 DADn0 0 1 0 1 Increment Decrement Fixed Setting prohibited Count direction Remark n = 0 to 3 262 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position 3, 2 Bit name TMn1, TMn0 Function Sets the transfer mode during DMA transfer. TMn1 0 0 1 1 TMn0 0 1 0 1 Single transfer mode Single-step transfer mode Setting prohibited Block transfer mode Transfer mode 1 TTYPn Sets the DMA transfer type. 0: 2-cycle transfer 1: Flyby transfer 0 TDIRn Sets the transfer direction during transfer between I/O and memory. The setting is valid during flyby transfer only and ignored during 2-cycle transfer. 0: Memory I/O (read) 1: I/O memory (write) Remark n = 0 to 3 User's Manual U16031EJ4V1UD 263 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only. If bits 2 and 1 are read, the read value is always 0.) Be sure to clear bits 6 to 4 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. During a 2-cycle transfer that performs a write operation on the external device, the write operation on the external device may not be completed even if the TCn bit of the DCHCn register is set to 1 (DMA transfer completion) by the write buffer function. completion of the write operation on the external device as follows, if necessary. * Monitor the signal of the TCn pin (the TCn pin becomes active in synchronization with a write operation to the external device). * After it has been detected that the TCn bit of the DCHCn register is set to 1, write 00H to the WAS register or write the same value as that set to the LBC0 or LBC1 register. When this write is completed, completion of an access from the write buffer to the external device can be recognized. If the set value of the LBC0 or LBC1 register is rewritten when a dummy write to the LBC0 or LBC1 register is executed, the operation is not guaranteed. 2. Setting the MLEn bit to 1 is valid only when DMA transfer (hardware DMA) is started by DMARQn pin input or an interrupt from the on-chip peripheral I/O. To start DMA transfer by setting the STGn bit to 1 (software DMA), read the TCn bit and confirm that it is set to 1, and then set the STGn bit to 1. 3. Set the MLEn bit at the following timing while the target DMA channel is in operation or is not suspended (the operation is not guaranteed if the register is set at any other timing). * Period from system reset to generation of the first DMA transfer request * Period from completion of DMA transfer (after generation of terminal count) to generation of the next DMA transfer request * Period from forced termination of DMA transfer (after the INITn bit is set to 1) to generation of the next DMA transfer request 4. If DMA transfer is forcibly terminated in the last transfer cycle with the MLEn bit set to 1, the same operation as that performed when transfer is completed is performed (the TCn bit is set to 1). (The Enn bit is cleared to 0 on completion of forced termination, regardless of the value of the MLEn bit.) In this case, the TCn bit must be read (cleared to 0) in addition to setting the Enn bit when the next DMA transfer is requested. 5. Do not set the STGn bit to 1 while DMA is suspended. 6. Each bit is updated upon completion of DMA transfer (at terminal count) with the Enn bit cleared to 0 and the TCn bit set to 1 in that order. While the statuses of the TCn and Enn bits are being polled, therefore, values indicating the status of "transfer not completed and prohibited" (TCn bit = 0 and Enn bit = 0) may be read if the DCHCn register is read while each bit is being updated. Recognize 264 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Cautions 7. The TCn bit does not have to be read (cleared to 0) on completion of DMA transfer (on generation of the terminal count) only if the following two conditions are satisfied. If either of the conditions is not satisfied, be sure to read the TCn bit (cleared to 0) before the next DMA transfer request is generated. * If the MLEn bit is set to 1 upon completion of DMA transfer (at terminal count) * If the source that starts the next DMA transfer is an external pin (DMARQn) If these two conditions are not satisfied, the operation is not guaranteed if the next DMA transfer request is generated with the TCn bit set to 1. User's Manual U16031EJ4V1UD 265 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) <7> 6 0 5 0 4 0 <3> <2> <1> <0> Address FFFFF0E0H After reset 00H DCHC0 TC0 MLE0 INIT0 STG0 E00 DCHC1 TC1 0 0 0 MLE1 INIT1 STG1 E11 FFFFF0E2H 00H DCHC2 TC2 0 0 0 MLE2 INIT2 STG2 E22 FFFFF0E4H 00H DCHC3 TC3 0 0 0 MLE3 INIT3 STG3 E33 FFFFF0E6H 00H Bit position 7 Bit name TCn Function This status bit indicates whether DMA transfer through DMA channel n is complete or not. This bit is read-only. It is set to 1 during the last DMA transfer and cleared to 0 when it is read. 0: DMA transfer is not complete. 1: DMA transfer is complete. Caution To read the TCn bit on completion of a DMA transfer that transfers data to/from the internal data RAM, first read the status in which the TCn bit was set to 1, and then insert two dummy reads of the DCHCn register in a row. 3 MLEn If this bit is set to 1 when DMA transfer is complete (at terminal count output), the Enn bit is not cleared to 0 and the DMA transfer enable state is retained. If the next DMA transfer startup factor is input from the DMARQn pin or is an interrupt from the on-chip peripheral I/O (hardware DMA), the DMA transfer request is acknowledged even if the TCn bit is not read. If the next DMA transfer startup factor is input by setting the STGn bit to 1 (software DMA), the DMA transfer request is acknowledged if the TCn bit is read and cleared to 0. If this bit is cleared to 0 when DMA transfer is complete (at terminal count output), the Enn bit is cleared to 0 and the DMA transfer disable state is entered. At the next DMA transfer request, the Enn bit must be set to 1 and the TCn bit read. 2 INITn If this bit is set to 1 during DMA transfer or after DMA is forcibly suspended by NMI input, DMA transfer is forcibly terminated. 1 STGn If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA transfer is started. 0 Enn Specifies whether DMA transfer through DMA channel n is to be enabled or disabled. This bit is cleared to 0 when DMA transfer ends. It is also cleared to 0 when DMA transfer is forcibly interrupted or forcibly terminated by setting the INITn bit to 1 or by NMI input. 0: DMA transfer disabled 1: DMA transfer enabled Caution If the Enn bit is set to 1, forcibly terminate DMA transfer using the INITn bit after the number of DMA transfers set by the DBCn register is complete or the Enn bit is cleared to 0 (if the Enn bit is cleared to 0 during DMA transfer, do not re-set the Enn bit to 1). Remark n = 0 to 3 266 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA terminal count output control register (DTOC) The DMA terminal count output control register (DTOC) is an 8-bit register that controls the terminal count output from each DMA channel and DMA transfer during NMI input. Terminal count signals from each DMA channel can be brought together and output from the TC0 pin. This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 5 and 4 to 0, and set bit 0 to 1. Otherwise, the operation is not guaranteed. 7 6 5 0 4 0 <3> TCO3 <2> TCO2 <1> TCO1 0 1 Address FFFFF8A0H After reset 01H DTOC DMSTPM DAKEBC Bit position 7 Bit name DMSTPM Function Controls DMA transfer when NMI is input. 0: Forcibly aborts DMA transfer when NMI is input. 1: Does not abort DMA transfer when NMI is input. Cautions 1. When DMSTPM bit = 0, NMI servicing can be executed immediately after completion of the DMA cycle currently under execution. Before executing the aborted DMA transfer, however, be sure to re-initialize it. 2. When DMSTPM bit = 1, NMI servicing is held pending in the block transfer mode until DMA transfer has been completed the preset number of times. In the single transfer mode and single-step transfer mode, NMI servicing is executed after the DMA cycle currently under execution is completed. As necessary, forcibly terminate DMA transfer by setting the INITn bit of the DCHCn register to 1 (n = 0 to 3). 3. Be sure to change the value of the DMSTPM bit when DMA is not used. The operation is not guaranteed if the value of the DMSTPM bit is changed after registers related to DMAC have been set or during DMA transfer. 6 DAKEBC Specifies extension of the active width of the DMAAKn signal while the DAKEn bit of the DIFC register = 1. 0: Active width extended by 4 x fCLK. 1: Active width extended by 6 to 7 x fCLK. Remark For details of the function to extend the active width of the DMAAKn signal, see 6.3.8 DMA interface control register (DIFC) or 6.5.1 (2) DMAAKn signal active width extension function. 3 to 1 TCO3 to TCO1 Indicates the state of the TC0 pin. 0: Channel n terminal count signal not output from TC0 pin. 1: Channel n terminal count signal output from TC0 pin. Remark fCLK: Internal system clock User's Manual U16031EJ4V1UD 267 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The following shows an example of the case when the DTOC register is set to 03H. DMA0 DMA0 CPU DMA1 DMA1 CPU DMA2 DMA2 DMA channel 0 terminal count DMA channel 1 terminal count DMA channel 2 terminal count TC0 (output) TC2 (output) 6.3.7 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip peripheral I/O. The interrupt requests set by these registers serve as DMA transfer startup factors. These registers can be read or written in 8-bit or 1-bit units. However, only bit 7 (DFn) can be read or written in 1bit units. Cautions 1. To change the setting of the DTFRn register, be sure to stop the DMA operation. 2. An interrupt request from an on-chip peripheral I/O input in the standby mode (IDLE or software STOP mode) is held pending as a DMA transfer start factor. The held DMA start factor is executed following return to the normal operation mode. 3. If the factor of starting DMA transfer is changed by using the IFCn6 to IFCn0 bits, be sure to clear the DFn bit to 0 using the instruction immediately after. 4. When a transmission completion interrupt request signal (UBTIT0 or UBTIT1) of UARTB is used as the factor of starting DMA transfer, the factor of starting DMA transfer that is triggered by the interrupt request signal generated when the last transmission was completed is retained. In this case, clear the DFn bit to 0 to clear the DMA transfer request. 268 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (1/3) <7> 6 IFC06 5 IFC05 4 IFC04 3 IFC03 2 IFC02 1 IFC01 0 IFC00 Address FFFFF810H After reset 00H DTFR0 DF0 DTFR1 DF1 IFC16 IFC15 IFC14 IFC13 IFC12 IFC11 IFC10 FFFFF812H 00H DTFR2 DF2 IFC26 IFC25 IFC24 IFC23 IFC22 IFC21 IFC20 FFFFF814H 00H DTFR3 DF3 IFC36 IFC35 IFC34 IFC33 IFC32 IFC31 IFC30 FFFFF816H 00H Bit position 7 Bit name DFn This is a DMA transfer request flag. Only 0 can be written to this flag. 0: DMA transfer not requested 1: DMA transfer requested Function If the interrupt specified as the DMA transfer startup trigger occurs and it is necessary to clear the DMA transfer request while DMA transfer is disabled (including when it is aborted by NMI or forcibly terminated by software), stop the operation of the source causing the interrupt, and then clear the DFn bit to 0 (for example, disable reception in the case of serial reception). If it is clear that the interrupt will not occur until DMA transfer is resumed next, it is not necessary to stop the operation of the source causing the interrupt. 6 to 0 IFCn6 to IFCn0 This code is used to set the interrupt sources serving as DMA transfer startup factors. IFCn6 0 IFCn5 0 IFCn4 0 IFCn3 0 IFCn2 0 IFCn1 0 IFCn0 0 Interrupt source Level detection mode of DMARQn pin input (DMA request from onchip peripheral I/O disabled) 0 0 0 0 0 0 1 Edge detection mode of DMARQn pin input (DMA request from onchip peripheral I/O disabled) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 INTP10 INTP11 INTP21 INTP22 INTP23 INTP24 INTP25 Remark n = 0 to 3 User's Manual U16031EJ4V1UD 269 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/3) Bit position 6 to 0 Bit name IFCn6 to IFCn0 IFCn6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFCn5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 IFCn4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 IFCn3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 IFCn2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 IFCn1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 IFCn0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Interrupt source INTP50 INTP51 INTP52 INTP65 INTP66 INTP67 INTPD0 INTPD1 INTPD2 INTPD3 INTPD4 INTPD5 INTPD6 INTPD7 INTPD8 INTPD9 INTPD10 INTPD11 INTPD12 INTPD13 INTPD14 INTPD15 INTPL0 INTPL1 INTPC00/INTCCC00 INTPC01/INTCCC01 INTPC10/INTCCC10 INTPC11/INTCCC11 INTPC20/INTCCC20 INTPC21/INTCCC21 INTPC30/INTCCC30 INTPC31/INTCCC31 Function Remark n = 0 to 3 270 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (3/3) Bit position 6 to 0 Bit name IFCn6 to IFCn0 IFCn6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 IFCn5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IFCn4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IFCn3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 IFCn2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 IFCn1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 IFCn0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 Interrupt source INTCCC40 INTCCC41 INTCCC50 INTCCC51 INTCMD0 INTCMD1 INTCMD2 INTCMD3 INTCC100 INTCC101 INTCM100 INTCM101 INTCC110 INTCC111 INTCM110 INTCM111 INTCSI30 INTCSI31 UBTIR0 UBTIT0 UBTIR1 UBTIT1 INTAD UFDRQn Setting prohibited Function Other than above Caution When using an external interrupt (when IFCn6 to IFCn0 bits = 0000010B to 0100000B) as a DMA trigger source, be sure to specify an edge (do not use level detection). Remark n = 0 to 3 User's Manual U16031EJ4V1UD 271 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The relationship between the DMARQn signal and the interrupt source that serves as a DMA transfer trigger is as follows (n = 0 to 3). DMARQn Selector Interrupt source Internal DMA request signal IFCn0 to IFCn6 Remark If an interrupt request is specified as the DMA transfer start factor, an interrupt request will be generated if DMA transfer starts. To prevent an interrupt from being generated, mask the interrupt by setting the interrupt request control register. DMA transfer starts even if an interrupt is masked. For the level detection mode (IFCn6 to IFCn0 bits = 0000000) and edge detection mode (IFCn6 to IFCn0 bits = 0000001) of the DMARQn pin input, see Figures 6-8 to 6-10 (n = 0 to 3). 272 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (1) DMA request detection function The V850E/ME2 has a level detection mode and an edge detection mode as functions to sample the DMARQn pin (n = 0 to 3). The level detection mode also has a mask mode in which sampling the DMA request is masked. (a) Level detection mode (IFCn6 to IFCn0 bits = 0000000) In this mode, handshaking of the DMARQn and DMAAKn signals can be executed at high speeds. In the single transfer mode, deassert the DMARQn signal for the duration of 2 x fCLK from the rising edge of the DMAAKn signal, in order not to start the DMA transfer cycle next to that currently under execution. If the DMARQn signal is active for the duration of 2 x fCLK, the next DMA request is recognized. In the 2-cycle transfer mode, however, the active period of the DMAAKn signal may be shortened depending on the combination of the transfer source and transfer destination (Min.: 2 x fCLK). Consequently, if the inactive timing of the DMARQn signal is generated from the falling edge of the DMAAKn signal, for example, the timing may be 4 x fCLK at the shortest. For the active width of the DMAAKn signal for 2-cycle transfer, see Table 6-4 Minimum Value of Active Width of DMAAKn Signal for 2-Cycle Transfer. Remark fCLK: Internal system clock <1> Mask mode (IFCn6 to IFCn0 bits = 0000000 and DRMKn bit of DIFC register = 1) This mode is used to establish handshaking of the DMARQn and DMAAKn signals in synchronization with BUSCLK in the level detection mode. In the single transfer mode, deassert the DMARQn signal within 3 x BUSCLK after sampling the rising edge of the DMAAKn signal, in order not to start the DMA transfer cycle next to that currently under execution. When the mask mode is set, sampling the DMA request is always masked for the duration of 3 x BUSCLK period from the rising edge of the DMARQn signal, regardless of the division ratio of BUSCLK (set by the BMC register). (b) Edge detection mode (IFCn6 to IFCn0 bits = 0000001) This mode uses the falling edge of the DMARQn signal as a DMA request. It realizes handshaking of the DMARQn and DMAAKn signals at a speed much lower than that when the mask mode is used. However, note that the falling edge of the DMARQn signal is ignored, even if input, while the DMAAKn signal is active. For the detailed timing in each mode, see CHAPTER 17 ELECTRICAL SPECIFICATIONS. User's Manual U16031EJ4V1UD 273 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.8 DMA interface control register (DIFC) This 8-bit register controls the active width of the DMAAKn signal of each DMA channel and controls the mask function (DMA mask mode) of the DMARQn signal (n = 0 to 3). This register can be read or written in 8-bit or 1-bit units. 7 DIFC DAKE3 6 DAKE2 5 DAKE1 4 DAKE0 3 DRMK3 2 DRMK2 1 DRMK1 0 DRMK0 Address FFFFF8A8H After reset 00H Bit position 7 to 4 Bit name DAKEn Function These bits specify the active width of the DMAAKn signal. 0: Active width of DMAAKn signal output from DMAC 1: Active width of DMAAKn signal + active extension width Note output from DMAC Note The active width is extended by the DAKEn bit as follows. * 4 x fCLK when DAKEBC bit of DTOC register = 0 * 6 to 7 x fCLK when DAKEBC bit of DTOC register = 1 For details of the function to extend the active width of the DMAAKn signal, see 6.3.8 DMA interface control register (DIFC) or 6.5.1 (2) DMAAKn signal active width extension function. Cautions 1. Do not set the DAKEn bits to 1 during flyby transfer. 2. If either of the following conditions is satisfied when the function to extend the active width of the DMAAKn signal is used, the next DMAAKn signal is asserted while the active width of the preceding DMAAKn signal is extended. As a result, the active cycles of more than one DMAAKn signal combine into one DMAAKn signal, and the number of times the DMAAKn signal is asserted is less than the actual number of DMA cycles. * During block transfer or single-step transfer * When the DMARQn signal is kept active (including when the next DMA request is generated while the DMAAKn signal is active or immediately after it has been deasserted in the pending mode of UARTB) 3 to 0 DRMKn These are mask bits of the DMARQn signal. They specify the DMA mask mode. 0: Do not mask the DMARQn signal. 1: Mask input of the DMARQn signal for the duration of 3 bus clocks from the rising edge of the DMAAKn signal. Caution The period masked by the DRMKn bit is three bus clocks (BUSCLK) from the rising edge of the DMAAKn signal. If the rising edge of the DMAAKn signal is sampled with DRMKn bit = 1, the DMA controller does not recognize the next DMA transfer request if the DMARQn signal is deasserted within 3 bus clocks (BUSCLK) after the rising edge (high level) of the DMAAKn signal has been sampled with BUSCLK. Remarks 1. n = 0 to 3 2. fCLK: Internal system clock 274 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 Transfer Modes 6.4.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence. If other DMA transfer request with the lower priority occurs one clock after single transfer has been completed, however, this request does not take precedence even if the previous DMA transfer request signal with the higher priority remains active. DMA transfer with the lower priority newly request is executed after the CPU bus has been released. Figures 6-1 to 6-4 show examples of single transfer. Figure 6-1. Single Transfer Example 1 DMARQ3 (input) Note Note Note Note CPU CPU DMA3 CPU DMA3 CPU DMA3 CPU CPU CPU CPU CPU CPU DMA3 CPU DMA3 CPU CPU CPU DMA channel 3 terminal count Note The bus is always released. Figure 6-2 shows an example of a single transfer in which a higher priority DMA request is issued. DMA channels 0 to 2 are in the block transfer mode and channel 3 is in the single transfer mode. Figure 6-2. Single Transfer Example 2 DMARQ0 (input) DMARQ1 (input) DMARQ2 (input) DMARQ3 (input) Note Note Note Note CPU CPU CPU DMA3 CPU DMA0 DMA0 CPU DMA1 DMA1 CPU DMA2 DMA2 CPU DMA3 CPU DMA3 DMA channel 1 terminal count DMA channel 3 terminal count DMA channel 0 terminal count DMA channel 2 terminal count Note The bus is always released. User's Manual U16031EJ4V1UD 275 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-3 is an example of single transfer where a DMA transfer request with the lower priority is issued one clock after single transfer has been completed. DMA channels 0 and 3 are used for single transfer. If two DMA transfer request signals become active at the same time, two DMA transfer operations are alternately executed. Figure 6-3. Single Transfer Example 3 DMARQ0 (input) DMARQ3 (input) Note Note Note Note Note Note Note CPU CPU DMA0 CPU DMA0 CPU DMA3 CPU DMA0 CPU DMA3 CPU DMA0 CPU DMA0 CPU DMA0 CPU CPU DMA channel 3 terminal count DMA channel 0 terminal count Note The bus is always released. Figure 6-4 is an example of single transfer where two or more DMA transfer requests with the lower priority are issued one clock after single transfer has been completed. DMA channels 0, 2, and 3 are used for single transfer. If three or more DMA transfer request signals become active at the same time, two DMA transfer operations are alternately executed, always starting from the one with the highest priority. Figure 6-4. Single Transfer Example 4 DMARQ0 (input) DMARQ2 (input) DMARQ3 (input) Note Note Note Note Note Note Note Note Note CPU DMA3 CPU DMA3 CPU DMA2 CPU DMA0 CPU DMA2 CPU DMA0 CPU DMA2 CPU DMA3 CPU DMA2 CPU DMA3 CPU CPU DMA channel 0 terminal count DMA channel 3 DMA channel 2 terminal count terminal count Note The bus is always released. 276 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. subsequent DMA transfer request signal (DMARQ0 to DMARQ3), transfer is performed again. continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence. The following shows an example of a single-step transfer. Figure 6-6 shows an example of single-step transfer made in which a higher priority DMA request is issued. DMA channels 0 and 1 are in the single-step transfer mode. Figure 6-5. Single-Step Transfer Example 1 If there is a This operation DMARQ1 (input) Note Note Note CPU CPU CPU DMA1 CPU DMA1 CPU DMA1 CPU DMA1 CPU CPU CPU CPU CPU CPU CPU DMA channel 1 terminal count Note The bus is always released. Figure 6-6. Single-Step Transfer Example 2 DMARQ0 (input) DMARQ1 (input) Note Note Note Note Note Note CPU CPU CPU DMA1 CPU DMA1 CPU DMA0 CPU DMA0 CPU DMA0 CPU DMA1 CPU DMA1 CPU DMA channel 0 terminal count DMA channel 1 terminal count Note The bus is always released. User's Manual U16031EJ4V1UD 277 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.3 Block transfer mode In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer. After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged. The bus cycle of the CPU is not inserted during block transfer, but bus hold and refresh cycles are inserted in between DMA transfer operations. The following shows an example of block transfer in which a higher priority DMA request is issued. DMA channels 2 and 3 are in the block transfer mode. Figure 6-7. Block Transfer Example DMARQ2 (input) DMARQ3 (input) CPU CPU CPU DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 CPU DMA2 DMA2 DMA2 DMA2 DMA2 The bus is always released. DMA channel 3 terminal count 278 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5 Transfer Types 6.5.1 2-cycle transfer In 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle (DMAC to destination). In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the second cycle, the destination address is output and writing is performed from the DMAC to the destination. Cautions 1. An idle cycle of 1 to 2 clocks is always inserted between a read cycle and a write cycle. 2. See 6.15 (8) Restriction on 2-cycle DMA transfer for restrictions on 2-cycle DMA transfer. Figure 6-8. Timing of 2-Cycle DMA Transfer (SRAM External I/O) (1/2) (a) Single transfer mode (0 waits, BMC register = 00H, level detection mode) T1 BUSCLK (output) T2 TINote 1 TI T2 DMARQx (input) DMAAKx (output) BCYST (output) CSm (output) of SRAM area CSn (output) of external I/O area RD (output) WR (output) Note 2 (output) SDCKE (output) H SDRAS (output) SDCAS (output) H H D0 to D31 (I/O) Data Data Notes 1. 2. This idle state (TI) is independent of the BCC register setting. UUBE/UUDQM, ULBE/ULDQM, LLBE/LLDQM, LUBE/LUDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3 User's Manual U16031EJ4V1UD 279 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8. Timing of 2-Cycle DMA Transfer (SRAM External I/O) (2/2) (b) Single transfer mode (0 waits, BMC register = 00H, edge detection mode) T1 BUSCLK (output) T2 TI Note 1 T1 T2 DMARQx (input) DMAAKx (output) BCYST (output) CSm (output) of SRAM area CSn (output) of external I/O area RD (output) WR (output) Note 2 (output) SDCKE (output) H SDRAS (output) SDCAS (output) H H D0 to D31 (input) Data Data Notes 1. 2. This idle state (TI) is independent of the BCC register setting. UUBE/UUDQM, ULBE/ULDQM, LLBE/LLDQM, LUBE/LUDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3 280 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-9. Timing of 2-Cycle DMA Transfer (SDRAM SRAM): Single Transfer Mode (SRAM Data 1 Wait, SDRAM Latency = 2, BMC Register = 00H, Level Detection Mode) TACT BUSCLK (output) DMARQx (input) DMAAKx (output) BCYST (output) CSm (output) of SRAM area CSn (output) of external I/O area RD (output) WR (output) Note 2 (output) SDCKE (output) SDRAS (output) SDCAS (output) H H TREAD TLATE TLATE TINote 1 T1 TW T2 D0 to D31 (input) Data Data Notes 1. 2. This idle state (TI) is independent of the BCC register setting. UUBE/UUDQM, ULBE/ULDQM, LLBE/LLDQM, LUBE/LUDQM Remarks 1. The broken lines indicate the high-impedance state. 2. m = 0 to 7 n = 1, 3, 4, 6 x = 0 to 3 User's Manual U16031EJ4V1UD 281 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-10. Timing of 2-Cycle DMA Transfer (SRAM SDRAM): Single Transfer Mode (SRAM Data 1 Wait, BMC Register = 00H, Edge Detection Mode) T1 BUSCLK (output) DMARQx (input) DMAAKx (output) BCYST (output) CSm (output) of SRAM area CSn (output) of external I/O area RD (output) WR (output) Note 2 (output) H TW T2 TINote 1 TACT TWR SDCKE (output) SDRAS (output) SDCAS (output) D0 to D31 (I/O) Data Data Notes 1. 2. This idle state (TI) is independent of the BCC register setting. UUBE/UUDQM, ULBE/ULDQM, LLBE/LLDQM, LUBE/LUDQM Remarks 1. The broken lines indicate the high-impedance state. 2. m = 0 to 7 n = 1, 3, 4, 6 x = 0 to 3 282 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM External I/O): Without Speculative Read T0 BUSCLK (output) A0 to A25 (output) BCYST (output) CSn (output) of SRAM area CSn (output) of external I/O area RD (output) Note 1 T1 T2 TI Note 2 T1 T2 Address Address WR (output) Note 3 (output) D0 to D31 (I/O) Data 1 Data 1 WAIT (input) Notes 1. 2. 3. State (T0) inserted between bus cycles This idle state (TI) is independent of the BCC register setting. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 3. n = 0 to 7 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 283 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-12. Timing of 2-Cycle DMA Transfer (SDRAM SRAM) (1/2) (a) Without speculative read T0Note 1 BUSCLK (output) TACT TREAD TLATE TLATE TINote 2 T1 T2 A0 to A25 (output) Row Col. Address BCYST (output) CSn (output) transfer source CSm (output) transfer source SDRAS (output) SDCAS (output) WE (output) H H SDCKE (output) Note 3 (output) Note 4 (output) WR (output) D0 to D31 (I/O) Data Data Notes 1. 2. 3. 4. State (T0) inserted between bus cycles This idle state (TI) is independent of the BCC register setting. When xxWR output mode/xxDQM output mode is set (PFCCTa bit of PFCCT register = 0) When xxBE output mode/xxDQM output mode is set (PFCCTa bit of PFCCT register = 1) Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 7 a = 0 to 3 xx = UU, UL, LU, LL 284 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-12. Timing of 2-Cycle DMA Transfer (SDRAM SRAM) (2/2) (b) With speculative read, speculative read hit T0Note 1 TACT TREAD TREAD TREAD TREAD TLATE TLATE T1 T2 Note 2 TINote 2 TI TINote 2 T1 T2 TINote 2 TINote 2 TINote 2 TINote 2 T1 T2 TINote 2 TINote 2 TINote 2 TINote 2 T1 T2 BUSCLK (output) A0 to A25 (output) Row Col. Col.+4 Col.+8 Col.+C Address Address Address Address BCYST (output) CSn (output) transfer source CSm (output) transfer destination SDRAS (output) SDCAS (output) WE (output) H SDCKE (output) H Note 3 (output) WR (output) D0 to D31 (I/O) Da.1 Da.2 Da.3 Da.4 Da.1 Da.2 Da.3 Da.4 Speculative read cycle (fill cycle of speculative read buffer) Notes 1. 2. 3. State (T0) inserted between bus cycles This idle state (TI) is independent of the BCC register setting. UUDQM, ULDQM, LLDQM, LUDQM Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 m = 0 to 7 3. Da.: Data User's Manual U16031EJ4V1UD 285 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (1) Timing of DMARQn and DMAAKn signals for 2-cycle transfer The targets of 2-cycle transfer are as follows. Table 6-1. Targets of 2-Cycle Transfer Transfer Destination External I/O/External On-Chip Peripheral Memory Transfer source External I/O/external memory On-chip peripheral I/O Internal data RAM I/O x Internal Data RAM Internal Instruction RAM Remarks 1. : Can be transferred, x: Cannot be transferred 2. For details, see Table 6-4 Transfer. The bus configuration is as shown below. Figure 6-13. Bus Configuration Minimum Value of Active Width of DMAAKn Signal for 2-Cycle Internal bus <2> Internal instruction RAM <3> Internal data RAM <4> On-chip peripheral I/O <5> Speculative read buffer External bus <1> DMA controller <7> External I/O/external memory <6> Write buffer Caution The internal bus operates in synchronization with the CPU clock, and the external bus operates in synchronization with the bus clock (BUSCLK). 286 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The active width of the DMAAKn signal output by the DMA controller is from the beginning of a read operation by the DMA controller to the end of a write operation (n = 0 to 3). The DMAAKn signal is not asserted in a cycle used to write/read the internal data RAM. The active width of the DMAAKn signal for each DMA transfer is shown below. Table 6-2. Active Width of DMAAKn Signal for 2-Cycle Transfer Transfer Destination External I/O/External On-Chip Peripheral Memory I/O Transfer source External I/O/external memory <5> (<7>) <1> <6><5> (<7>) <1> <4> On-chip peripheral I/O Internal data RAM <4> <1> <6> <1> <6> <4> <1> <4> <1> <4> Internal Data RAM <5> (<7>) <1> <4> <1> - Internal Instruction RAM <5> (<7>) <1> <2> <4> <1> <2> <1> <2> Remark ( ): Cycle without speculative reading or in case of speculative read miss-hit Therefore, the correlation between external access during 2-cycle transfer (execution to external I/O/external memory) and the active width of the DMAAKn signal is as follows. Table 6-3. Correlation Between External Access (Execution to External I/O/External Memory) and Active Width of DMAAKn Signal Speculative Read Function External I/O/ External Memory x (a) x (a) Provided x (b) x (a) x (a) Transfer Destination On-Chip Peripheral I/O - - x (c) - - Internal Data RAM - - x (c) - - Internal Instruction RAM - - x (c) - - Transfer source External I/O/external memory On-chip peripheral I/O Internal data RAM External I/O/external memory On-chip peripheral I/O Internal data RAM None Remarks : The DMAAKn signal is asserted while DMA access to/from external I/O/external memory is being executed. x: The DMAAKn signal may not be asserted while DMA access to/from external I/O/external memory is being executed. (a): As soon as data has been transferred to the write buffer (<4> <1> <6> or <1> <6>), assertion of the DMAAKn signal ends. Therefore, handshaking of the DMARQn and DMAAKn signals may be completed before a write operation to the external I/O or external memory is executed. If data of three buffers has already been stored in the write buffer separately, data transferred by DMA is stored in the fourth buffer and the DMAAKn signal is deasserted. Subsequently, when a write operation of the stored data has taken place three times, transfer to the external I/O or external memory targeted by the last DMAAKn signal (already deasserted) is executed (<6> <7>). User's Manual U16031EJ4V1UD 287 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (b): Handshaking of the DMARQn and DMAAKn signals may be completed if a read operation from the external I/O or external memory (DMA access) has been completed before handshaking of the DMARQn and DMAAKn signals is completed, or before a write operation to the external I/O or external memory is executed. The active state of the DMAAKn signal ends as soon as data has been transferred to the write buffer (<5> <1> <6>). If speculative reading hits, data is read from the external I/O or external memory when speculative reading has been completed. Therefore, a read operation from the external I/O or external memory (<7> <5>) is executed before the DMAAKn signal. While data is being transferred from the speculative read buffer to the write buffer (<5> <1> <6>) after that, the DMAAKn signal is asserted. For example, if data of three buffers has already been stored in the write buffer, data transferred by DMA is stored in the fourth buffer. After that, transfer to the external I/O or external memory (<6> <7>) targeted by the last DMAAKn signal is executed when a write operation of the stored data has taken place three times. (c): A read operation from the external I/O or external memory (DMA access) may be completed before handshaking of the DMARQn and DMAAKn signals is completed. If speculative reading hits, because the data has already been transferred from the external I/O or external memory to the speculative read buffer (<7> <5>), execution to the external I/O or external memory (DMA access) will have already been completed while the DMAAKn signal was asserted (<5> <1> (<2>, <3> or <4>)). (2) DMAAKn signal active width extension function The DMAAKn signal is output in synchronization with the internal bus cycle during 2-cycle transfer, and is not synchronized with the external bus cycle (n = 0 to 3). The DMA cycle differs depending on the configuration subject to DMA transfer (see 6.5.1 (1) Timing of DMARQn and DMAAKn signals for 2-cycle transfer). Depending on the target of DMA transfer, the configuration may allow the DMAAKn signal to be asserted only for the duration of 2 x fCLK. In this case, assertion of the DMAAKn signal may not be sampled with BUSCLK if the internal system clock (fCLK) is divided and the bus clock (BUSCLK) is used (e.g., BMC register = 02H: internal system clock divided by three). To sample assertion of the DMAAKn signal with BUSCLK, extend the active width of the DMAAKn signal by using the DAKEBC bit of the DTOC register and DAKEn bit of the DIFC register. 288 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The minimum value of the active width of the DMAAKn during 2-cycle transfer is shown in the table below. Table 6-4. Minimum Value of Active Width of DMAAKn Signal During 2-Cycle Transfer Speculative Read Function External I/O/ External Memory Read cycle + 3 x fCLK Transfer Destination On-Chip Peripheral I/O Read cycle + (4+i) x fCLK Internal Data RAM Internal Instruction RAM Read cycle + internal instruction RAM write cycle + 1 x fCLK On-chip peripheral I/O 2 x fCLK 5 x fCLK (3+i) x fCLK (6+i) x fCLK - 2 x fCLK (6+i) x fCLK (7+2i) x fCLK (3+i) x fCLK Internal instruction RAM write cycle + (4+i) x fCLK Internal instruction RAM write cycle Provided Internal instruction RAM write cycle + 3 x fCLK (6+i) x fCLK (7+2i) x fCLK (3+i) x fCLK Internal instruction RAM write cycle + (4+i) x fCLK 2 x fCLK (3+i) x fCLK - Internal instruction RAM write cycle Transfer source External I/O/external memory None Read cycle Internal data RAM External I/O/external memory On-chip peripheral I/O Internal data RAM Caution The function to extend the active width of the DMAAKn signal can be used only during 2-cycle transfer (n = 0 to 3). It cannot be used during flyby transfer. The operation is not guaranteed if it is used during flyby transfer. During flyby transfer, the DMAAKn signal synchronized with the bus cycle is output. Remark i: Number of wait cycles set by VSWC register fCLK: Internal system clock User's Manual U16031EJ4V1UD 289 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5.2 Flyby transfer Since data is transferred in 1 cycle during a flyby transfer, a memory address is always output irrespective whether it is a source address or a destination address, and read/write signals of the memory and on-chip peripheral I/O become active at the same time. Therefore, the external I/O is selected by the DMAAK0 to DMAAK3 signals. To perform a normal access to the external I/O by means other than DMA transfer, externally AND the CSm and DMAAKx signals (m = 0 to 7, x = 0 to 3), and connect the resultant signal to the chip select signal of the external I/O. A circuit example of a normal access, other than DMA transfer, to external I/O is shown below. Caution Flyby transfer to SDRAM is possible only from external I/O. Figure 6-14. Circuit Example When Flyby Transfer Is Performed Between External I/O and SRAM A# to A## D0 to D15 RD LLWR, LUWR CSn A# to A## D0 to D7 OE WE CSn SRAM A# to A## D8 to D15 OE ULWR, UUWR WE CSn SRAM D0 to D15 IORD IOWR DMAAKx CSm V850E/ME2 RD WR CS External I/O Remark n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3 290 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-15. Timing of DMA Flyby Transfer (External I/O SDRAM) (1/3) (a) Single transfer mode TINote 1 BUSCLK (output) TINote 1 TINote 1 T0Note 2 TACT TFNote 3 TWR TINote 1 TINote 1 TINote 1 TINote 1 TINote 1 TINote 1 T0Note 2 TFNote 3 TWR DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) A0 to A25 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) SDCKE (output) Note 4 (ouptut) H Row Col. Col. D0 to D15 (input) IOWR (ouptut) IORD (ouptut) H Data Data Notes 1. 2. 3. 4. Caution This idle state (TI) is independent of the BCC register setting. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. UUDQM, ULDQM, LLDQM, LUDQM In the TF state during SDRAM flyby transfer, wait cycles of the set value of the FWC register + 1 are always inserted (one wait cycle is inserted when the set value is 0 (the case where the set value is 0 is shown above)). Remarks 1. The circle 3. x = 0 to 3 n = 1, 3, 4, 6 indicates the sampling timing. 2. The broken lines indicate the high-impedance state. 4. Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 291 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-15. Timing of DMA Flyby Transfer (External I/O SDRAM) (2/3) (b) Single-step transfer mode TINote 1 BUSCLK (output) TINote 1 TINote 1 T0Note 2 TACT TINote 3 TWR TINote 1 TINote 1 TINote 1 TINote 1 T0Note 2 TINote 3 TWR DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) A0 to A25 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) SDCKE (output) Note 4 (output) Data H Data H Row Col. Col. D0 to D15 (input) IOWR (output) IORD (output) Notes 1. 2. 3. 4. Caution This idle state (TI) is independent of the BCC register setting. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. UUDQM, ULDQM, LLDQM, LUDQM In the TF state during SDRAM flyby transfer, wait cycles of the set value of the FWC register + 1 are always inserted (one wait cycle is inserted when the set value is 0 (the case where the set value is 0 is shown above)). Remarks 1. The circle 3. x = 0 to 3 n = 1, 3, 4, 6 indicates the sampling timing. 2. The broken lines indicate the high-impedance state. 4. Col.: Column address Row: Row address 292 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-15. Timing of DMA Flyby Transfer (External I/O SDRAM) (3/3) (c) Block transfer mode TINote 1 BUSCLK (output) TINote 1 TINote 1 T0Note 2 TACT TINote 3 TWR T0Note 2 TINote 3 TWR DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) A0 to A25 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) SDCKE (output) Note 4 (output) D0 to D15 (input) IOWR (output) IORD (output) H Data Data H Row Col. Col. Notes 1. 2. 3. 4. Caution This idle state (TI) is independent of the BCC register setting. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. UUDQM, ULDQM, LLDQM, LUDQM In the TF state during SDRAM flyby transfer, wait cycles of the set value of the FWC register + 1 are always inserted (one wait cycle is inserted when the set value is 0 (the case where the set value is 0 is shown above)). Remarks 1. The circle 3. x = 0 to 3 n = 1, 3, 4, 6 indicates the sampling timing. 2. The broken lines indicate the high-impedance state. 4. Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 293 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-16. Timing of DMA Flyby Transfer (SRAM External I/O) (1/2) (a) With speculative read/without speculative read, 32-bit bus width T0Note 1 BUSCLK (output) T1 T2 T0Note 1 T1 TFNote 2 T2 T0Note 1 TASWNote 3 T1 TFNote 2 TW T2 TINote 4 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) IOWR (output) IORD (output) Note 5 (output) H H Address Address Address D0 to D31 (input) WAIT (input) Data Data Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. This address setup wait (TASW) is inserted by means of the ASC register setting. This idle state (TI) is inserted by means of the FIC register setting. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 294 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-16. Timing of DMA Flyby Transfer (SRAM External I/O) (2/2) (b) With speculative read/without speculative read, 16-bit bus width, 32-bit data transfer T0Note 1 BUSCLK (output) T1 T2 T1 T2 T0Note 1 TASWNote 3 T1 TFNote 2 T2 TINote 4 TASWNote 3 T1 TFNote 2 T2 TINote 4 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) IOWR (output) IORD (output) Note 5 (output) H H Address A Address A+2 Address B Address B+2 D0 to D15 (input) WAIT (input) Data Data Data Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. This address setup wait (TASW) is inserted by means of the ASC register setting. This idle state (TI) is inserted by means of the FIC register setting. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 295 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-17. Timing of DMA Flyby Transfer (External I/O SRAM) (1/2) (a) With speculative read/without speculative read, 32-bit bus width T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) IOWR (output) IORD (output) Note 5 (output) H H Address Address Address T1 T2 T0Note 1 T1 TFNote 2 T2 T0Note 1 TASWNote 3 T1 TFNote 2 TW T2 TINote 4 D0 to D31 (input) WAIT (input) Data Data Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. This address setup wait (TASW) is inserted by means of the ASC register setting. This idle state (TI) is inserted by means of the FIC register setting. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 296 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-17. Timing of DMA Flyby Transfer (External I/O SRAM) (2/2) (b) With speculative read/without speculative read, 16-bit bus width, 32-bit data transfer T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) IOWR (output) IORD (output) H H Address A Address A+2 Address B Address B+2 T1 T2 T1 T2 T0Note 1 TASWNote 3 T1 TFNote 2 T2 TINote 4 TASWNote 3 T1 TFNote 2 T2 TINote 4 Note 5 (output) D0 to D15 (input) WAIT (input) Data Data Data Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. This address setup wait (TASW) is inserted by means of the ASC register setting. This idle state (TI) is inserted by means of the FIC register setting. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 297 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-18. Timing of DMA Flyby Transfer (Page ROM External I/O) (1/2) (a) With speculative read/without speculative read, 32-bit bus width T0Note 1 BUSCLK (output) T1 T2 T0Note 1 T1 TFNote 2 T2 T0Note 1 TASWNote 3 T1 TFNote 2 TW T2 TINote 4 A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) H Address Address A2 WR (output) IOWR (output) IORD (output) Note 5 (output) H D0 to D31 (input) WAIT (input) Data Data Data Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. This address setup wait (TASW) is inserted by means of the ASC register setting. This idle state (TI) is inserted by means of the FIC register setting. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. 298 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-18. Timing of DMA Flyby Transfer (Page ROM External I/O) (2/2) (b) With speculative read/without speculative read, 16-bit bus width, 32-bit data transfer T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CS0 to CS7 (output) RD (output) WR (output) IOWR (output) IORD (output) Note 5 (output) Data Data Data Data H H Address A Address A+2 Address B Address B+2 T1 T2 T1 T2 T0Note 1 TASWNote 3 T1 TFNote 2 TFNote 2 T2 T1 TFNote 2 TFNote 2 T2 TINote 4 D0 to D15 (input) WAIT (input) Notes 1. 2. 3. 4. 5. State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. This address setup wait (TASW) is inserted by means of the ASC register setting. This idle state (TI) is inserted by means of the FIC register setting. UUBE, ULBE, LUBE, LLBE indicates the sampling timing. Remarks 1. The circle 2. The broken lines indicate the high-impedance state. User's Manual U16031EJ4V1UD 299 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-19. Timing of DMA Flyby Transfer (External I/O SDRAM) (1/2) (a) With speculative read/without speculative read, 32-bit bus width, CAS latency = 2 T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) SDCKE (output) Note 4 (output) H Row Col. Row Col. Col. Col. TACT TFNote 2 TWR T0Note 1 TACT TFNote 2 TFNote 2 TFNote 2 TWR T0Note 1 TFNote 2 TWR T0Note 1 TFNotw 2 TWR TINote 3 D0 to D15 (input) IOWR (output) IORD (output) H Data Data Data Data Notes 1. 2. 3. 4. Caution State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. This idle state (TI) is inserted by means of the FIC register setting. UUDQM, ULDQM, LLDQM, LUDQM In the TF state during SDRAM flyby transfer, wait cycles of the set value of the FWC register + 1 are inserted (one wait cycle is inserted when the set value is 0). Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address Row: Row address 300 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-19. Timing of DMA Flyby Transfer (External I/O SDRAM) (2/2) (b) With speculative read/without speculative read, 16-bit bus width, 32-bit data transfer, CAS latency = 2 T0Note 1 BUSCLK (output) A0 to A25 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) SDCKE (output) Note 3 (output) H Row Col. Col. Col. Col. TACT TFNote 2 TWR TFNote 2 TWR T0Note 1 TFNote 2 TWR TFNote 2 TWR D0 to D15 (input) H Data Data Data Data IOWR (output) IORD (output) Notes 1. 2. 3. Caution State (T0) inserted between bus cycles This wait (TF) is inserted by means of the FWC register setting. UUDQM, ULDQM, LLDQM, LUDQM In the TF state during SDRAM flyby transfer, wait cycles of the set value of the FWC register + 1 are inserted (one wait cycle is inserted when the set value is 0). Remarks 1. The broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6 3. Col.: Column address Row: Row address User's Manual U16031EJ4V1UD 301 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Target 6.6.1 Transfer type and transfer target Table 6-1 lists the relationships between transfer type and transfer target. The mark "" means "transfer possible", and the mark "x" means "transfer impossible". Table 6-5. Relationship Between Transfer Type and Transfer Target Transfer Destination 2-Cycle Transfer On-chip Peripheral I/O On-chip Note 1 Flyby Transfer Internal Data RAM x x x x Internal External Instruction Memory RAM x x x x x x x External I/O Internal Data RAM Note 3 Internal External On-Chip External Instruction Memory Peripheral I/O RAM I/O Note 4 Note 1 Note 2 x x x x x x x Note 5 Transfer source peripheral I/O External I/O Internal data RAM Note 2 x Note 3 Note 4 Note 2 Note 4 External memory Note 4 Notes 1. 2. 3. 4. 5. If the transfer source is the on-chip peripheral I/O, only the single transfer mode can be used. Transfer can also be executed between a little-endian area and a big-endian area. See 6.15 (8) Restriction on 2-cycle DMA transfer for restrictions on 2-cycle DMA transfer. When the internal instruction RAM is in the write mode (IRAMMn bit of IRAMM register = 1), it can be used only as a transfer destination. Flyby transfer to SDRAM is possible only from external I/O. The reverse direction is not possible. Cautions 1. The operation is not guaranteed for combinations of transfer destination and source marked with "x" in Table 6-5. 2. 3. In the case of flyby transfer, make the data bus width the same for the source and destination. Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source and destination address of DMA transfer. Be sure to specify an address between FFFF000H and FFFFFFFH. 4. Do not use DMA transfer to set on-chip peripheral I/O registers and to read the set values. Remarks 1. During 2-cycle DMA transfer, if the data bus width of the transfer source and that of the transfer destination are different, the operation becomes as follows. If DMA transfer is executed to transfer data of an on-chip peripheral I/O register (as a transfer source or destination), be sure to specify the same transfer size as the register size. For example, to execute DMA transfer of an 8-bit register, be sure to specify byte (8-bit) transfer. <32-bit transfer> * Transfer from a 32-bit bus to a 16-bit bus A read cycle (32 bits) is generated and then a write cycle (16 bits) is generated twice consecutively. 302 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) * Transfer from a 32-bit bus to an 8-bit bus A read cycle (32 bits) is generated and then a write cycle (8 bits) is generated 4 times consecutively. * Transfer from a 16-bit bus to an 8-bit bus A read cycle (16 bits) is generated twice consecutively and then a write cycle (8 bits) is generated 4 times consecutively. * Transfer from a 16-bit bus to a 32-bit bus A read cycle (16 bits) is generated twice consecutively and then a write cycle (32 bits) is generated. For how to write data to the transfer destination, see Remark 2 below. * Transfer from an 8-bit bus to a 32-bit bus A read cycle (8 bits) is generated 4 times consecutively and then a write cycle (32 bits) is generated. For how to write data to the transfer destination, see Remark 2 below. * Transfer from an 8-bit bus to a 16-bit bus A read cycle (8 bits) is generated 4 times consecutively and then a write cycle (16 bits) is generated twice consecutively. For how to write data to the transfer destination, see Remark 2 below. <16-bit transfer> * Transfer from a 32-bit bus to a 16-bit bus A read cycle (the higher 16 bits are high impedance) is generated and then a write cycle (16 bits) is generated. * Transfer from a 32-bit bus to an 8-bit bus A read cycle (the higher 16 bits are high impedance) is generated and then a write cycle (8 bits) is generated twice consecutively. * Transfer from a 16-bit bus to an 8-bit bus A read cycle (16 bits) is generated and then a write cycle (8 bits) is generated twice consecutively. * Transfer from a 16-bit bus to a 32-bit bus A read cycle (16 bits) is generated and then a write cycle (the higher 16 bits are high impedance) is generated. For how to write data to the transfer destination, see Remark 2 below. * Transfer from an 8-bit bus to a 32-bit bus A read cycle (8 bits) is generated twice consecutively and then a write cycle (the higher 16 bits are high impedance) is generated. For how to write data to the transfer destination, see Remark 2 below. * Transfer from an 8-bit bus to a 16-bit bus A read cycle (8 bits) is generated twice consecutively and then a write cycle (16 bits) is generated. For how to write data to the transfer destination, see Remark 2 below. <8-bit transfer> * Transfer from a 32-bit bus to a 16-bit bus A read cycle (the higher 24 bits are high impedance) is generated and then a write cycle (the higher 8 bits are high impedance) is generated. * Transfer from a 32-bit bus to an 8-bit bus A read cycle (the higher 24 bits are high impedance) is generated and then a write cycle (8 bits) is generated. * Transfer from a 16-bit bus to an 8-bit bus A read cycle (the higher 8 bits are high impedance) is generated and then a write cycle (8 bits) is generated. User's Manual U16031EJ4V1UD 303 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) * Transfer from a 16-bit bus to a 32-bit bus A read cycle (the higher 8 bits are high impedance) is generated and then a write cycle (the higher 24 bits are high impedance) is generated. For how to write data to the transfer destination, see Remark 2 below. * Transfer from an 8-bit bus to a 32-bit bus A read cycle (8 bits) is generated and then a write cycle (the higher 24 bits are high impedance) is generated. For how to write data to the transfer destination, see Remark 2 below. * Transfer from an 8-bit bus to a 16-bit bus A read cycle (8 bits) is generated and then a write cycle (the higher 8 bits are high impedance) is generated. For how to write data to the transfer destination, see Remark 2 below. Remarks 2. Under the following conditions, data is written to the lower byte and then the higher byte of the transfer destination in the little-endian mode, and to the higher byte and lower byte of the destination in the big-endian mode. * Transfer from a 16-bit bus to a 32-bit bus * Transfer from an 8-bit bus to a 32-bit bus * Transfer from an 8-bit bus to a 16-bit bus 6.6.2 External bus cycles during DMA transfer The external bus cycles during DMA transfer are shown below. Table 6-6. External Bus Cycles During DMA Transfer Transfer Type 2-cycle transfer Transfer Target On-chip peripheral I/O, internal data RAM, internal instruction RAM External I/O External memory Flyby transfer Between external memory and external I/O Yes Yes Yes SRAM cycle Memory access cycle set by the BCT register DMA flyby transfer cycle accessing memory that is set as external memory by the BCT register None External Bus Cycle - 6.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 In the block transfer mode, the channel used for transfer is never switched. In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released, the higher priority DMA transfer request is acknowledged. Caution If DMA is started by inputting the same signal to more than one DMARQn pin (n = 0 to 3), a DMA channel with a lower priority may be acknowledged before a DMA channel with a higher priority. 304 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.8 Next Address Setting Function The DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers are buffer registers with a 2-stage FIFO format (n = 0 to 3). When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately before. Therefore, during DMA transfer, transfer is automatically started when a new DMA transfer setting is made for these registers and the Enn bit of the DCHCn register, and MLEn bit is set to 1 (however, the DMA transfer end interrupt may be issued even if DMA transfer is automatically started). The configuration of the buffer register is shown below. Figure 6-20. Buffer Register Configuration Data read Internal bus Data write Master register Slave register Address/ count controller The actual DMA transfer is executed in accordance with the contents of the slave register. The set values that are reflected in the master register and slave register differ as follows, depending on the timing (period) of setting the registers. (1) Period from system reset to the beginning of the first DMA transfer The set value is reflected in both the master register and slave register. (2) During DMA transfer (period from the beginning to the end of DMA transfer) The set value is reflected only in the master register and not in the slave register (the slave register holds the set value for the next DMA transfer). However, the contents of the master register are automatically overwritten to the slave register after completion of DMA transfer. If the value of each register is read during this period, the value of the slave register is read. (3) Period from the end of DMA transfer to the beginning of the next DMA transfer The set value is reflected in both the master register and slave register. Remark "The end of DMA transfer" means either of the following. * Completion of DMA transfer (terminal count) * Forced termination of DMA transfer (setting the INITn bit of the DMA channel control register (DCHCn) to 1) User's Manual U16031EJ4V1UD 305 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) If the setting of a new DMA transfer is made using the DSAnH, DSAnL, DDAnL, and DBCn registers during DMA transfer, the values of the registers are automatically updated after completion of transferNote. Note Before setting a new DMA transfer, confirm the start of the preceding DMA transfer. If the setting of the new DMA transfer is made before the start of the preceding DMA transfer, the new set value is overwritten to both the master register and slave register, and DMA transfer according to the preceding set value cannot be executed. 306 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.9 DMA Transfer Start Factors There are 4 types of DMA transfer start factors, as shown below. Cautions 1. Do not use two or more start factors ((1) to (4)) in combination for the same channel (if two or more start factors are generated at the same time, only one of them is valid, but the valid start factor cannot be identified). The operation is not guaranteed if two or more start factors are used in combination. 2. If DMA transfer is started via software and if the software does not correctly detect whether the expected DMA transfer operation has been completed through manipulation (setting to 1) of the STGn bit of the DCHCn register, it cannot be guaranteed whether the next (second) manipulation of the STGn bit corresponds to the start of "the next DMA transfer expected by software" (n = 0 to 3). For example, suppose single transfer is started by manipulating the STGn bit. Even if the STGn bit is manipulated next (the second time) without checking by software whether the single transfer has actually been executed, the next (second) DMA transfer is not always executed. This is because the STGn bit may be manipulated the second time before the first DMA transfer is started or completed because, for example, DMA transfer with a higher priority had already been started when the STGn bit was manipulated for the first time. It is therefore necessary to manipulate the STGn bit next time (the second time) after checking whether DMA transfer started by the first manipulation of the STGn bit has been completed. Completion of DMA transfer can be checked in the following ways. * Detecting the acknowledge signal (DMAAKn) or terminal count signal (TCn) by using a peripheral port or interrupt * Checking the contents of the DBCn register User's Manual U16031EJ4V1UD 307 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (1) Request from an external pin (DMARQn) Requests from the DMARQn pin are sampled each time the BUSCLK signal rises (n = 0 to 3). Hold the request from DMARQn pin until the corresponding DMAAKn signal becomes active. If a state whereby the Enn bit of the DCHCn register = 1 and the TCn bit = 0 is set, the DMARQn signal becomes valid. If the DMARQn signal set by the DTFRn register becomes active in this status, DMA transfer starts. Remark Since the DMARQn signal is level-sampled and not edge-detected, to enable edge detection of a DMA request, set an external interrupt request for the DMA start trigger instead of using the DMARQn signal (n = 0 to 3). (2) Request from software If the STGn, Enn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3). * STGn bit = 1 * Enn bit = 1 * TCn bit = 0 (3) Request from on-chip peripheral I/O If, when the Enn and TCn bits of the DCHCn register are set as shown below, an interrupt request is issued from the on-chip peripheral I/O that is set in the DTFRn register, DMA transfer starts (n = 0 to 3). * Enn bit = 1 * TCn bit = 0 (4) Request by USB (enabled only in single transfer mode) If a request is generated from the USB set to the DTFRn register when the Enn and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3). * Enn bit = 1 * TCn bit = 0 308 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 Terminal Count Output upon DMA Transfer End The terminal count signal (TCn) becomes active for one clock of BUSCLK during the last DMA transfer cycle (n = 3 to 0). Figure 6-21. Terminal Count Signal (TCn) Timing Example (1) DMARQn (input) TCn (output) CPU CPU CPU DMAn DMAn DMAn CPU DMA channel n terminal count Remark n = 0 to 3 The TCn signal becomes active for one clock in any clock, from which the DMAAKn signal of the last DMA transfer is output when 2-cycle transfer is executed. If the transfer destination is the internal data RAM, however, the TCn signal is not output. When flyby transfer is executed, the TCn signal becomes active for one clock at the clock in which the BCYST signal of the last DMA transfer cycle becomes active. Figure 6-22. Terminal Count Signal (TCn) Timing Example (2) (1) 2-cycle transfer 2-cycle transfer (last) Read cycle BUSCLK (output) TCn (output) Write cycle (2) Flyby transfer Flyby transfer cycle (last) BUSCLK (output) TCn (output) Remark n = 0 to 3 User's Manual U16031EJ4V1UD 309 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.11 Forcible Interruption DMA transfer can be forcibly interrupted by NMI input during DMA transfer. At such a time, the DMAC resets the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer disabled state is entered. An NMI request can then be acknowledged after the DMA transfer that was being executed when the NMI was input is complete (n = 0 to 3). 310 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12 Forcible Termination DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register, in addition to the forcible interruption operation by means of NMI input (n = 0 to 3). An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3). Figure 6-23. Example of Forcible Termination of DMA Transfer (a) Block transfer through DMA channel 3 is started during single-step transfer through DMA channel 2 DSA2, DDA2, DBC2, DADC2, DCHC2 Register set DCHC2 (INIT2 bit = 1) Register set E22 bit 0 TC2 bit = 0 DSA3, DDA3, DBC3, DADC3, DCHC3 Register set DMARQ2 (input) E22 bit = 1 TC2 bit = 0 DMARQ3 (input) E33 bit = 1 TC3 bit = 0 E33 bit 0 TC3 bit 1 CPU CPU CPU CPU DMA2 CPU DMA2 CPU DMA2 CPU DMA3 DMA3 DMA3 DMA3 CPU CPU CPU DMA channel 3 terminal count DMA channel 3 transfer start Forcible termination of DMA channel 2 transfer (b) When transfer is aborted during DMA channel 1 single-step transfer, and transfer under another condition is executed DSA1, DDA1, DBC1, DADC1, DCHC1 Register set DSA1, DDA1, DBC1 Register set DCHC1 (INIT1 bit = 1) DADC1, DCHC1 Register set E11 bit 0 TC1 bit 1 Register set E11 bit 0 TC1 bit = 0 DMARQ1 (input) E11 bit = 1 TC1 bit = 0 E11 bit 1 TC1 bit = 0 CPU CPU CPU CPU CPU DMA1 CPU DMA1 CPU DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 CPU Forcible termination of DMA channel 1 transfer DMA channel 1 terminal count Remark The values of the DSAn, DDAn, and DBCn registers (n = 0 to 3) are retained even when DMA transfer is forcibly stopped, because these registers are FIFO-configured buffer registers. The next transfer condition can be set to these registers even while DMA transfer is in progress. On the other hand, the setting of the DADCn and DCHCn registers is invalid during DMA transfer because these registers are not buffer registers (see 6.8 registers 0 to 3 (DCHC0 to DCHC3)). Next Address Setting Function, 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3), and 6.3.5 DMA channel control User's Manual U16031EJ4V1UD 311 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.13 Times Related to DMA Transfer The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below. In the case of external memory access, the time depends on the type of external memory connected. Table 6-7. Number of Minimum Execution Clocks in DMA Cycle DMA Cycle <1> Time to respond to DMA request <2> Memory access External memory access Internal data RAM or internal instruction RAM (read mode) access On-chip peripheral I/O register access Number of Minimum Execution Clocks 4 clocks Note 1 Differs depending on the memory connected 2 clocks Note 2 3 clocks + Number of wait cycles specified by VSWC register Notes 1. If an external interrupt (INTPn) is specified as a factor of starting DMA transfer, noise elimination time is added (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, or L1). 2. Two clocks are required for the DMA cycle. The minimum execution clock in the DMA cycle in each transfer mode is as follows. 2-cycle transfer * Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1Note + Transfer destination memory access (<2>) * Block transfer: DMA response time (<1>) + (Transfer source memory access (<2>) + 1Note + Transfer destination memory access (<2>)) x Number of transfers Note One clock is always inserted between the read cycle and write cycle of DMA transfer. However, two clocks are inserted when the undivided external bus clock is used. Flyby transfer: DMA response time (<1>) + External memory access (<2>) 312 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.14 Maximum Response Time for DMA Transfer Request The response time for a DMA transfer request becomes the longest under the following conditions (state in which all the refresh cycles for the SDRAM are enabled). Caution The wait time caused by the following conditions is not included. * DMA transfer with a higher priority occurs * When DMA transfer triggered by other than the DMARQn pin input occurs * External bus hold * Speculative read buffer * Cache miss-hit Condition Instruction fetch from an external memory using 8-bit data bus width Execution of a bit manipulation instruction (SET1, CLR1, or NOT1) A branch instruction (JR, JARL, JMP, or Bcond) follows a bit manipulation instruction Either DMA transfer source or destination is internal RAM The DRMKn bit of the DIFC register = 1 4 channels of SDRAM are used Response time Tinst x16 + Tdata x 2 + Tref x 4 + BUSCLK x 4 BUSCLK x 4 Tdata Tinst x 16 (8-bit bus) Tdata Tinst x 16 (8-bit bus) Tref x 4 DMARQn (input) DMAAKn (output) D0 to D31 (I/O) Data read Data read Fetch (32 bits) Data write Data read Fetch (32 bits) Refresh DMA cycle Previous DMA transfer ends DMARQn input masked for 4 BUSCLK clocks from the rise of the DMAAKn signal. Number of channels in SDRAM area (4 max.) Remarks 1. Tinst: Tref: Number of clocks per bus cycle during instruction fetch Number of clocks per refresh cycle Tdata: Number of clocks per bus cycle during data access BUSCLK x 4: Time for masking DMARQn input 2. n = 0 to 3 User's Manual U16031EJ4V1UD 313 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.15 Cautions Cautions concerning the DMA function are shown below. (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects (external memory, internal data RAM, internal instruction RAM, or on-chip peripheral I/O) during DMA transfer. (2) Transfer of misaligned data DMA transfer of 32-/16-bit bus width misaligned data is not supported. If the source or the destination address is set to an odd address, the LSB of the address is forcibly handled as "0". (3) Bus arbitration for CPU When DMA transfer is executed to transfer data to/from an external device, the CPU can access internal data RAM and internal instruction RAMNote not being used for DMA transfer. Because the DMA controller has a priority higher than the CPU acquiring bus mastership, a CPU access that takes place during DMA transfer is kept waiting until the preceding DMA transfer is completed and the bus is released to the CPU. If DMA transfer is executed between the external memory and on-chip peripheral I/O, however, the CPU can access the internal data RAM and internal instruction RAMNote. Note When the IRAMMn bit of the IRAMM register = 0 (n = 0, 1) (4) Holding DMARQn signal Be sure to keep the DMARQn signal active until the DMAAKn signal becomes active (n = 0 to 3). (5) DMAAKn signal output When the transfer target is internal data RAM, the DMAAKn signal is not output during a DMA cycle for internal data RAM (for example, if 2-cycle transfer is performed from internal data RAM to an external memory, the DMAAKn signal is output only during a DMA write cycle for the external memory). If the transfer target is the on-chip peripheral I/O or internal instruction RAM, the DMAAKn signal is output even in the DMA cycle executed on the on-chip peripheral I/O or internal instruction RAM. The DMAAKn signal maintains the active state during the TI state of flyby transfer. (6) DMA start factors Do not start two or more DMA channels with the same factor. If two or more DMA channels are started with the same factor, the DMA channel with the lower priority may be accepted before the DMA channel with the higher priority. 314 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (7) Read values of DSAn and DDAn registers If the values of the DSAn and DDAn registers are read during DMA transfer, the values in the middle of being updated may be read (n = 0 to 3). For example, if the DSAnH register and the DSAnL register are read in that order when the value of the DMA transfer source address (DSAn register) is "0000FFFFH" and the counting direction is incremental (when the SADn1 and SADn0 bits of the DADCn register = 00), the value of the DSAnL register differs as follows depending on whether DMA transfer is executed immediately after the DSAnH register has been read. (a) If DMA transfer does not occur while the DSAn register is being read <1> Reading DSAnH register: DSAnH = 0000H <2> Reading DSAnL register: DSAnL = FFFFH (b) If DMA transfer occurs while the DSAn register is being read <1> Reading DSAnH register: DSAnH = 0000H <2> Occurrence of DMA transfer <3> Incrementing DSAn register : DSAn = 00010000H <4> Reading DSAnL register: DSAnL = 0000H (8) Restriction on 2-cycle DMA transfer When performing any of the following 2-cycle DMA transfers, the TC signal output may become active twice (normally it becomes active once) and the DMA transfer end interrupt may occur twice (normally it occurs once) when the last data has been transferred. However, the DMA transfer itself is completed normally. This bug does not occur during flyby transfer. * The speculative read function (set by the LBC0 or LBC1 register) is enabled for a CS space and 2-cycle DMA transfer from external memory to internal data RAM is executed. * 2-cycle DMA transfer from on-chip peripheral I/O to internal data RAM is executed (regardless of the speculative read function setting). [Countermeasures] * In the case of 2-cycle DMA transfer from external memory to internal data RAM Disable the speculative read function for the CS space in the DMA transfer source (side to be read). * In the case of 2-cycle DMA transfer from on-chip peripheral I/O to internal data RAM Do not use the TC signal. In addition, execute the processing of <1> and <2> below consecutively for the excessive DMA transfer end interrupt in the DMA transfer end interrupt servicing routine. After the processing of <2> is executed, by executing the application processing that should be performed in the normal operation and restoring from the interrupt, occurrence of the second DMA transfer end interrupt can be suppressed. <1> Clear the WAS register to 00H. <2> Clear bit 7 (DMAIFn) of the interrupt control register (DMAICn) of the same channel as the DMA transfer end interrupt currently being serviced to 0 (n = 0 to 3). User's Manual U16031EJ4V1UD 315 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (9) Caution on setting DSAnH register When setting an address of an on-chip peripheral I/O register for the source address, be sure to specify an address between FFFF000H and FFFFFFFH. (3FFF000H to 3FFFFFFH) must not be specified. (10) Cautions on setting DDAnH register * When setting an address of an on-chip peripheral I/O register for the destination address, be sure to specify an address between FFFF000H and FFFFFFFH. An address of the on-chip peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified. * When enabling the speculative read function is selected for the CS space at the DMA transfer destination, set the DMA transfer destination address so that the address on which a speculative read is performed and the line address to which the last DMA transfer data is written are not the same line address (the same line address means that A25 to A4 are the same in the same CS space). (11) Cautions on setting DADCn register Do not set flyby transfer via the TTYPn bit of the DADCn register if all the following conditions are satisfied (n = 0 to 3). * BMC register = 00H * FWn2 to FWn0 bits of FWC register = 000 * FIn1 to FIn0 bits of FIC register = 00 * ACn1 and ACn0 bits of the CSn space subject to flyby transfer by the ASC register = 00 (during transfer to/from SRAM) (12) Cautions on setting CDHCn register During a 2-cycle transfer that performs a write operation on the external device, the write operation on the external device may not be completed even if the TCn bit of the DCHCn register is set to 1 (DMA transfer completion) by the write buffer function. Recognize completion of the write operation on the external device as follows, if necessary. * Monitor the signal of the TCn pin (the TCn pin becomes active in synchronization with a write operation to the external device). * After it has been detected that the TCn bit of the DCHCn register is set to 1, write 00H to the WAS register or write the same value as that set to the LBC0 or LBC1 register. When this write is completed, completion of an access from the write buffer to the external device can be recognized. If the set value of the LBC0 or LBC1 register is rewritten when a dummy write to the LBC0 or LBC1 register is executed, the operation is not guaranteed. (13) Caution on setting DTFRn register An interrupt request from an on-chip peripheral I/O input in the standby mode (IDLE or software STOP mode) is held pending as a DMA transfer start factor. The held DMA start factor is executed following return to the normal operation mode. (14) DMAAKn signal active width extension function The function to extend the active width of the DMAAKn signal can be used only during 2-cycle transfer (n = 0 to 3). It cannot be used during flyby transfer. The operation is not guaranteed if it is used during flyby transfer. An address of the on-chip peripheral I/O register image 316 User's Manual U16031EJ4V1UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (15) SDRAM flyby transfer Flyby transfer to SDRAM is possible only from external I/O. 6.15.1 Interrupt factors DMA transfer is interrupted if the following factors are issued. * Bus hold * Refresh cycle If the factor that is interrupting DMA transfer disappears, DMA transfer promptly restarts. 6.16 DMA Transfer End When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt (INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3). User's Manual U16031EJ4V1UD 317 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/ME2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 91 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850E/ME2 can process interrupt requests from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 7.1 Features Interrupts * Non-maskable interrupts: 1 source Caution P20 is fixed to NMI input. The level of the NMI pin is read when the P20 bit of the P2 register is read, regardless of the value of the PM2 and PMC2 registers. Set the valid edge of the NMI pin by using the NMIR0 bit of the INTR2 register and the NMIF0 bit of the INTF2 register (default value: both rising/falling edges detection). * Maskable interrupts: External: 39 sources, Internal: 59 sources * 8 levels of programmable priorities (maskable interrupts) * Multiple interrupt control according to priority * Masks can be specified for each maskable interrupt request. * Noise eliminationNote, edge detection, and valid edge specification for external interrupt request signals. Note For details of the noise eliminator, see 14.6 Noise Eliminator. Exceptions * Software exceptions: 32 sources * Exception traps: 2 sources (illegal opcode exception and debug trap) Interrupt sources are listed in Table 7-1. 318 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (1/3) Type Classification Name Interrupt/Exception Source Controlling Register Reset Non-maskable Software exception Exception trap Interrupt Interrupt Exception Exception Exception RESET NMI0 TRAP0n Note Default Exception Generating Priority Unit - - - - - Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin TMC0 TMC1 TMC2 TMC3 TMC4 - - - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Code Handler Address Restored PC Generating Source - - - - - P1IC0 P1IC1 P2IC1 P2IC2 P2IC3 P2IC4 P2IC5 P5IC0 P5IC1 P5IC2 P6IC5 P6IC6 P6IC7 PDIC0 PDIC1 PDIC2 PDIC3 PDIC4 PDIC5 PDIC6 PDIC7 PDIC8 PDIC9 PDIC10 PDIC11 PDIC12 PDIC13 PDIC14 PDIC15 PLIC0 PLIC1 OVCIC0 OVCIC1 OVCIC2 OVCIC3 OVCIC4 Reset input NMI input TRAP instruction TRAP instruction Illegal opcode/ DBTRAP instruction INTP10 pin INTP11 pin INTP21 pin INTP22 pin INTP23 pin INTP24 pin INTP25 pin INTP50 pin INTP51 pin INTP52 pin INTP65 pin INTP66 pin INTP67 pin INTPD0 pin INTPD1 pin INTPD2 pin INTPD3 pin INTPD4 pin INTPD5 pin INTPD6 pin INTPD7 pin INTPD8 pin INTPD9 pin INTPD10 pin INTPD11 pin INTPD12 pin INTPD13 pin INTPD14 pin INTPD15 pin INTPL0 pin INTPL1 pin Timer C0 overflow Timer C1 overflow Timer C2 overflow Timer C3 overflow Timer C4 overflow 0000H 0010H 004nH Note 00100000H 00000010H 00000040H 00000050H 00000060H Undefined nextPC nextPC nextPC nextPC TRAP1nNote ILGOP/ DBG0 005nHNote 0060H Maskable Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt INTP10 INTP11 INTP21 INTP22 INTP23 INTP24 INTP25 INTP50 INTP51 INTP52 INTP65 INTP66 INTP67 INTPD0 INTPD1 INTPD2 INTPD3 INTPD4 INTPD5 INTPD6 INTPD7 INTPD8 INTPD9 INTPD10 INTPD11 INTPD12 INTPD13 INTPD14 INTPD15 INTPL0 INTPL1 INTOVC0 INTOVC1 INTOVC2 INTOVC3 INTOVC4 0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H 0190H 01A0H 01B0H 01C0H 01D0H 01E0H 01F0H 0200H 0210H 0220H 0230H 0240H 0250H 0260H 0270H 0280H 0290H 02A0H 02B0H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001A0H 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC Note n = 0H to FH User's Manual U16031EJ4V1UD 319 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (2/3) Type Classification Name Interrupt/Exception Source Controlling Register Maskable Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt INTOVC5 INTPC00/ INTCCC00 INTPC01/ INTCCC01 INTPC10/ INTCCC10 INTPC11/ INTCCC11 INTPC20/ INTCCC20 INTPC21/ INTCCC21 INTPC30/ INTCCC30 INTPC31/ INTCCC31 INTCCC40 INTCCC41 INTCCC50 INTCCC51 INTCMD0 INTCMD1 INTCMD2 INTCMD3 INTCC100 INTCC101 INTCM100 INTCM101 INTOV10 INTUD10 INTCC110 INTCC111 INTCM110 INTCM111 INTOV11 INTUD11 INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTCSI30 INTCOVF30 INTCSI31 INTCOVF31 CCC4IC0 CCC4IC1 CCC5IC0 CCC5IC1 CMDIC0 CMDIC1 CMDIC2 CMDIC3 CC10IC0 CC10IC1 CM10IC0 CM10IC1 OV1IC0 UD1IC0 CC11IC0 CC11IC1 CM11IC0 CM11IC1 OV1IC1 UD1IC1 DMAIC0 DMAIC1 DMAIC2 DMAIC3 CSI3IC0 COVF3IC0 CSI3IC1 COVF3IC1 CCC3IC1 CCC3IC0 CCC2IC1 CCC2IC0 CCC1IC1 CCC1IC0 CCC0IC1 OVCIC5 CCC0IC0 Timer C5 overflow Match of INTPC00 pin/CCC00 Match of INTPC01 pin/CCC01 Match of INTPC10 pin/CCC10 Match of INTPC11 pin/CCC11 Match of INTPC20 pin/CCC20 Match of INTPC21 pin/CCC21 Match of INTPC30 pin/CCC30 Match of INTPC31 pin/CCC31 CCC40 match CCC41 match CCC50 match CCC51 match CMD0 match CMD1 match CMD2 match CMD3 match CC100 match CC101 match CM100 match CM101 match Timer ENC10 overflow Timer ENC10 underflow CC110 match CC111 match CM110 match CM111 match Timer ENC11 overflow Timer ENC11 underflow End of DMA0 transfer End of DMA1 transfer End of DMA2 transfer End of DMA3 transfer CSI30 transmission/ reception completion CSI30BUF overflow CSI31 transmission/ reception completion CSI31BUF overflow CSI31 72 0500H 00000500H nextPC CSI30 CSI31 70 71 04E0H 04F0H 000004E0H 000004F0H nextPC nextPC TMC4 TMC4 TMC5 TMC5 TMD0 TMD1 TMD2 TMD3 TMENC10 TMENC10 TMENC10 TMENC10 TMENC10 TMENC10 TMENC11 TMENC11 TMENC11 TMENC11 TMENC11 TMENC11 DMA DMA DMA DMA CSI30 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 0350H 0360H 0370H 0380H 0390H 03A0H 03B0H 03C0H 03D0H 03E0H 03F0H 0400H 0410H 0420H 0430H 0440H 0450H 0460H 0470H 0480H 0490H 04A0H 04B0H 04C0H 04D0H 00000350H 00000360H 00000370H 00000380H 00000390H 000003A0H 000003B0H 000003C0H 000003D0H 000003E0H 000003F0H 00000400H 00000410H 00000420H 00000430H 00000440H 00000450H 00000460H 00000470H 00000480H 00000490H 000004A0H 000004B0H 000004C0H 000004D0H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC Pin/TMC3 44 0340H 00000340H nextPC Pin/TMC3 43 0330H 00000330H nextPC Pin/TMC2 42 0320H 00000320H nextPC Pin/TMC2 41 0310H 00000310H nextPC Pin/TMC1 40 0300H 00000300H nextPC Pin/TMC1 39 02F0H 000002F0H nextPC Pin/TMC0 38 02E0H 000002E0H nextPC Generating Source Unit TMC5 Pin/TMC0 36 37 02C0H 02D0H 000002C0H 000002D0H nextPC nextPC Default Exception Generating Priority Code Handler Address Restored PC 320 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt Source List (3/3) Type Classification Name Interrupt/Exception Source Controlling Register Maskable Interrupt Interrupt UBTIRE0 UBTIR0 UREIC0 URIC0 UARTB0 reception error UARTB0 reception completion Interrupt UBTIT0 UTIC0 UARTB0 transmission completion Interrupt UBTIF0 UIFIC0 UARTB0 FIFO transmission completion Interrupt UBTITO0 UTOIC0 UARTB0 reception timeout Interrupt Interrupt UBTIRE1 UBTIR1 UREIC1 URIC1 UARTB1 reception error UARTB1 reception completion Interrupt UBTIT1 UTIC1 UARTB1 transmission completion Interrupt UBTIF1 UIFIC1 UARTB1 FIFO transmission completion Interrupt UBTITO1 UTOIC1 UARTB1 reception timeout Interrupt Interrupt Interrupt Interrupt Interrupt INTAD INTUSB0B INTUSB1B INTUSB2B USBSP2B ADIC US0BIC US1BIC US2BIC USP2IC End of A/D conversion USB function status 0 USB function status 1 USB function status 2 Forcible end of USB function EP2 DMA Interrupt USBSP4B USP4IC Forcible end of USB function EP4 DMA Interrupt INTRSUM RSUMIC USB Resume signal detection SIE 89 0610H 00000610H nextPC USBF 88 0600H 00000600H nextPC ADC USBF USBF USBF USBF 83 84 85 86 87 05B0H 05C0H 05D0H 05E0H 05F0H 000005B0H 000005C0H 000005D0H 000005E0H 000005F0H nextPC nextPC nextPC nextPC nextPC UARTB1 82 05A0H 000005A0H nextPC UARTB1 81 0590H 00000590H nextPC UARTB1 80 0580H 00000580H nextPC UARTB1 UARTB1 78 79 0560H 0570H 00000560H 00000570H nextPC nextPC UARTB0 77 0550H 00000550H nextPC UARTB0 76 0540H 00000540H nextPC UARTB0 75 0530H 00000530H nextPC Generating Source Default Exception Generating Priority Unit UARTB0 UARTB0 73 74 0510H 0520H 00000510H 00000520H nextPC nextPC Code Handler Address Restored PC Remarks 1. Default Priority: Restored PC: The priority order when two or more maskable interrupt request signals are generated at the same time. The highest priority is 0. The value of the program counter (PC) saved to EIPC, FEPC, or DBPC of the CPU when interrupt servicing is started. Note, however, that the restored PC when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextPC. (If an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished. In this case, the address of the aborted instruction is the restore PC.) * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Division instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only if an interrupt is generated before the stack pointer is updated) nextPC: The PC value from which the processing starts following interrupt/exception processing. 2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). User's Manual U16031EJ4V1UD 321 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI request signal is not subject to priority control and takes precedence over all the other interrupt request signals. A non-maskable interrupt request signal is input from the NMI pin. When the valid edge specified by bit 0 (NMIR0) of external interrupt rising edge specification register 2 (INTR2) or bit 0 (NMIF0) of external interrupt falling edge specification register 2 (INTF2) is detected at the NMI pin, the interrupt occurs. While the service program of the non-maskable interrupt is being executed, the acknowledgment of another nonmaskable interrupt request signal is held pending. The pending NMI is acknowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the RETI instruction). Note that if two or more NMI request signals are input during the execution of the service program for an NMI, the number of NMIs that will be acknowledged after the RETI instruction is executed is cleared to 0 is only one. 322 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine: <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes exception code 0010H to the higher halfword (FECC) of ECR. <4> Sets the NP and ID bits of the PSW to 1 and clears the EP bit of the PSW to 0. <5> Sets the handler address (00000010H) corresponding to the non-maskable interrupt to the PC, and transfers control. The servicing configuration of a non-maskable interrupt is shown in Figure 7-1. Figure 7-1. Servicing Configuration of Non-Maskable Interrupt NMI input INTC acknowledged Non-maskable interrupt request CPU processing PSW.NP 0 FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC Restored PC PSW 0010H 1 0 1 00000010H Interrupt request held pending 1 Interrupt servicing User's Manual U16031EJ4V1UD 323 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service program is being executed Main routine (PSW.NP = 1) NMI request NMI request NMI request is held pending regardless of the value of the NP bit of PSW. Pending NMI request serviced (b) If a new NMI request is generated twice while an NMI service program is being executed Main routine NMI request NMI request Held pending because NMI service program is being serviced NMI request Held pending because NMI service program is being serviced Only one NMI request is acknowledged even though two NMI requests are generated 324 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from the non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1. <2> Transfers control back to the address of the restored PC and PSW. Figure 7-3 illustrates how the RETI instruction is processed. Figure 7-3. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during nonmaskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the PSW.EP bit back to 0 and the PSW.NP bit back to 1 using the LDSR instruction immediately before the RETI instruction. The solid line shows the CPU processing flow. Remark User's Manual U16031EJ4V1UD 325 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set to 1 when an NMI interrupt request signal has been acknowledged, and masks NMI interrupt requests to prohibit multiple interrupts from being acknowledged. 31 PSW 876543210 After reset 00000020H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z Bit position 7 Bit name NP NMI Pending Function Indicates whether NMI interrupt servicing is in progress. 0: No NMI interrupt servicing 1: NMI interrupt currently being serviced 7.2.4 Edge detection function (1) External interrupt rising edge specification register 2 (INTR2), external interrupt falling edge specification register 2 (INTF2) These registers are used to specify the valid edge of the non-maskable interrupt (NMI). The NMIR0 bit of the INTR2 register and NMIF0 bit of the INTF2 register specify the rising edge, falling edge, or both the rising and falling edges of the NMI as the valid edge. These registers can be read or written in 8-bit or 1-bit units. 7 INTR2 0 6 0 5 INTR25 4 INTR24 3 INTR23 2 INTR22 1 INTR21 0 NMIR0 Address FFFFFC24H After reset 3FH INTF2 0 0 INTF25 INTF24 INTF23 INTF22 INTF21 NMIF0 FFFFFC04H 00H Bit position 0 Bit name NMIR0 (INTR2 register), NMIF0 (INTF2 register) Specify the NMI pin's valid edge. NMIF0 0 0 1 1 NMIR0 0 1 0 1 Falling edge Rising edge Function Operation Setting prohibited Both rising and falling edges Remark For bits 5 to 1, see 7.3.9 (2) External interrupt rising edge specification register 2 (INTR2), external interrupt falling edge specification register 2 (INTF2). 326 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850E/ME2 has 90 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which enables servicing of interrupt signals having a higher priority than the interrupt request signal in progress (specified by the interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. To enable multiple interrupt servicing, however, save EIPC and EIPSW to memory or registers before executing the EI instruction, and execute the DI instruction before the RETI instruction to restore EIPC and EIPSW to the original values. 7.3.1 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine: <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower halfword of ECR (EICC). <4> Sets the ID bit of the PSW to 1 and clears the EP bit of the PSW to 0. <5> Sets the handler address corresponding to each interrupt to the PC, and transfers control. The maskable interrupt request signal masked by the interrupt controller (INTC) and the maskable interrupt request signal generated while another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside the INTC. In this case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or the NP and ID bits are cleared to 0 by using the RETI or LDSR instruction. The servicing configuration of a maskable interrupt is shown in Figure 7-4. User's Manual U16031EJ4V1UD 327 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-4. Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 Yes xxMK = 0 Yes Priority higher than that of interrupt currently being serviced? No No Is the interrupt mask released? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request CPU processing PSW.NP 0 PSW.ID 0 EIPC EIPSW ECR.EICC PSW.EP PSW.ID Corresponding bit of ISPRNote PC Restored PC PSW Exception code 0 1 1 Handler address Interrupt request held pending 1 1 Interrupt request held pending Interrupt servicing Note For the ISPR register, see 7.3.7 In-service priority register (ISPR). 328 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1> Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0. <2> Transfers control to the address of the restored PC and PSW. Figure 7-5 illustrates the processing of the RETI instruction. Figure 7-5. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 PC PSW Corresponding bit of ISPRNote EIPC EIPSW 0 1 PC PSW FEPC FEPSW Restores original processing Note For the ISPR register, see 7.3.7 In-service priority register (ISPR). Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP and NP bits back to 0 using the LDSR instruction immediately before the RETI instruction. The solid line shows the CPU processing flow. Remark User's Manual U16031EJ4V1UD 329 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/ME2 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request signal type (default priority level) beforehand. For more information, see Table 7-1 Interrupt Source List. The programmable priority control customizes interrupt request signals into eight levels by setting the priority level specification flag. Note that when an interrupt request signal is acknowledged, the ID flag of PSW is automatically set to 1. Therefore, when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the interrupt service program) to set the interrupt enable mode. Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) 330 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a EI Interrupt request a (level 3) Interrupt request b (level 2) EI Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b Servicing of c Interrupt request c (level 3) Interrupt request d (level 2) Servicing of d Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Servicing of h Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to u in the figure are provisional interrupt request signal names shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. User's Manual U16031EJ4V1UD 331 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i EI EI Interrupt request j (level 3) Interrupt request k (level 1) Servicing of k Interrupt request i (level 2) Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Servicing of j Servicing of l Interrupt request m (level 3) Interrupt request n (level 1) Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request l (level 2) Servicing of n Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Servicing of m Interrupt request o (level 3) Interrupt request p (level 2) Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request q Interrupt (level 1) request r (level 0) If levels 3 to 0 are acknowledged Servicing of s Interrupt request t (level 2) Interrupt request u (level 2) Interrupt request s (level 1) Note 1 Note 2 Pending interrupt requests t and u are acknowledged after servicing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Servicing of u Servicing of t Notes 1. 2. Lower default priority Higher default priority Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. 332 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Servicing of interrupt request b . . Default priority a>b>c Servicing of interrupt request c Interrupt request b and c are acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first according to the default priority. Servicing of interrupt request a Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to c in the figure are provisional interrupt request signal names shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. User's Manual U16031EJ4V1UD 333 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Caution Disable interrupts (DI) to read the xxIFn bit of the xxICn register. If the xxIFn bit is read while interrupts are enabled (EI), the correct value may not be read if there is a conflict between acknowledging an interrupt and reading the bit. <7> <6> 5 0 4 0 3 0 2 xxPRn2 1 xxPRn1 0 xxPRn0 Address FFFFF110H to FFFFF1C2H After reset 47H xxICn xxIFn xxMKn Bit position 7 Bit name xxIFn This is an interrupt request flag. 0: Interrupt request signal not issued 1: Interrupt request signal issued Function The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged. 6 xxMKn This is an interrupt mask flag. 0: Interrupt servicing enabled 1: Interrupt servicing disabled (pending) 2 to 0 xxPRn2 to xxPRn0 8 levels of priority order are specified for each interrupt. xxPRn2 0 0 0 0 1 1 1 1 xxPRn1 0 0 1 1 0 0 1 1 xxPRn0 0 1 0 1 0 1 0 1 Interrupt priority specification bit Specifies level 0 (highest). Specifies level 1. Specifies level 2. Specifies level 3. Specifies level 4. Specifies level 5. Specifies level 6. Specifies level 7 (lowest). Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) The addresses and bits of the interrupt control registers are as follows: 334 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (1/3) Address Register <7> FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H FFFFF15AH FFFFF15CH FFFFF15EH FFFFF160H P1IC0 P1IC1 P2IC1 P2IC2 P2IC3 P2IC4 P2IC5 P5IC0 P5IC1 P5IC2 P6IC5 P6IC6 P6IC7 PDIC0 PDIC1 PDIC2 PDIC3 PDIC4 PDIC5 PDIC6 PDIC7 PDIC8 PDIC9 PDIC10 PDIC11 PDIC12 PDIC13 PDIC14 PDIC15 PLIC0 PLIC1 OVCIC0 OVCIC1 OVCIC2 OVCIC3 OVCIC4 OVCIC5 CCC0IC0 CCC0IC1 CCC1IC0 CCC1IC1 P1IF0 P1IF1 P2IF1 P2IF2 P2IF3 P2IF4 P2IF5 P5IF0 P5IF1 P5IF2 P6IF5 P6IF6 P6IF7 PDIF0 PDIF1 PDIF2 PDIF3 PDIF4 PDIF5 PDIF6 PDIF7 PDIF8 PDIF9 PDIF10 PDIF11 PDIF12 PDIF13 PDIF14 PDIF15 PLIF0 PLIF1 OVCIF0 OVCIF1 OVCIF2 OVCIF3 OVCIF4 OVCIF5 CCC0IF0 CCC0IF1 CCC1IF0 CCC1IF1 <6> P1MK0 P1MK1 P2MK1 P2MK2 P2MK3 P2MK4 P2MK5 P5MK0 P5MK1 P5MK2 P6MK5 P6MK6 P6MK7 PDMK0 PDMK1 PDMK2 PDMK3 PDMK4 PDMK5 PDMK6 PDMK7 PDMK8 PDMK9 PDMK10 PDMK11 PDMK12 PDMK13 PDMK14 PDMK15 PLMK0 PLMK1 OVCMK0 OVCMK1 OVCMK2 OVCMK3 OVCMK4 OVCMK5 CCC0MK0 CCC0MK1 CCC1MK0 CCC1MK1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 P1PR02 P1PR12 P2PR12 P2PR22 P2PR32 P2PR42 P2PR52 P5PR02 P5PR12 P5PR22 P6PR52 P6PR62 P6PR72 PDPR02 PDPR12 PDPR22 PDPR32 PDPR42 PDPR52 PDPR62 PDPR72 PDPR82 PDPR92 PDPR102 PDPR112 PDPR122 PDPR132 PDPR142 PDPR152 PLPR02 PLPR12 OVCPR02 OVCPR12 OVCPR22 OVCPR32 OVCPR42 OVCPR52 CCC0PR02 CCC0PR12 CCC1PR02 CCC1PR12 1 P1PR01 P1PR11 P2PR11 P2PR21 P2PR31 P2PR41 P2PR51 P5PR01 P5PR11 P5PR21 P6PR51 P6PR61 P6PR71 PDPR01 PDPR11 PDPR21 PDPR31 PDPR41 PDPR51 PDPR61 PDPR71 PDPR81 PDPR91 PDPR101 PDPR111 PDPR121 PDPR131 PDPR141 PDPR151 PLPR01 PLPR11 OVCPR01 OVCPR11 OVCPR21 OVCPR31 OVCPR41 OVCPR51 CCC0PR01 CCC0PR11 CCC1PR01 CCC1PR11 0 P1PR00 P1PR10 P2PR10 P2PR20 P2PR30 P2PR40 P2PR50 P5PR00 P5PR10 P5PR20 P6PR50 P6PR60 P6PR70 PDPR00 PDPR10 PDPR20 PDPR30 PDPR40 PDPR50 PDPR60 PDPR70 PDPR80 PDPR90 PDPR100 PDPR110 PDPR120 PDPR130 PDPR140 PDPR150 PLPR00 PLPR10 OVCPR00 OVCPR10 OVCPR20 OVCPR30 OVCPR40 OVCPR50 CCC0PR00 CCC0PR10 CCC1PR00 CCC1PR10 User's Manual U16031EJ4V1UD 335 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (2/3) Address Register <7> FFFFF162H FFFFF164H FFFFF166H FFFFF168H FFFFF16AH FFFFF16CH FFFFF16EH FFFFF170H FFFFF172H FFFFF174H FFFFF176H FFFFF178H FFFFF17AH FFFFF17CH FFFFF17EH FFFFF180H FFFFF182H FFFFF184H FFFFF186H FFFFF188H FFFFF18AH FFFFF18CH FFFFF18EH FFFFF190H FFFFF192H FFFFF194H FFFFF196H FFFFF198H FFFFF19AH FFFFF19CH FFFFF19EH FFFFF1A0H FFFFF1A2H FFFFF1A4H FFFFF1A6H FFFFF1A8H FFFFF1AAH FFFFF1ACH FFFFF1AEH FFFFF1B0H FFFFF1B2H CCC2IC0 CCC2IC1 CCC3IC0 CCC3IC1 CCC4IC0 CCC4IC1 CCC5IC0 CCC5IC1 CMDIC0 CMDIC1 CMDIC2 CMDIC3 CC10IC0 CC10IC1 CM10IC0 CM10IC1 OV1IC0 UD1IC0 CC11IC0 CC11IC1 CM11IC0 CM11IC1 OV1IC1 UD1IC1 DMAIC0 DMAIC1 DMAIC2 DMAIC3 CSI3IC0 CCC2IF0 CCC2IF1 CCC3IF0 CCC3IF1 CCC4IF0 CCC4IF1 CCC5IF0 CCC5IF1 CMDIF0 CMDIF1 CMDIF2 CMDIF3 CC10IF0 CC10IF1 CM10IF0 CM10IF1 OV1IF0 UD1IF0 CC11IF0 CC11IF1 CM11IF0 CM11IF1 OV1IF1 UD1IF1 DMAIF0 DMAIF1 DMAIF2 DMAIF3 CSI3IF0 <6> CCC2MK0 CCC2MK1 CCC3MK0 CCC3MK1 CCC4MK0 CCC4MK1 CCC5MK0 CCC5MK1 CMDMK0 CMDMK1 CMDMK2 CMDMK3 CC10MK0 CC10MK1 CM10MK0 CM10MK1 OV1MK0 UD1MK0 CC11MK0 CC11MK1 CM11MK0 CM11MK1 OV1MK1 UD1MK1 DMAMK0 DMAMK1 DMAMK2 DMAMK3 CSI3MK0 COVF3MK0 CSI3MK1 COVF3MK1 UREMK0 URMK0 UTMK0 UIFMK0 UTOMK0 UREMK1 URMK1 UTMK1 UIFMK1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 CCC2PR02 CCC2PR12 CCC3PR02 CCC3PR12 CCC4PR02 CCC4PR12 CCC5PR02 CCC5PR12 CMDPR02 CMDPR12 CMDPR22 CMDPR32 CC10PR02 CC10PR12 CM10PR02 CM10PR12 OV1PR02 UD1PR02 CC11PR02 CC11PR12 CM11PR02 CM11PR12 OV1PR12 UD1PR12 DMAPR02 DMAPR12 DMAPR22 DMAPR32 CSI3PR02 1 CCC2PR01 CCC2PR11 CCC3PR01 CCC3PR11 CCC4PR01 CCC4PR11 CCC5PR01 CCC5PR11 CMDPR01 CMDPR11 CMDPR21 CMDPR31 CC10PR01 CC10PR11 CM10PR01 CM10PR11 OV1PR01 UD1PR01 CC11PR01 CC11PR11 CM11PR01 CM11PR11 OV1PR11 UD1PR11 DMAPR01 DMAPR11 DMAPR21 DMAPR31 CSI3PR01 0 CCC2PR00 CCC2PR10 CCC3PR00 CCC3PR10 CCC4PR00 CCC4PR10 CCC5PR00 CCC5PR10 CMDPR00 CMDPR10 CMDPR20 CMDPR30 CC10PR00 CC10PR10 CM10PR00 CM10PR10 OV1PR00 UD1PR00 CC11PR00 CC11PR10 CM11PR00 CM11PR10 OV1PR10 UD1PR10 DMAPR00 DMAPR10 DMAPR20 DMAPR30 CSI3PR00 COVF3IC0 COVF3IF0 CSI3IC1 CSI3IF1 COVF3PR02 COVF3PR01 COVF3PR00 CSI3PR12 CSI3PR11 CSI3PR10 COVF3IC1 COVF3IF1 UREIC0 URIC0 UTIC0 UIFIC0 UTOIC0 UREIC1 URIC1 UTIC1 UIFIC1 UREIF0 URIF0 UTIF0 UIFIF0 UTOIF0 UREIF1 URIF1 UTIF1 UIFIF1 COVF3PR12 COVF3PR11 COVF3PR10 UREPR02 URPR02 UTPR02 UIFPR02 UTOPR02 UREPR12 URPR12 UTPR12 UIFPR12 UREPR01 URPR01 UTPR01 UIFPR01 UTOPR01 UREPR11 URPR11 UTPR11 UIFPR11 UREPR00 URPR00 UTPR00 UIFPR00 UTOPR00 UREPR10 URPR10 UTPR10 UIFPR10 336 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (3/3) Address Register <7> FFFFF1B4H FFFFF1B6H FFFFF1B8H FFFFF1BAH FFFFF1BCH FFFFF1BEH FFFFF1C0H FFFFF1C2H UTOIC1 ADIC US0BIC US1BIC US2BIC USP2IC USP4IC RSUMIC UTOIF1 ADIF US0BIF US1BIF US2BIF USP2IF USP4IF RSUMIF <6> UTOMK1 ADMK US0BMK US1BMK US2BMK USP2MK USP4MK RSUMMK 5 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 2 UTOPR12 ADPR2 US0BPR2 US1BPR2 US2BPR2 USP2PR2 USP4PR2 RSUMPR2 1 UTOPR11 ADPR1 US0BPR1 US1BPR1 US2BPR1 USP2PR1 USP4PR1 RSUMPR1 0 UTOPR10 ADPR0 US0BPR0 US1BPR0 US2BPR0 USP2PR0 USP4PR0 RSUMPR0 7.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR5 registers is equivalent to the xxMKn bit of the xxICn register. The IMRm register (m = 0 to 5) can be read or written in 16-bit units. If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register, these registers can be read or written in 8-bit or 1-bit units. Set bits 15 to 10 of the IMR5 register (bits 7 to 2 of the IMR5H register) to 1. If these bits are not 1, the operation cannot be guaranteed. Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit is manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm register, are rewritten (as a result, the contents of the IMRm register are also rewritten). User's Manual U16031EJ4V1UD 337 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15 IMR0 PDMK2 7 P5MK0 14 PDMK1 6 P2MK5 13 PDMK0 5 P2MK4 12 P6MK7 4 P2MK3 11 P6MK6 3 P2MK2 10 P6MK5 2 P2MK1 9 P5MK2 1 P1MK1 8 P5MK1 0 P1MK0 Address FFFFF100H After reset FFFFH 15 IMR1 OVCMK0 7 PDMK10 14 PLMK1 6 PDMK9 13 PLMK0 5 PDMK8 12 11 10 9 8 Address FFFFF102H After reset FFFFH PDMK15 PDMK14 PDMK13 PDMK12 PDMK11 4 PDMK7 3 PDMK6 2 PDMK5 1 PDMK4 0 PDMK3 15 14 13 12 11 10 9 8 Address FFFFF104H After reset FFFFH IMR2 CCC5MK0 CCC4MK1 CCC4MK0 CCC3MK1 CCC3MK0 CCC2MK1 CCC2MK0 CCC1MK1 7 6 5 4 3 2 1 0 CCC1MK0 CCC0MK1 CCC0MK0 OVCMK5 OVCMK4 OVCMK3 OVCMK2 OVCMK1 15 14 13 12 11 10 9 8 Address FFFFF106H After reset FFFFH IMR3 OV1MK1 CM11MK1 CM11MK0 CC11MK1 CC11MK0 UD1MK0 OV1MK0 CM10MK1 7 6 5 4 3 2 1 0 CM10MK0 CC10MK1 CC10MK0 CMDMK3 CMDMK2 CMDMK1 CMDMK0 CCC5MK1 15 IMR4 14 13 12 11 UTMK0 3 10 9 8 Address FFFFF108H After reset FFFFH URMK1 UREMK1 UTOMK0 UIFMK0 7 6 5 4 URMK0 UREMK0 COVF3MK1 2 1 0 CSI3MK1 COVF3MK0 CSI3MK0 DMAMK3 DMAMK2 DMAMK1 DMAMK0 UD1MK1 15 IMR5 1 7 14 1 6 13 1 5 12 1 4 11 1 3 ADMK 10 1 2 9 8 Address FFFFF10AH After reset FFFFH RSUMMK USP4MK 1 0 UTMK1 USP2MK US2BMK US1BMK US0BMK UTOMK1 UIFMK1 Bit position 15 to 0 Bit name xxMKn Interrupt mask flag 0: Interrupt servicing enabled Function 1: Interrupt servicing disabled (pending) Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) 338 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.6 NMI reset status register (NRS) This register holds the valid edge input status of the NMI after the reset signal has been cleared. This register is read-only, in 8-bit or 1-bit units. Cautions 1. The NMIRS bit of the NRS register is set to 1 if an NMI occurs after the internal instruction RAM has been set in the read mode (IRAMM0 bit of IRAMM register = 0). In this case, the status of the NMIRS bit does not have to be checked because execution automatically branches to the NMI servicing routine. 2. The mask function of NMI input is valid after the reset signal has been cleared and before the internal instruction RAM is set in the read mode (IRAMM0 bit of IRAMM register = 0). 7 6 0 5 0 4 0 3 0 2 0 1 0 0 NMIRS Address FFFFF80CH After reset 00H NRS 0 Bit position 0 Bit name NMIRS Function Indicates the valid edge input status of NMI. 0: No NMI input 1: NMI input With the V850E/ME2, the NMI is masked after the reset signal has been cleared. It is unmasked if the mode of the internal instruction RAM is changed from the write mode (IRAMM0 bit of IRAMM register = 1) to the read mode (IRAMM0 bit of IRAMM register = 0) after the program has been downloaded to internal instruction RAM bank 0. (The NRS register is controlled to prohibit a jump to the interrupt vector before the program is stored in the interrupt vector table.) If the NMI valid edge is input while the NMI is masked, the NMI input can be recognized by reading the NRS register. User's Manual U16031EJ4V1UD 339 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest priority is automatically cleared to 0 by hardware. However, it is not cleared to 0 when execution is returned from nonmaskable interrupt servicing or exception processing. This register is read-only, in 8-bit or 1-bit units. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set to 1 by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI status). <7> <6> <5> <4> <3> <2> <1> <0> Address FFFFF1FAH After reset 00H ISPR ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 Bit position 7 to 0 Bit name ISPR7 to ISPR0 Function Indicates priority of interrupt currently acknowledged 0: Interrupt request signal with priority n not acknowledged 1: Interrupt request signal with priority n acknowledged Remark n = 0 to 7 (priority level) 7.3.8 Maskable interrupt status flag (ID) The ID flag controls the maskable interrupt's operating state and stores control information regarding enabling or disabling of interrupt requests. The ID flag is allocated to the PSW. 31 PSW 876543210 After reset 00000020H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z Bit position 5 ID Bit name Function Indicates whether maskable interrupt servicing is enabled or disabled. 0: Maskable interrupt request signal acknowledgment enabled 1: Maskable interrupt request signal acknowledgment disabled (pending) This bit is set to 1 by the DI instruction and cleared to 0 by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When a maskable interrupt signal is acknowledged, the ID flag is automatically set to 1 by hardware. The interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) is acknowledged when the xxIFn bit of xxICn is set to 1, and the ID flag is cleared to 0. 340 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.9 Selecting interrupt trigger mode The valid edge of the INTPn, INTPCm, TIC0 to TIC3, INTPx, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11 pins can be selected by program (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, L0, L1, or D0 to D15, m = 00, 01, 10, 11, 20, 21, 30, or 31, x = 100, 101, 110, or 111). A trigger level can also be selected for the INTPn pin. The following valid edges can be selected. * Rising edge * Falling edge * Both rising and falling edges The INTPn, INTPCm, TIC0 to TIC3, INTPx, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11 signals detected by the edge are used as interrupt sources, to input a capture trigger, or to input an external count signal to the timers. The valid edge of these signals is specified by external interrupt rising edge specification registers 1, 2, 5, 6, AL, and DH (INTR1, INTR2, INTR5, INTR6, INTRAL, and INTRDH), external interrupt falling edge specification registers 1, 2, 5, 6, AL, and DH (INTF1, INTF2, INTF5, INTF6, INTFAL, and INTFDH), valid edge select registers C0 to C3 (SESC0 to SESC3), and valid edge select registers 10 and 11 (SESA10 and SESA11). The trigger level is specified by external interrupt rising edge specification registers 1, 2, 5, 6, AL, and DH (INTR1, INTR2, INTR5, INTR6, INTRAL, and INTRDH) and external interrupt falling edge specification registers 1, 2, 5, 6, AL, and DH (INTF1, INTF2, INTF5, INTF6, INTFAL, and INTFDH). (1) External interrupt rising edge specification register 1 (INTR1), external interrupt falling edge specification register 1 (INTF1) These registers are used to specify the trigger mode of the external interrupt requests (INTP10 and INTP11) input from external pins. The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTF10 and INTR10 bits: INTP10 * INTF11 and INTR11 bits: INTP11 The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge. Each of these registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC1 register before setting the trigger mode of the INTP10 and INTP11 pins. If the PMC1 register is set after the INTR1 and INTF1 registers have been set, an illegal interrupt may occur when the PMC1 register is set. User's Manual U16031EJ4V1UD 341 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7 INTR1 0 6 0 5 0 4 0 3 0 2 0 1 INTR11 0 INTR10 Address FFFFFC22H After reset 03H INTF1 0 0 0 0 0 0 INTF11 INTF10 FFFFFC02H 00H Bit position 1, 0 Bit name INTF1n, INTR1n (n = 0, 1) Function Specify the trigger mode of the INTP10 and INTP11 pins. INTF1n 0 0 1 1 INTR1n 0 1 0 1 Falling edge Rising edge Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Operation Notes 1. The level of the INTP1n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P1IFn bit (n = 0, 1). Consequently, even when the CPU acknowledges the interrupt and the P1IFn bit of the interrupt control register (P1ICn) is automatically cleared to 0, the P1IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP1n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P1IFn bit to 0. 2. If a level-detected interrupt request (INTP1n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP1n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP1n) is held pending (n = 0, 1). To not acknowledge the interrupt request of INTP1n, clear the P1IFn bit of the interrupt control register. 342 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt rising edge specification register 2 (INTR2), external interrupt falling edge specification register 2 (INTF2) These registers are used to specify the trigger mode of the external interrupt requests (INTP2n) input from external pins and the non-maskable interrupt (NMI) (n = 1 to 5). For the trigger mode of the NMI, see 7.2.4 (1) External interrupt rising edge specification register 2 (INTR2), external interrupt falling edge specification register 2 (INTF2). The correspondence between each bit and the external interrupt request and non-maskable interrupt that are controlled by that bit is as follows. * INTF21 and INTR21 bits: INTP21 * INTF22 and INTR22 bits: INTP22 * INTF23 and INTR23 bits: INTP23 * INTF24 and INTR24 bits: INTP24 * INTF25 and INTR25 bits: INTP25 The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge of the INTP2n pin. Each of these registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC2 register before setting the trigger mode of the INTP2n pin (n = 1 to 5). If the PMC2 register is set after the INTR2 and INTF2 registers have been set, an illegal interrupt may occur when the PMC2 register is set. User's Manual U16031EJ4V1UD 343 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7 INTR2 0 6 0 5 INTR25 4 INTR24 3 INTR23 2 INTR22 1 INTR21 0 NMIR0 Address FFFFFC24H After reset 3FH INTF2 0 0 INTF25 INTF24 INTF23 INTF22 INTF21 NMIF0 FFFFFC04H 00H Bit position 5 to 1 Bit name INTF2n, INTR2n (n = 1 to 5) Function Specify the trigger mode of the INTP2n pin. INTF2n 0 0 1 1 INTR2n 0 1 0 1 Falling edge Rising edge Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Operation Notes 1. The level of the INTP2n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P2IFn bit (n = 1 to 5). Consequently, even when the CPU acknowledges the interrupt and the P2IFn bit of the interrupt control register (P2ICn) is automatically cleared to 0, the P2IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP2n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P2IFn bit to 0. 2. If a level-detected interrupt request (INTP2n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP2n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP2n) is held pending (n = 1 to 5). To not acknowledge the interrupt request of INTP2n, clear the P2IFn bit of the interrupt control register. Remark For the bit 0 (NMIR0) of the INTR2 register and bit 0 (NMIF0) of the INTF2 register, see 7.2.4 (1) External interrupt rising edge specification register 2 (INTR2), external interrupt falling edge specification register 2 (INTF2). 344 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt rising edge specification register 5 (INTR5), external interrupt falling edge specification register 5 (INTF5) These registers are used to specify the trigger mode of the external interrupt requests (INTP5n) input from external pins (n = 0 to 2). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTF50 and INTR50 bits: INTP50 * INTF51 and INTR51 bits: INTP51 * INTF52 and INTR52 bits: INTP52 The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge. Each of these registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC5 register before setting the trigger mode. If the PMC5 register is set after the INTR5 and INTF5 registers have been set, an illegal interrupt may occur when the PMC5 register is set. User's Manual U16031EJ4V1UD 345 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7 INTR5 0 6 0 5 0 4 0 3 0 2 INTR52 1 INTR51 0 INTR50 Address FFFFFC2AH After reset 07H INTF5 0 0 0 0 0 INTF52 INTF51 INTF50 FFFFFC0AH 00H Bit position 2 to 0 Bit name INTF5n, INTR5n (n = 0 to 2) Function Specify the trigger mode of the INTP5n pin. INTF5n 0 0 1 1 INTR5n 0 1 0 1 Falling edge Rising edge Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Operation Notes 1. The level of the INTP5n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P5IFn bit (n = 0 to 2). Consequently, even when the CPU acknowledges the interrupt and the P5IFn bit of the interrupt control register (P5ICn) is automatically cleared to 0, the P5IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP5n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P5IFn bit to 0. 2. If a level-detected interrupt request (INTP5n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP5n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP5n) is held pending (n = 0 to 2). To not acknowledge the interrupt request of INTP5n, clear the P5IFn bit of the interrupt control register. 346 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) External interrupt rising edge specification register 6 (INTR6), external interrupt falling edge specification register 6 (INTF6) These registers are used to specify the trigger mode of the external interrupt requests (INTP6n) input from external pins (n = 5 to 7). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTF65 and INTR65 bits: INTP65 * INTF66 and INTR66 bits: INTP66 * INTF67 and INTR67 bits: INTP67 The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge. Each of these registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC6 register before setting the trigger mode. If the PMC6 register is set after the INTR6 and INTF6 registers have been set, an illegal interrupt may occur when the PMC6 register is set. User's Manual U16031EJ4V1UD 347 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7 INTR6 INTR67 6 INTR66 5 INTR65 4 0 3 0 2 0 1 0 0 0 Address FFFFFC2CH After reset E0H INTF6 INTF67 INTF66 INTF65 0 0 0 0 0 FFFFFC0CH 00H Bit position 7 to 5 Bit name INTF6n, INTR6n (n = 7 to 5) Function Specify the trigger mode of the INTP6n pin. INTF6n 0 0 1 1 INTR6n 0 1 0 1 Falling edge Rising edge Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Operation Notes 1. The level of the INTP6n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P6IFn bit (n = 5 to 7). Consequently, even when the CPU acknowledges the interrupt and the P6IFn bit of the interrupt control register (P6ICn) is automatically cleared to 0, the P6IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP6n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P6IFn bit to 0. 2. If a level-detected interrupt request (INTP6n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP6n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP6n) is held pending (n = 5 to 7). To not acknowledge the interrupt request of INTP6n, clear the P6IFn bit of the interrupt control register. 348 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (5) External interrupt rising edge specification register AL (INTRAL), external interrupt falling edge specification register AL (INTFAL) These registers are used to specify the trigger mode of the external interrupt requests (INTPLn) input from external pins (n = 0, 1). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTFAL0 and INTRAL0 bits: INTPL0 * INTFAL1 and INTRAL1 bits: INTPL1 The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge. Each of these registers can be read or written in 8-bit or 1-bit units. Caution Set the PMCAL register before setting the trigger mode. If the PMCAL register is set after the INTRAL and INTFAL registers have been set, an illegal interrupt may occur when the PMCAL register is set. 7 INTRAL 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFFC30H After reset 03H INTRAL1 INTRAL0 INTFAL 0 0 0 0 0 0 INTFAL1 INTFAL0 FFFFFC10H 00H Bit position 1, 0 Bit name INTFALn, INTRALn (n = 0, 1) Function Specify the trigger mode of the INTPLn pin. INTFALn 0 0 1 1 INTRALn 0 1 0 1 Falling edge Rising edge Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Operation Notes 1. The level of the INTPLn pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the PLIFn bit (n = 0, 1). Consequently, even when the CPU acknowledges the interrupt and the PLIFn bit of the interrupt control register (PLICn) is automatically cleared to 0, the PLIFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTPLn pin of the external device inactive in the interrupt servicing routine, and forcibly clear the PLIFn bit to 0. 2. If a level-detected interrupt request (INTPLn) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTPLn) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTPLn) is held pending (n = 0, 1). To not acknowledge the interrupt request of INTPLn, clear the PLIFn bit of the interrupt control register. User's Manual U16031EJ4V1UD 349 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (6) External interrupt rising edge specification register DH (INTRDH), external interrupt falling edge specification register DH (INTFDH) These registers are used to specify the trigger mode of the external interrupt requests (INTPDn) input from external pins (n = 0 to 15). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTFDH0 and INTRDH0 bits: INTPD0 * INTFDH1 and INTRDH1 bits: INTPD1 * INTFDH2 and INTRDH2 bits: INTPD2 * INTFDH3 and INTRDH3 bits: INTPD3 * INTFDH4 and INTRDH4 bits: INTPD4 * INTFDH5 and INTRDH5 bits: INTPD5 * INTFDH6 and INTRDH6 bits: INTPD6 * INTFDH7 and INTRDH7 bits: INTPD7 * INTFDH8 and INTRDH8 bits: * INTFDH9 and INTRDH9 bits: INTPD8 INTPD9 * INTFDH10 and INTRDH10 bits: INTPD10 * INTFDH11 and INTRDH11 bits: INTPD11 * INTFDH12 and INTRDH12 bits: INTPD12 * INTFDH13 and INTRDH13 bits: INTPD13 * INTFDH14 and INTRDH14 bits: INTPD14 * INTFDH15 and INTRDH15 bits: INTPD15 The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge. The INTRDH and INTFDH registers can be read or written in 16-bit units. If the higher 8 bits of the INTRDH and INTFDH registers are used as the INTRDHH and INTFDHH registers, and the lower 8 bits as the INTRDHL and INTFDHL registers, these registers can be read or written in 8-bit or 1-bit units. Caution Set the PMCDH register before setting the trigger mode. If the PMCDH register is set after the INTRDH and INTFDH registers have been set, an illegal interrupt may occur when the PMCDH register is set. 350 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFC36H After reset FFFFH INTRDH INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR DH15 DH14 DH13 DH12 DH11 DH10 DH9 DH8 DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0 INTFDH INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF DH15 DH14 DH13 DH12 DH11 DH10 DH9 DH8 DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0 FFFFFC16H 0000H Bit position 15 to 0 Bit name INTFDHn, INTRDHn (n = 0 to 15) Function Specify the trigger mode of the INTPDn pin. INTFDHn 0 0 1 1 INTRDHn 0 1 0 1 Falling edge Rising edge Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Operation Notes 1. The level of the INTPDn pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the PDIFn bit (n = 0 to 15). Consequently, even when the CPU acknowledges the interrupt and the PDIFn bit of the interrupt control register (PDICn) is automatically cleared to 0, the PDIFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTPDn pin of the external device inactive in the interrupt servicing routine, and forcibly clear the PDIFn bit to 0. 2. If a level-detected interrupt request (INTPDn) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTPDn) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTPDn) is held pending (n = 0 to 15). To not acknowledge the interrupt request of INTPDn, clear the PDIFn bit of the interrupt control register. User's Manual U16031EJ4V1UD 351 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (7) Valid edge select registers C0 to C3 (SESC0 to SESC3) These registers are used to specify the valid edge of the external interrupt requests (INTPC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, INTPC31, or TIC0 to TIC3) input from external pins to TMCn (n = 0 to 3). The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge. Each of these registers can be read or written in 8-bit units. Be sure to clear bits 5 and 4 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. Do not change each bit of the SESCn register while the timer is operating (n = 0 to 3). To change a bit, clear the CECn bit of the TMCCn0 register to 0. The operation is not guaranteed if the SESCn register is rewritten during timer operation. 2. Even when the INTPC00/TIC0, INTPC10/TIC1, INTPC20/TIC2, and INTPC30/TIC3 pins are used as INTPC00, INTPC10, INTPC20, and INTPC30, respectively, without using timer C, be sure to set the CAECn and CECn bits of timer mode control registers C00 to C03 (TMCC00 to TMCC30) to 1. 3. Set the PMCx register before setting the trigger mode of the INTPC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, INTPC31, and TIC0 to TIC3 pins (x = 5 to 7), then set the CAECn and CECn bits of the TMCCn0 register to 1 (n = 0 to 3). If the PMCx register is set after the SESCn register has been set, an illegal interrupt, incorrect count, or incorrect clear may occur depending on the timing of setting the PMCx register (n = 0 to 3, x = 5 to 7). 352 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7 SESC0 TESC01 6 TESC00 5 0 4 0 3 2 1 0 Address FFFFF609H After reset 00H IESC101 IESC100 IESC001 IESC000 INTPC01 INTPC00 2 1 0 TIC0 7 SESC1 TESC11 6 TESC10 5 0 4 0 3 Address FFFFF629H After reset 00H IESC111 IESC110 IESC011 IESC010 INTPC11 INTPC10 2 1 0 TIC1 7 SESC2 TESC21 6 TESC20 5 0 4 0 3 Address FFFFF649H After reset 00H IESC121 IESC120 IESC021 IESC020 INTPC21 INTPC20 2 1 0 TIC2 7 SESC3 TESC31 6 TESC30 5 0 4 0 3 Address FFFFF669H After reset 00H IESC131 IESC130 IESC031 IESC030 INTPC31 INTPC30 TIC3 Bit position 7, 6 Bit name TESCn1, TESCn0 (n = 0 to 3) xESCn1 xESCn0 0 1 0 1 Falling edge Rising edge Function Specify the valid edge of the INTPCm0, INTPCm1, and TICm pins (m = 0 to 3). Operation 3, 2 IESCn1, IESCn0 (n = 10 to 13) 0 0 1 Setting prohibited Both rising and falling edges 1, 0 IESCn1, IESCn0 (n = 00 to 03) 1 User's Manual U16031EJ4V1UD 353 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (8) Valid edge select registers 10, 11 (SESA10, SESA11) These registers are used to specify the valid edge of the external interrupt requests (TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, or TCLR11) input from external pins and the external capture trigger inputs to timer ENC1 (INTP100, INTP101, INTP110, or INTP111). The rising edge, falling edge, or both the rising and falling edges can be independently specified as the valid edge. Each of these registers can be read or written in 8-bit or 1-bit units. Cautions 1. Changing each bit of the SESA1n register is prohibited while TMENC1n is operating (CE1n1 bit = 1). 2. Set the PMCDH register before setting the trigger mode of the INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11 pins. If the PMCDH register is set after the SESA1n register has been set, an illegal interrupt, incorrect count, or incorrect clear may occur depending on the timing of setting the PMCDH register. (1/2) 7 6 5 4 3 2 IES100 1 IES001 0 IES000 Address FFFFF5ADH After reset 00H SESA10 TESUD01 TESUD00 CESUD01 CESUD00 IES101 TIUD10, TCUD10 TCLR10 INTP101 INTP100 7 6 5 4 3 2 IES110 1 IES011 0 IES010 Address FFFFF5DDH After reset 00H SESA11 TESUD11 TESUD10 CESUD11 CESUD10 IES111 TIUD11, TCUD11 TCLR11 INTP111 INTP110 Bit position 7, 6 Bit name TESUDn1, TESUDn0 Function Specify the valid edge of the TIUD1n and TCUD1n pins. TESUDn1 0 0 1 1 TESUDn0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge Cautions 1. The set values of the TESUDn1 and TESUDn0 bits are valid only in UDC mode A and UDC mode B. 2. If mode 4 is specified for the operation of TMENC1n (specified by the PRM1n2 to PRM1n0 bits of the PRM1n register), specifying the valid edge for the TIUD1n and TCUD1n pins (TESUDn1 and TESUDn0 bits) is invalid. Remark n = 0, 1 354 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit position 5, 4 Bit name CESUDn1, CESUDn0 Function Specify the valid edge of the TCLR1n pin. CESUDn1 0 0 1 1 CESUDn0 0 1 0 1 Falling edge Rising edge Low-level High-level Valid edge The relationship between the set values of the CESUDn1 and CESUDn0 bits and the operation of TMENC1n is as follows. 00: TMENC1n cleared after the rising edge of TCLR1n has been detected. 01: TMENC1n cleared after the falling edge of TCLR1n has been detected. 10: TMENC1n stays cleared while TCLR1n input is low. 11: TMENC1n stays cleared while TCLR1n input is high. Caution The set values of the CESUDn1 and CESUDn0 bits are valid only in UDC mode A. 3, 2 IES1n1, IES1n0 Specify the valid edge of the INTP1n1 pin. IES1n1 0 0 1 1 IES1n0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge 1, 0 IES0n1, IES0n0 Specify the valid edge of the INTP1n0 pin. IES0n1 0 0 1 1 IES0n0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge Remark n = 0, 1 User's Manual U16031EJ4V1UD 355 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the EP and ID bits of the PSW to 1. <5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC, and transfers control. Figure 7-8 illustrates the processing of a software exception. Figure 7-8. Software Exception Processing TRAP instructionNote CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restored PC PSW Exception code 1 1 Handler address Exception processing Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.) The handler address is determined by the TRAP instruction's operand (vector). If the vector is 00H to 0FH, it becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H. 356 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC's address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. <2> Transfers control to the address of the restored PC and PSW. Figure 7-9 illustrates the processing of the RETI instruction. Figure 7-9. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the software exception processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP and NP bits back to 0 using the LDSR instruction immediately before the RETI instruction. The solid line shows the CPU processing flow. Remark User's Manual U16031EJ4V1UD 357 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is a status flag used to indicate that exception processing is in progress. It is set to 1 when an exception occurs. The EP flag is allocated to the PSW. 31 PSW 876543210 After reset 00000020H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z Bit position 6 Bit name EP Function Shows that exception processing is in progress. 0: Exception processing not in progress. 1: Exception processing in progress. 358 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850E/ME2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B. instruction is executed. An exception trap is generated when an instruction applicable to this illegal 15 11 10 54 0 31 27 26 23 22 16 xxxxx x: Arbitrary 111111 xxxxxxxxxx 0111 to 1111 xxxxxx 0 Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine: <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the NP, EP, and ID bits of the PSW to 1. <4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control. Figure 7-10 illustrates the processing of the exception trap. User's Manual U16031EJ4V1UD 359 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the address indicated by the restored PC and PSW. Figure 7-11 illustrates the restore processing from an exception trap. Figure 7-11. Restore Processing from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 360 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the NP, EP and ID bits of the PSW to 1. <4> Sets the handler address (00000060H) corresponding to the debug trap to the PC and transfers control. Figure 7-12 illustrates the processing of the debug trap. Figure 7-12. Debug Trap Processing DBTRAP instruction CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Debug monitor routine processing User's Manual U16031EJ4V1UD 361 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the address indicated by the restored PC and PSW. Caution DBPC and DBPSW can be accessed during the period between when the DBTRAP instruction is executed and when the DBRET instruction is executed. Figure 7-13 illustrates the restore processing from a debug trap. Figure 7-13. Restore Processing from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 362 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request signal with a higher priority level, and the higher priority interrupt request signal is acknowledged and serviced first. If there is an interrupt request signal with a lower priority level than the interrupt request currently being serviced, that interrupt request signal is held pending. Multiple interrupt servicing control of maskable interrupts is executed when interrupts are enabled (ID bit of PSW = 0). Thus, to execute multiple interrupts, it is necessary to set the interrupt enabled state (ID bit = 0) even for an interrupt service routine. If maskable interrupts are enabled or a software exception is generated in a maskable interrupt or software exception service program, it is necessary to save EIPC and EIPSW. This is accomplished by the following procedure. (1) Acknowledgment of maskable interrupt request signals in service program Service program of maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register * EI instruction (interrupt acknowledgment enabled) ... ... ... ... * DI instruction (interrupt acknowledgment disabled) * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Maskable interrupt acknowledgment User's Manual U16031EJ4V1UD 363 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in service program Service program of maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register ... * TRAP instruction ... * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Exception such as TRAP instruction acknowledged. The priority order for multiple interrupt servicing control has 8 levels, from 0 to 7 for each maskable interrupt request signal (0 is the highest priority), but it can be set as desired via software. The priority order is set using the xxPRn0 to xxPRn2 bits of the interrupt control request register (xxlCn), provided for each maskable interrupt request signal. After system reset, an interrupt request signal is masked by the xxMKn bit and the priority order is set to level 7 by the xxPRn0 to xxPRn2 bits. The priority order of maskable interrupts is as follows. (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low) Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the servicing of the higher priority interrupt has been completed and the RETI instruction has been executed. A pending interrupt request signal is acknowledged after the current interrupt servicing has been completed and the RETI instruction has been executed. Caution In a non-maskable interrupt servicing routine (time until the RETI instruction is executed), maskable interrupts are held pending and not acknowledged. Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) 364 User's Manual U16031EJ4V1UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.7 Interrupt Latency Time The V850E/ME2 interrupt latency time (from interrupt request generation to start of interrupt servicing) is described below. Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgment (Outline) 4 system clocks Internal clock Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM WB IFX IDX INT1 INT2 INT3 INT4 IF ID EX Remark INT1 to INT4: Interrupt acknowledgment processing IFX: IDX: Invalid instruction fetch Invalid instruction decode Condition Interrupt latency (internal system clock (fCLK)) Internal interrupt Minimum 4 External interrupt INTPm 7+ Digital delay time Note INTPn 4+ Analog delay time The following cases are exceptions. * In IDLE/software STOP mode * External bus access * Two or more interrupt request non-sample instructions are executed in succession * Access to on-chip peripheral I/O register Maximum 6 9+ Digital delay time 6+ Analog delay time Note The interrupt latency is the maximum value when executing any of the following instructions. DIV instruction, PREPARE instruction, DISPOSE instruction, SWITCH instruction, SET1 instruction, CLR1 instruction, NOT1 instruction, LD instruction for internal instruction RAM, misalign access Remark m = C00, C01, C10, C11, C20, C21, C30, C31 n = 10, 11, 21 to 25, 50 to 52, 65 to 67, L0, L1, D0 to D15 User's Manual U16031EJ4V1UD 365 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which CPU Does Not Acknowledge Interrupts However, no interrupt will be The CPU acknowledges an interrupt while an instruction is being executed. The interrupt request non-sample instructions are as follows. * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (for PSW) * The store instruction for the command register (PRCMD) acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). * The store and bit manipulation instructions of SET1, NOT1, and CLR1 for the following registers. * Interrupt-related registers: Interrupt control register (xxICn), interrupt mask registers 0 to 5 (IMR0 to IMR5), * Power-save control register (PSC) Remark xx: Identification name of each peripheral unit (see Table 7-2) n: Peripheral unit number (see Table 7-2) 7.9 Cautions Cautions concerning the interrupt/exception processing function are shown below. (1) Setting trigger mode of INTPn pin Set the PMCm register before setting the trigger mode of the INTPn pin. If the PMCm register is set after the INTRm and INTFm registers have been set, an illegal interrupt may occur when the PMCm register is set (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, L0, L1, D0 to D15, m = 1, 2, 5, 6, AL, DH). (2) Multiple interrupt servicing control In a non-maskable interrupt servicing routine (time until the RETI instruction is executed), maskable interrupts are held pending and not acknowledged. 366 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION The clock generator (CG) consists of a spread spectrum frequency synthesizer phase locked loop (SSCG) and a divider circuit, and generates and controls the clock supplied to the internal units as well as the CPU. The SSCG is a spread spectrum clock generator used to suppress noise, and is effective in reducing the peak value of electromagnetic interference (EMI) noise. 8.1 Features * SSCG output is used fixed to x8. * Selection of SSCG output by PLLSEL pin Set the PLLSEL pin as follows according to the value of fX = Input frequency to X1 and X2 pins (FX) x 8 PLLSEL Pin 0 1 SSCG Output (fX) 96 MHz fX 150 MHz 80 MHz fX < 96 MHz * Selection of frequency modulation rate (fDIT) of SSCG output The following two setting methods are available. * Selection by JIT0 and JIT1 pins (without modulation (frequency fixed), -1%, -3%, -5%) * Selection by SSCGC register (without modulation (frequency fixed), -0.5%, -1%, -2%, -3%, -4%, -5%) * MDL-Selector Table (modulation period) Selection by SSCGC register (13 to 27 kHz, 23 to 37 kHz, 32 to 48 kHz) * Division function by register setting (1/1, 1/2, 1/4, 1/8) * Clock sources Oscillation by connecting a resonator * Operation mode selection by register setting The clock to be supplied to each unit is selected from the following by register setting. * Clock output by SSCG * Clock from OSC without passing through SSCG * USB-dedicated clock input * Power-save control * HALT mode * IDLE mode * Software STOP mode User's Manual U16031EJ4V1UD 367 CHAPTER 8 CLOCK GENERATION FUNCTION 8.2 Configuration OSTS2 OSTS1 LOCK Lock register (LOCKR) Oscillation stabilization time select register (OSTS) OSTS0 PLL lock (lockup time) CKSSEL PLLSEL JIT1 JIT0 SSEL1 SSEL0 Selector Clock source select register (CKS) CKDIV1 CKDIV0 Clock control register (CKC) IDLE Main fX, fX/2, IDLE clock Divider fX/4, fX/8 control fX 1 fCLK CKM1 CKM0 Bus mode control register (BMC) HALT HALT control Internal system clock X1 X2 OSC FX SSCG FX x 8 Divider 2 Bus clock (BUSCLK) Prescaler Clock to peripheral function IDLE FU STOP UCK USB dedicated clock control 48 MHz STOP IDLE control UCKCNT USB clock control register (UCKC) fUSB 48 MHz Clock to USB Remark Be sure to set the USB clock to 48 MHz. 8.3 Control Registers 8.3.1 Clock control register (CKC) The clock control register is an 8-bit register that controls the internal system clock (fCLK) in PLL mode. It can be written to only by a specific sequence so that it cannot easily be overwritten by mistake due to an inadvertent program loop. This register can be read or written in 8-bit units. Be sure to clear bits 7 to 2 to 0. If they are set to 1, the operation is not guaranteed. 368 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION (1/2) 7 CKC 0 6 0 5 0 4 0 3 0 2 0 1 CKDIV1 0 CKDIV0 Address FFFFF822H After reset 03H Bit position 1, 0 Bit name CKDIV1, CKDIV0 Function Sets the internal system clock (fCLK) when PLL mode is used. CKDIV1 0 0 1 1 CKDIV0 0 1 0 1 fX/8 fX/4 fX/2 fX Internal system clock (fCLK) To change the internal system clock frequency in the middle of an operation, be sure to set it to fX first, and then change the frequency as desired. Remark fX: Main clock Cautions 1. Note that if the internal system clock (fCLK) is changed, the frequency of the bus clock (BUSCLK) is also changed. 2. If it necessary to change the refresh interval of the SDRAM as a result of changing the internal system clock (fCLK), follow this procedure. <1> Mask all interrupts. Disable DMA operations. For how to disable maskable interrupts, refer to the description of interrupt mask registers 0 to 5 (IMR0 to IMR5) (7.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5)). For how to disable non-maskable interrupts, disable multiple interrupts by setting the NP bit of the PSW to 1 (see 3.2.2 (4) Program status word (PSW)). <2> <3> <4> <5> <6> <7> <8> Clear the MEa bit of the BCTm register to 0. Clear the RENn bit of the RFSn register to 0 (n = 1, 3, 4, or 6). Change the values of the CKDIV0 and CKDIV1 bits of the CKC register (see 8.3.1 (2) Setting data to clock control register (CKC) for how to change the values). Set the MEa bit of the BCTm register to 1. Set a new refresh interval to the RFSn register, and clear the RENn bit to 0 (n = 1, 3, 4, or 6). Write the same value currently set to the SCRn register to the SCRn register (n = 1, 3, 4, or 6). Confirm that the WCFn bit of the SCRn register is set to 1, then set the RENn bit of the RFSn register to 1. Do not change any other bits except for the RENn bit (n = 1, 3, 4, or 6). <9> Enable DMA operations as necessary. <10> Access SDRAM. Remarks 1. fX: Main clock 2. a = 0 to 3 when m = 0 a = 4 to 7 when m = 1 User's Manual U16031EJ4V1UD 369 CHAPTER 8 CLOCK GENERATION FUNCTION (2/2) To change the refresh interval, set a value at which refresh can be made in time even while the interval is changed (see 8.3.1 (1) Notes on changing refresh interval). If the refresh interval is correctly secured with the interrupt servicing time taken into consideration, the processing in <1> above may be skipped. The RFSn and BCTm registers are prohibited from being rewritten, but they can be rewritten when the refreshing interval is re-set by changing the value of the CKC register. A register setting cycle of SDRAM is generated as a result of rewriting the SCRn register (processing in <6> above), but the value of SDRAM before the RFSn and SCRn registers are re-set is retained. 370 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION (1) Notes on changing refresh interval Figure 8-1 shows the internal state and the external bus state when the refresh interval is changed when the SDRAM is connected to the CS1 and CS3 areas. In such a case, the SDRAM that is connected to CS1 is not refreshed during a <1> and <3> period, and the SDRAM that is connected to CS3 is not refreshed during a <2> period. The time for <1> may be increased or decreased depending on factors such as the use status of the internal system bus or a bus hold request from the external bus. Moreover, the time for <2> and <3> may be increased or decreased depending on the value set to the RFSn register. When changing the refresh interval, therefore, the value must be set by making allowances for periods <1> to <3> in which a refresh is not performed. When the SDRAM is connected to only one CS area, the refresh interval value must be changed by making allowances for period <1>. Cautions 1. The refresh command is issued eight times in the register setting cycle regardless of the setting of the RENn bit of the RFSn register. 2. The REFRQ signal does not operate while the RENn bit is set to 0, so care must be exercised when the external bus master references the REFRQ signal. 3. Input to the SELFREF signal is ignored while the MEa bit of the BCTm register is set to 0, so the operation does not shift to the self-refresh state. Remarks 1. n = 1, 3, 4, or 6 2. a = 0 to 3 when m = 0 a = 4 to 7 when m = 1 Figure 8-1. Internal State and External Bus State When Refresh Interval Is Changed BUSCLK Internal register access signal SCR1 register changed RFS1/RFS3 register changed (refresh disabled) External bus cycle <1> <2> SCR3 register changed RFS1/RFS3 register changed (refresh enabled) SDRAM register setting cycle of CS1 SDRAM register setting cycle of CS3 <3> User's Manual U16031EJ4V1UD 371 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Setting data to clock control register (CKC) Set data to the CKC register in the following sequence. <1> Disable interrupts (set the NP bit of PSW to 1). <2> Prepare data in any one of the general-purpose registers to set in the specific register. <3> Write data to the command register (PRCMD). <4> Set the clock control register (CKC) (with the following instruction). * Store instruction (ST/SST instruction) <5> Insert the NOP instructions (5 instructions (<5> to <9>)). <10> Release the interrupt disabled state (clear the NP bit of PSW to 0). [Sample coding] <1> LDSR <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP <10> LDSR Remark rY, 5 rX, 5 0x02, r10 r10, PRCMD[r0] r10, CKC[r0] rX: Value written to PSW rY: Value returned to PSW No special sequence is required to read the specific register. Cautions 1. If an interrupt is acknowledged between the issuance of data to the PRCMD (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed. Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment. Also disable interrupt acknowledgment when selecting a bit manipulation instruction for the specific register setting. 2. Although the data written to the PRCMD register is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the PRCMD register (<3>). The same method should be applied when using a generalpurpose register for addressing. 3. Be sure to terminate all DMA transfers prior to the execution of the above sequence. 372 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.2 Clock source select register (CKS) This 8-bit register controls supply of the main clock (fX). It can be written to only by a specific sequence so that it cannot easily be overwritten by mistake due to an inadvertent program loop. This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 7 to 1 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. With the V850E/ME2, it is not assumed that the CPU operates with the OSC output always supplied as the main clock (CKSSEL bit = 0). Therefore, be sure to confirm in the initialization sequence that the LOCK bit of the LOCKR register is 0, and then supply the main clock from the SSCG output (CKSSEL bit = 1); otherwise the operation will not be guaranteed. 2. If the software STOP mode is released by a non-maskable interrupt request (NMI) or an unmasked maskable interrupt request, the system operates on the SSCG output clock after PLL frequency stabilization time (about 2 ms) after the count time (oscillation stabilization time set by the OSTS register) of the time base counter (TBC) has elapsed. Therefore, it is not necessary to re-set the CKS register. If the software STOP mode is released by RESET pin input, set the CKS register in accordance with the initialization sequence (see 3.4.10 Initialization sequence). 7 CKS 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> Address FFFFF82CH After reset 00H CKSSEL Bit position 0 Bit name CKSSEL Controls supply of the main clock (fX). 0: OSC output clock (FX) 1: SSCG output clock (FX x 8) Function User's Manual U16031EJ4V1UD 373 CHAPTER 8 CLOCK GENERATION FUNCTION Set data in the clock source select register (CKS) in the following sequence. <1> <2> <3> <4> <5> Disable interrupts (set the NP bit of PSW to 1). Prepare data in any one of the general-purpose registers to set in the specific register. Write data to the command register (PRCMD). Set the clock source select register (CKS) (with the following instruction). * Store instruction (ST/SST instruction) Insert the NOP instructions (5 instructions (<5> to <9>)). <10> Release the interrupt disabled state (clear the NP bit of PSW to 0). [Sample coding] <1> LDSR <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP <10> LDSR Remark rX: Value written to PSW rY: Value returned to PSW No special sequence is required to read the specific register. Cautions 1. If an interrupt is acknowledged between the issuance of data to the PRCMD (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed. Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment. Also disable interrupt acknowledgment when selecting a bit manipulation instruction for the specific register setting. 2. Although the data written to the PRCMD register is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the PRCMD register (<3>). The same method should be applied when using a general-purpose register for addressing. 3. Be sure to terminate all DMA transfers prior to the execution of the above sequence. rY, 5 rX, 5 0x01, r10 r10, PRCMD[r0] r10, CKS[r0] 374 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.3 SSCG control register (SSCGC) This is an 8-bit register that controls the frequency modulation rate and modulation period of SSCG output. It modulates the frequency by the frequency modulation rate (Down Spread) set by the ADJ2 to ADJ0 bits within the modulation period set by the SMDLn bit. This is effective in reducing the peak value of EMI noise. It can be written to only by a specific sequence so that it cannot easily be overwritten by mistake due to an inadvertent program loop. This register can be read or written in 8-bit units. Caution The SSCGC register can be set only when OSC output is supplied as the main clock (CKSSEL bit of CKS register = 0). If the setting of the SSCGC register is changed, the SSCG is unlocked (LOCK bit of LOCKR register = 1). Be sure to confirm that the LOCK bit = 0 before starting to supply SSCG output as the main clock (CKSSEL bit = 1); otherwise the operation will not be guaranteed. (1/2) 7 SSCGC 0 6 0 5 SMDL1 4 SMDL0 3 ADJON 2 ADJ2 1 ADJ1 0 ADJ0 Address FFFFF836H After reset Note Note The default value is as follows. SMDL1 bit = 0, SMDL0 bit = 1 The ADJON and ADJ2 to ADJ0 bits are set as follows by the JIT1 and JIT0 pins. JIT1 pin JIT0 pin ADJON bit 0 0 1 1 0 1 0 1 0 1 1 1 ADJ2 bit 0 0 0 1 Reset value ADJ1 bit 0 0 1 0 ADJ0 bit 0 1 1 1 Bit position 5, 4 Bit name SMDL1, SMDL0 Function Set the modulation period of SSCG output. SMDL1 0 0 1 1 SMDL0 0 1 0 1 Modulation period of SSCG output 13 to 27 kHz 23 to 37 kHz 32 to 48 kHz Setting prohibited User's Manual U16031EJ4V1UD 375 CHAPTER 8 CLOCK GENERATION FUNCTION (2/2) Bit position 3 to 0 Bit name ADJON, ADJ2 to ADJ0 Function Set the frequency modulation rate of SSCG output. ADJON ADJ2 ADJ1 ADJ0 Frequency modulation rate of SSCG output Min. 0 1 1 1 1 1 1 x 0 0 0 0 1 1 x 0 0 1 1 0 0 x 0 1 0 1 0 1 Typ. Max. No modulation (frequency fixed) -0.31% -0.67% -1.23% -1.74% -2.48% -3.27% -0.50% -1.00% -2.00% -3.00% -4.00% -5.00% -1.28% -1.75% -3.10% -4.33% -5.83% -7.28% Other than above Setting prohibited Cautions 1. If the frequency modulation rate of SSCG output is set to other than "No modulation (frequency fixed)" (ADJON bit = 0), the internal system clock (fCLK), bus clock (BUSCLK), and clock supplied to the on-chip peripheral functions all operate at the frequency that accords with the frequency modulation rate set by the ADJ2 to ADJ0 bits (see 8.5 Operating Clock Provisions). Therefore, thoroughly evaluate and confirm the system. 2. An overshoot/undershoot of the frequency modulation rate occurs. Set data in the SSCG control register (SSCGC) in the following sequence. <1> <2> <3> <4> <5> Disable interrupts (set the NP bit of PSW to 1). Prepare data in any one of the general-purpose registers to set in the specific register. Write data to the command register (PRCMD). Set the SSCG control register (SSCGC) (with the following instruction). * Store instruction (ST/SST instruction) Insert the NOP instructions (5 instructions (<5> to <9>)). <10> Release the interrupt disabled state (clear the NP bit of PSW to 0). [Sample coding] <1> LDSR <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP <10> LDSR rY, 5 rX, 5 0x08, r10 r10, PRCMD[r0] r10, SSCGC[r0] 376 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Remark rX: Value written to PSW rY: Value returned to PSW No special sequence is required to read the specific register. Cautions 1. If an interrupt is acknowledged between the issuance of data to the PRCMD (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed. Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment. Also disable interrupt acknowledgment when selecting a bit manipulation instruction for the specific register setting. 2. Although the data written to the PRCMD register is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the PRCMD register (<3>). The same method should be applied when using a general-purpose register for addressing. 3. Be sure to terminate all DMA transfers prior to the execution of the above sequence. 8.3.4 USB clock control register (UCKC) This register is used to select the clock source of the USB clock. Be sure to input fUSB at 48 MHz. This register can be read or written in 8-bit or 1-bit units. Be sure to clear the bits of this register other than bit 7 to 0. If they are set to 1, the operation is not guaranteed. Caution When using the USB function, be sure to set (1) the UCKCNT bit. If the registers related to the USB function are read while the UCKCNT bit is 0, 0 is read. <7> 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFF82EH After reset 00H UCKC UCKCNT Bit position 7 Bit name UCKCNT Controls clock supply to USB. 0: Stops clock supply to USB. 1: Supplies clock to USB. Function User's Manual U16031EJ4V1UD 377 CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.5 Lock register (LOCKR) The lockup time (frequency stabilization time: approx. 2 ms) is the time from when the power is turned on or software STOP mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called the lockup state, and the stabilized state is called the locked state. The lock register (LOCKR) has a LOCK flag that indicates that the PLL is in the lock wait state. This register is read-only, in 8-bit or 1-bit units. Caution If the phase is locked, the LOCK flag is cleared to 0. If it is unlocked later because of a standby status, writing to SSCGC register, or RESET input, the LOCK flag is set to 1. If the phase is unlocked by a cause other than these, however, the LOCK flag is not affected (LOCK = 0). 7 LOCKR 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> Address FFFFF824H After reset 01H LOCK Bit position 0 Bit name LOCK Function This is a read-only flag that indicates the PLL lock wait state. This flag holds the value 0 as long as a lockup state is maintained. 0: Indicates that the PLL is locked. 1: Indicates that the PLL is waiting to be locked (unlock state). If some other factor operates to cause an unlock state to occur, for control processing that depends on software execution speed, such as real-time processing, be sure to judge the LOCK flag by software immediately after operation begins and start processing after the PLL is locked. On the other hand, static processing such as the setting of internal hardware or the initialization of register data or memory data can be executed without waiting for the LOCK flag to be reset to 0. 378 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.6 Oscillation stabilization time select register (OSTS) This is an 8-bit register that specifies the oscillation stabilization time. The OSTS register is used to make sure that the oscillation stabilization time of the oscillator elapses when the software STOP mode is released. After the software STOP mode is released, the oscillation stabilization time is counted by the time base counter (TBC), and program execution is started about 2 ms later. This register can be read or written in 8-bit units. 7 OSTS 0 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 Address FFFFF6C0H After reset 04H Bit position 2 to 0 Bit name OSTS2 to OSTS0 Specify the oscillation stabilization time. OSTS2 0 0 0 0 1 1 1 1 OSTS1 0 0 1 1 0 0 1 1 OSTS0 0 1 0 1 0 1 0 1 Function Oscillation stabilization time FX/2 FX/2 FX/2 FX/2 FX/2 FX/2 FX/2 FX/2 13 15 16 17 18 19 20 21 Caution When the software STOP mode is released by RESET pin input, the oscillation stabilization time does not elapse. Secure the oscillation stabilization time by the low-level width of the RESET pin input. Remark FX: OSC output clock User's Manual U16031EJ4V1UD 379 CHAPTER 8 CLOCK GENERATION FUNCTION 8.4 Operation 8.4.1 Operation status of each clock The following table shows the operation status of each clock. Table 8-1. Operation Status of Each Clock Clock Source OSC PLL Main Clock (fX) Clock Supply to On-Chip Peripheral Function PLL mode Normal operation HALT mode IDLE mode Software STOP mode Oscillation stabilization period Reset period x x x x x x x Internal System Clock (fCLK) x x x Note 1 USB Clock (fUSB) BUSCLK x x x x x x Note 1 Note 2 Note 2 Remark : Operates x: Stops Notes 1. 2. The system operates on the OSC output clock at power application. It stops when the operation is restored from the software STOP mode by an interrupt. Operates on the OSC output clock. 8.4.2 Setting of input clock (FX) This table lists the frequencies supplied to the V850E/ME2. Table 8-2. Frequency List Multiple PLLSEL Pin SSEL1 Pin SSEL0 Pin Input Frequency (MHz) (Target Values) 8 1 0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 Setting prohibited 10.00 to 10.19 10.20 to 11.99 12.00 to 14.39 14.40 to 17.39 17.40 to 18.75 Setting prohibited Main Clock (fX) Frequency (MHz) Setting prohibited 80.00 to 81.59 81.60 to 95.99 96.00 to 115.19 115.20 to 139.19 139.20 to 150.00 Setting prohibited Caution The MAX. value of fCLK of a 100 MHz version is 100 MHz, that of a 133 MHz version is 133 MHz, and that of a 150 MHz version is 150 MHz. The operation is not guaranteed if fCLK (MAX.) < fX. Make sure that fX does not exceed the guaranteed operating frequency of each product. 380 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.5 Operating Clock Provisions SSCG consists of a multiplier that multiplies the OSC clock by eight and a modulation circuit for frequency diffusion. The multiplier that multiplies the OSC clock generates an output error of up to 150 ps in the output period because of its circuit characteristics. The modulation circuit adds the modulation error with respect to the set modulation rate, which varies depending on the modulation rate. Therefore, the output frequency (fCLK) of BUSCLK, which outputs a clock via SSCG, and the operating frequency of the on-chip peripheral I/O (main clock (fX) of timers C, D, and ENC1, PWM unit, CSI3, UARTB, and A/D converter) are affected by this error. When calculating the frequency of each signal, therefore, be sure to take this error into consideration. The methods of calculating the output period and output frequency at each modulation rate are shown below. (1) Minimum value of operating frequency (fMIN) Modulation Rate of SSCG Output (%) No modulation -0.50 -1.00 -2.00 -3.00 -4.00 -5.00 Parameter 1.00000 0.99110 0.98625 0.97450 0.96335 0.95085 0.93860 Output Period: TMAX (ns) (1/fX) x 10 + 0.15 3 Output Frequency (MHz) (1/TMAX) x 10 3 {1/(0.99110 x fX)} x 10 +0.15 3 (1/TMAX) x 10 (1/TMAX) x 10 (1/TMAX) x 10 (1/TMAX) x 10 (1/TMAX) x 10 (1/TMAX) x 10 3 {1/(0.98625 x fX)} x 10 + 0.15 3 3 {1/(0.97450 x fX)} x 10 + 0.15 3 3 {1/(0.96335 x fX)} x 10 + 0.15 3 3 {1/(0.95085 x fX)} x 10 + 0.15 3 3 {1(0.93860 x fX)} x 10 + 0.15 3 3 (2) Maximum value of operating frequency (fMAX) Modulation Rate of SSCG Output (%) No modulation -0.50 -1.00 -2.00 -3.00 -4.00 -5.00 Parameter 1.00000 1.00390 1.00375 1.00550 1.00665 1.00915 1.01140 Output Period: TMAX (ns) (1/fX) x 10 - 0.15 3 Output Frequency (MHz) (1/TMIN) x 10 3 {1/(1.00390 x fX)} x 10 - 0.15 3 (1/TMIN) x 10 (1/TMIN) x 10 (1/TMIN) x 10 (1/TMIN) x 10 (1/TMIN) x 10 (1/TMIN) x 10 3 {1/(1.00375 x fX)} x 10 - 0.15 3 3 {1/(1.00550 x fX)} x 10 - 0.15 3 3 {1/(1.00665 x fX)} x 10 - 0.15 3 3 {1/(1.00915 x fX)} x 10 - 0.15 3 3 {1/(1.01140 x fX)} x 10 - 0.15 3 3 (3) Average operating frequency (fAVE) The average operating frequency can be calculated by this expression. Average operating frequency (fAVE) = (fMIN + fMAX)/2 The average operating frequency is in one period of the modulation period set by the SMDL1 and SMDL0 bits of the SSCGC register. The average operating frequency in a period shorter than the modulation period may have a relatively larger error than the result of the above expression. User's Manual U16031EJ4V1UD 381 CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.1 Calculating BUSCLK frequency If the modulation function of SSCG is used, the internal system clock frequency (fCLK) from which BUSCLK is generated fluctuates. Exercise care in calculating the frequency of BUSCLK. The following table shows the frequency fluctuation of BUSCLK. Table 8-3. Frequency Fluctuation of BUSCLK BMC Register CKM1 0 0 1 1 CKM1 0 1 0 1 fMIN fMIN/2 fMIN/3 fMIN/4 Min. fAVE fAVE/2 fAVE/3 fAVE/4 BUSCLK Frequency (MHz) Typ. fMAX fMAX/2 fMAX/3 fMAX/4 Max. 8.5.2 Calculating operating clock frequency of each on-chip peripheral function When the modulation function of SSCG is used, the main clock (fX) from which the operating clock of each on-chip peripheral function is generated fluctuates. Note (1) to (8) below. (1) Count period of timer C: Period of count clock frequency (set by the CSCn2 to CSCn0 bits of the TMCCn0 register) when input clock is specified (ETICn bit of the TMCCn1 register = 0) (n = 0 to 5) The count period can be calculated from the average operating frequency. However, the average operating frequency is in one period of the modulation period set by the SMDL1 and SMDL0 bits of the SSCGC register. Note that the average operating frequency may have a relatively larger error than the result of calculation during a count operation in a period shorter than the modulation period. If it is necessary to guarantee an absolute value for the count operation, it is recommended to set appropriate counts during operation at fMIN if the counting operation is performed within a specific time and during operation at fMAX if the operation is performed for longer than a specific time. Do not use the modulation function of SSCG if a high-accuracy count operation is necessary. (2) Count period of timer D: Period of count clock frequency (set by CSDn2 to CSDn0 bits of the TMCDn register) (n = 0 to 3) The count period can be calculated from the average operating frequency. However, the average operating frequency is in one period of the modulation period set by the SMDL1 and SMDL0 bits of the SSCGC register. Note that the average operating frequency may have a relatively larger error than the result of calculation during a count operation in a period shorter than the modulation period. If it is necessary to guarantee an absolute value for the count operation, it is recommended to set appropriate counts during operation at fMIN if the counting operation is performed within a specific time and during operation at fMAX if the operation is performed for longer than a specific time. Do not use the modulation function of SSCG if a high-accuracy count operation is necessary. 382 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION (3) Count period of timer ENC1: Period of count clock frequency (set by PRM1n2 to PRM1n0 bits of the PRM1n register) when generalpurpose timer mode is specified (T1CMDn bit of the TUM1n register = 0) (n = 0, 1) The count period can be calculated from the average operating frequency. However, the average operating frequency is in one period of the modulation period set by the SMDL1 and SMDL0 bits of the SSCGC register. Note that the average operating frequency may have a relatively larger error than the result of calculation during a count operation in a period shorter than the modulation period. If it is necessary to guarantee an absolute value for the count operation, it is recommended to set appropriate counts during operation at fMIN if the counting operation is performed within a specific time and during operation at fMAX if the operation is performed for longer than a specific time. Duty setting is guaranteed during either high level output or low level output when timer output is performed. Do not use the modulation function of SSCG if a high-accuracy count operation is necessary. (4) Pulse output period of PWM unit: Period of operating clock frequency (set by the CKSPn1 and CKSPn0 bits of the PWMCn register) (n = 0, 1) The pulse output period can be calculated from the average operating frequency. However, the average operating frequency is in one period of the modulation period set by the SMDL1 and SMDL0 bits of the SSCGC register. Note that the average operating frequency may have a relatively larger error than the result of calculation when a pulse with a period shorter than the modulation period is output. If it is necessary to guarantee an absolute value for the pulse output, it is recommended to set appropriate counts during operation at fMIN if the counting operation is performed within a specific time and during operation at fMAX if the operation is performed for longer than a specific time. Duty setting is guaranteed during either high level output or low level output when PWM output is performed. Do not use the modulation function of SSCG if a high-accuracy pulse output is necessary. (5) Serial communication (transmission, reception, or transmission/reception) transfer rate of CSI3: Period of base clock frequency (CKS3n2 to CKS3n0 of the CSIC3n register = other than 111) (n = 0, 1) with master mode specified The transfer rate can be calculated from the average operating frequency. However, the average operating frequency is in one period of the modulation period set by the SMDL1 and SMDL0 bits of the SSCGC register. Note that the average operating frequency may have a relatively larger error than the result of calculation at a transfer rate shorter than the modulation period. If it is necessary to guarantee an absolute value for the transfer rate, it is recommended to set an appropriate transfer rate during operation at fMIN for the minimum transfer rate and during operation at fMAX for the maximum transfer rate. User's Manual U16031EJ4V1UD 383 CHAPTER 8 CLOCK GENERATION FUNCTION (6) Serial communication (transmission or reception) transfer rate of UARTB: Period of serial transfer speed (set by the UBnBRS15 to UBnBRS0 bits of the UBnCTL2 register) (n = 0, 1) Set the value of the transfer rate (set value (k) of the UBnCTL2 register) so that the permissible maximum and minimum baud rate errors are satisfied at both fMIN and fMAX. Here is a calculation example. <1> Determine the set value (k) of the UBnCTL2 register from the calculation result of the expression "Target baud rate x 8/fAVE (Hz)". <2> Calculate the actual baud rate value at fMAX and fMIN, by using the set value (k) calculated in <1> above. <3> Check that the result of calculation in <2> above satisfies the allowable maximum/minimum baud rate error. <4> Calculate the set value of the transfer rate using <1> to <3> (set value (k) of the UBnCTL2 register). Caution Change the modulation rate of SSCG if the set value (set value (k) of the UBnCTL2 register) of the transfer rate that satisfies the above calculation method cannot be obtained. The more the transfer rate is raised, the smaller the selectable modulation rate becomes. (Example) fX = 150 MHz: Setting of modulation rates of 4% and 5% is prohibited. fX = 133 MHz: Setting of modulation rates of 4% and 5% is prohibited. fX = 100 MHz: Setting of modulation rate of 5% is prohibited. (7) A/D converter: Conversion time Calculate the set value (2 to 10 s) of the A/D conversion time (set by the FR3 to FR0 bits of the ADM1 register) by fAVE (calculation by fMIN and fMAX is not necessary). (8) Digital noise elimination time Calculate the minimum noise elimination time set by the NCWCn and NCW1m registers at fMAX and the maximum noise elimination time at fMIN (n = 0 to 3, m = 0, 1). 384 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.6 Power-Save Control 8.6.1 Overview The power-save function has the following three modes. (1) HALT mode In this mode, the clock generator (oscillator (OSC, SSCG) and PLL synthesizer) continues to operate, but the CPU's operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues. The power consumption of the overall system can be reduced by intermittent operation using a combination of the HALT mode and the normal operation mode. The system is switched to HALT mode by a specific instruction (the HALT instruction). (2) IDLE mode In this mode, the clock generator (oscillator (OSC, SSCG) and PLL synthesizer) continues to operate, but the supply of internal system clocks (fCLK) is stopped, which causes the overall system to stop. When the system is released from IDLE mode, it can be switched to normal operation mode quickly because the oscillator's oscillation stabilization time does not need to be secured. The system is switched to IDLE mode by a PSMR register setting. IDLE mode is located midway between software STOP mode and HALT mode in relation to the clock stabilization time and power consumption. It is used for situations in which a low-power-consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released. (3) Software STOP mode In this mode, the overall system is stopped by stopping the clock generator (oscillator (OSC, SSCG) and PLL synthesizer). The system enters an ultra-low-power-consumption state in which only leakage current is lost. The system is switched to software STOP mode by a PSMR register setting. The PLL synthesizer's clock output is stopped at the same time the oscillator is stopped. After software STOP mode is released by RESET input, the oscillator's oscillation stabilization time must be secured until the system clock stabilizes. When the software STOP mode is released by the non-maskable interrupt request (NMI) or an unmasked maskable interrupt request, program execution is started about 2 ms after the count time of the time base counter (TBC) elapses. User's Manual U16031EJ4V1UD 385 CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use. Figure 8-2. Power-Save Mode State Transition Diagram Normal operation mode Release according to RESET Wait for oscillation stabilization + wait for PLL lockup Release according to RESET or interruptNote 3 Set HALT mode Release according to RESET or interrupt requestNote 2 HALT mode Release according to interrupt requestNote 1 Set STOP mode Set IDLE mode IDLE mode Software STOP mode Notes 1. Non-maskable interrupt request signal (NMI), unmasked external maskable interrupt request signalNote 4, or unmasked internal maskable interrupt request signalNote 5 of peripheral function that can operate in software STOP mode 2. Non-maskable interrupt request signal (NMI), unmasked external maskable interrupt request signalNote 4, or unmasked internal maskable interrupt request signalNote 5 of peripheral function that can operate in IDLE mode 3. 4. Non-maskable interrupt request signal (NMI) or unmasked maskable interrupt request signalNote 4 INTPn (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, L1) When level detection is specified for the INTPn pin, software STOP mode and IDLE mode cannot be released. 5. INTRSUM 386 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.6.2 Control registers (1) Power-save mode register (PSMR) This is an 8-bit register that controls power-save mode. It is effective only when the STP bit of the PSC register is set to 1. Writing to the PSMR register is executed by the store instruction (ST/SST instruction) and a bit manipulation instruction (SET1/CLR1/NOT1 instruction). This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 7, 5, and 4 to 0. If they are set to 1, the operation is not guaranteed. 7 PSMR 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> Address FFFFF820H After reset 00H PSM Bit position 0 Bit name PSM Function Specifies IDLE mode or software STOP mode. 0: Switches the system to IDLE mode 1: Switches the system to software STOP mode (2) Command register (PRCMD) This is an 8-bit register that is used to set protection for write operations to registers that can significantly affect the system so that the application system is not halted unexpectedly due to an inadvertent program loop. Writing to the first specific register (power-save control register (PSC), etc.) is only valid after first writing to the PRCMD register. Because of this, the register value can be overwritten only by the specified sequence, preventing an illegal write operation from being performed. This register is write-only, in 8-bit units (when it is read, undefined data is read out). 7 PRCMD RREG7 6 RREG6 5 RREG5 4 RREG4 3 RREG3 2 RREG2 1 RREG1 0 RREG0 Address FFFFF1FCH After reset Undefined Bit position 7 to 0 Bit name RREG7 to RREG0 Registration code (arbitrary 8-bit data) Function The specific register targeted is as follows. * Power-save control register (PSC) * Clock control register (CKC) * Clock source select register (CKS) * SSCG control register (SSCGC) User's Manual U16031EJ4V1UD 387 CHAPTER 8 CLOCK GENERATION FUNCTION (3) Power-save control register (PSC) This is an 8-bit register that controls the power-save function. If interrupts are enabled by the setting of the NMIM and INTM bits, the software STOP mode can be released by an interrupt request (except when interrupt servicing is disabled by the interrupt mask registers (IMR0 to IMR5)). The software STOP mode is specified by the setting of the STP bit. This register, which is one of the specific registers, is valid only when accessed in a specific sequence during a write operation. This register can be read or written in 8-bit or 1-bit units. Be sure to clear bits 7 and 6 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. It is impossible to set the STP bit and the NMIM or INTM bit at the same time. Be sure to set the STP bit after setting the NMIM or INTM bit. 2. The software STOP mode is not released by an interrupt request for which the NMIM and INTM bits are set to 1 because this interrupt request is invalid (it is not held pending). 7 PSC 0 6 0 <5> <4> 3 0 2 0 <1> 0 0 Address FFFFF1FEH After reset 00H NMIM INTM STP Bit position 5 Bit name NMIM Function This is the enable/disable setting bit for standby mode release using the valid edge input of NMI Note . 0: Release by NMI enabled 1: Release by NMI disabled 4 INTM This is the enable/disable setting for standby mode release using an unmasked maskable interrupt (INTPn) (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, L1) Note . 0: Release by maskable interrupt enabled 1: Release by maskable interrupt disabled 1 STP Indicates the standby mode status. If 1 is written to this bit, the system enters IDLE or software STOP mode (set by the PSM bit of the PSMR register). When standby mode is released, this bit is automatically reset to 0. 0: Standby mode is released 1: Standby mode is in effect Note Setting these bits is valid only in the IDLE/software STOP mode. 388 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Set data in the power-save control register (PSC) in the following sequence. <1> Set the power-save mode register (PSMR) (with the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <2> Prepare data in any one of the general-purpose registers to set to the specific register. <3> Write data to the command register (PRCMD). <4> Set the power-save control register (PSC) (with the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <5> Insert the NOP instructions (5 instructions (<5> to <9>). [Sample coding] <1> ST.B <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP (next instruction) r11, PSMR[r0] 0x02, r10 r10, PRCMD[r0] r10, PSC[r0] ; Write PRCMD register ; Set PSC register ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Execution routine after software STOP mode and IDLE mode release ; Set PSMR register No special sequence is required to read the specific register. Cautions 1. A store instruction for the command register does not acknowledge interrupts. This coding is made on assumption that <3> and <4> above are executed by the program with consecutive store instructions. If another instruction is set between <3> and <4>, the above sequence may become ineffective when the interrupt is acknowledged by that instruction, and a malfunction of the program may result. 2. Although the data written to the PRCMD register is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the PRCMD register (<3>). The same method should be applied when using a general-purpose register for addressing. 3. At least 5 NOP instructions must be inserted after executing a store instruction to the PSC register to set software STOP or IDLE mode. 4. Be sure to terminate all DMA transfers prior to the execution of the above sequence. User's Manual U16031EJ4V1UD 389 CHAPTER 8 CLOCK GENERATION FUNCTION 8.6.3 HALT mode (1) Setting and operation status In HALT mode, the clock generator (oscillator (OSC, SSCG) and PLL synthesizer) continues to operate, but the operation clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues. The power consumption of the overall system can be reduced by setting the system to HALT mode while the CPU is idle. The system is switched to HALT mode by the HALT instruction. Although program execution stops in HALT mode, the contents of all registers, internal data RAM, internal instruction RAM, and ports are maintained in the state they were in immediately before HALT mode began. Also, operation continues for all on-chip peripheral functions (other than ports) that do not depend on CPU instruction processing. The following shows the status of each hardware unit in HALT mode. Cautions 1. If the HALT instruction is executed while an interrupt request signal is being held pending, the HALT mode is set once but it is immediately released by the pending interrupt request signal. 2. At least 5 NOP instructions must be inserted after executing a HALT instruction. 390 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-4. Operation Status in HALT Mode Function Clock generator Main clock (fX) CPU Internal data Operating Operating Stopped All internal data such as CPU registers, statuses, data, and the contents of internal data RAM and internal instruction RAM are maintained in the state they were in immediately before HALT mode began. Operating Operating Operating Operating Operating Operating Operating Operating Maintained the state before HALT mode set Operating Operating Operation Status DMAC INTC TMC0 to TMC5 TMD0 to TMD3 TMENC10, TMENC11 UARTB0, UARTB1 CSI30, CSI31 A/D converter Ports USB function controller D0 to D31 A0 to A25 RD, WE/WR, BCYST ULWR, UUWR, LLWR, LUWR, IORD, IOWR LLDQM, LUDQM, ULDQM, UUDQM LLBE, LUBE, ULBE, UUBE CS0 to CS7 SDRAS SDCAS REFRQ HLDAK HLDRQ WAIT SELFREF SDCKE BUSCLK Clock output User's Manual U16031EJ4V1UD 391 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of HALT mode HALT mode is released by a non-maskable interrupt request signal, an unmasked maskable interrupt request signal (INTPn)Note, or RESET pin input (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, L1). (a) Release according to a non-maskable interrupt request signal or an unmasked maskable interrupt request signal HALT mode is released by a non-maskable interrupt request signal or by an unmasked maskable interrupt request signal regardless of the priority. The operation after release is as follows. Table 8-5. Operation After HALT Mode Is Released by Interrupt Request Signal Release Source Non-maskable interrupt request signal Unmasked maskable interrupt request signal Enable Interrupt (EI) Status Branch to handler address Disable Interrupt (DI) Status Branch to handler address or execute next instruction Execute next instruction However, if the system is set to HALT mode during an interrupt servicing routine, operation will differ as follows. (i) If an interrupt request signal is generated with a lower priority than that of the maskable interrupt request signal that is currently being serviced, HALT mode is released, but the newly generated interrupt request signal is not acknowledged. The new interrupt request signal is held pending. (ii) If an interrupt request signal (including non-maskable interrupt request signals) is generated with a higher priority than that of the maskable interrupt request signal that is currently being serviced, HALT mode is released and the newly generated interrupt request signal is acknowledged. (b) Release according to RESET pin input This is the same as a normal reset operation. The BUSCLK operation when the HALT mode is released is illustrated below. 392 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Figure 8-3. BUSCLK Operation When HALT Mode Is Released (a) When HALT mode is released by non-maskable interrupt request signal or unmasked external maskable interrupt request signal Power supply voltage OSC output clock (FX) H OSC output stabilized Internal system clock (fCLK) fX = FX x 8 (SSCG output), SSCG output stabilized (LOCK = 0) Interrupt request signal BUSCLK <1> Remarks 1. <1>: Interrupt signal (active) input 2. BUSCLK is output normally in the HALT mode. (b) When HALT mode is released by RESET pin input Power supply voltage H OSC output clock (FX) OSC output stabilized Internal system clock (fCLK) fX = FX (OSC output) fX = FX x 8 (SSCG output) SSCG output stabilized (LOCK = 0) RESET (input) BUSCLK PLL lockup time (2 ms or more) <1> <2> <3> <4> <5> Remarks 1. <1>: RESET input <2>: RESET cleared (counting PLL lockup time starts) <3>: PLL lock status (LOCK bit of LOCKR register = 0) <4>: BUSCLK = fCLK/2 (CKM1 and CKM0 bits of BMC register = 01) <5>: fX = FX x 8 (CKSSEL bit of CKS register = 1) 2. The above operation is performed if BUSCLK operates with half the period of the internal system clock (fCLK). User's Manual U16031EJ4V1UD 393 CHAPTER 8 CLOCK GENERATION FUNCTION 8.6.4 IDLE mode (1) Setting and operation status In this mode, the entire system is stopped with the clock generator (oscillator (OSC, SSCG) and PLL synthesizer) continuing to operate and clock supply to the CPU and other on-chip peripheral functions stopped. When IDLE mode is released, the system can be switched to normal operation mode quickly because the oscillator's oscillation stabilization time or the PLL lockup time does not need to be secured. The system is switched to IDLE mode by setting the PSC or PSMR register using a store instruction (ST or SST instruction) or a bit manipulation instruction (SET1, CLR1, or NOT1 instruction) (see 8.6.2 Control registers). In IDLE mode, program execution is stopped, and the contents of all registers, internal data RAM, internal instruction RAM, and ports are maintained in the state they were in immediately before execution stopped. The operation of CPU and other on-chip peripheral functions is stopped. The following shows the status of each hardware unit in IDLE mode. Caution Insert at least 5 NOP instructions after the instruction that stores data in the PSC register to set the IDLE mode. 394 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-6. Operation Status in IDLE Mode Function Clock generator Main clock (fX) CPU Internal data Operating Stopped Stopped All internal data such as CPU registers, statuses, data, and the contents of internal data RAM and internal instruction RAM are maintained in the state they were in immediately before IDLE mode began. DMAC INTC TMC0 to TMC5 TMD0 to TMD3 TMENC10, TMENC11 UARTB0, UARTB1 CSI30, CSI31 A/D converter Ports USB function controller D0 to D31 A0 to A25 RD, WE/WR, BCYST ULWR, UUWR, LLWR, LUWR, IORD, IOWR LLDQM, LUDQM, ULDQM, UUDQM LLBE, LUBE, ULBE, UUBE CS0 to CS7 SDRAS SDCAS REFRQ HLDAK HLDRQ WAIT SELFREF SDCKE BUSCLK Low-level output (outputs high level when SDRAM controller is not used) Low-level output Operating (outputs high level when SDRAM controller is not used) High-level output Input (no sampling) Self-refresh status when connected to SDRAM High-level output Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Maintained the state before IDLE mode set Stopped High impedance Operation Status User's Manual U16031EJ4V1UD 395 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of IDLE mode The IDLE mode is released by a non-maskable interrupt request signal, an unmasked external maskable interrupt request signal (INTPn)Note, an unmasked internal maskable interrupt request signal of a peripheral function that can operate in the IDLE mode (INTRSUM), and RESET pin input (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, or L1). Note When level detection is set, the IDLE mode cannot be released. (a) Release according to a non-maskable interrupt request signal or an unmasked maskable interrupt request signal IDLE mode can be released by an interrupt request signal only when it has been set with the INTM and NMIM bits of the PSC register cleared to 0. IDLE mode is released by a non-maskable interrupt request signal, an unmasked external maskable interrupt request signal (INTPn), or an unmasked internal maskable interrupt request signal of a peripheral function that can operate in the IDLE mode (INTRSUM) regardless of the priority (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, or L1). The operation after release is as follows. Caution When the INTM bit of the PSC register = 1, the IDLE mode cannot be released by the unmasked maskable interrupt request signal. Table 8-7. Operation After IDLE Mode Is Released by Interrupt Request Signal Release Source Non-maskable interrupt request signal Unmasked maskable interrupt request signal Enable Interrupt (EI) Status Branch to handler address Branch to handler address or execute next instruction Execute next instruction Disable Interrupt (DI) Status However, if the system is set to IDLE mode during an interrupt servicing routine, operation will differ as follows. (i) If an interrupt request signal is generated with a lower priority than that of the maskable interrupt request signal that is currently being serviced, IDLE mode is released, but the newly generated interrupt request signal is not acknowledged. The new interrupt request signal is held pending. (ii) If an interrupt request signal (including non-maskable interrupt request signals) is generated with a higher priority than that of the maskable interrupt request signal that is currently being serviced, IDLE mode is released and the newly generated interrupt request signal is acknowledged. If the system is set to IDLE mode during an NMI servicing routine, IDLE mode is released, but the interrupt is not acknowledged (interrupt is held pending). Interrupt servicing that is started when IDLE mode is released by NMI pin input is handled in the same way as normal NMI interrupt servicing that occurs during an emergency (because the NMI interrupt handler address is unique). Therefore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the PSMR register using a store instruction or a bit manipulation instruction. By checking for this status during NMI interrupt servicing, an ordinary NMI can be distinguished from the processing that is started when IDLE mode is released by NMI pin input. (b) Release according to RESET pin input This is the same as a normal reset operation. 396 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION The BUSCLK operation when the IDLE mode is released is illustrated below. Figure 8-4. BUSCLK Operation When IDLE Mode Is Released (a) When IDLE mode is released by non-maskable interrupt request signal or unmasked external maskable interrupt request signal Power supply voltage OSC output clock (FX) OSC output stabilized Internal system clock (fCLK) fX = FX x 8 (SSCG output), SSCG output stabilized (LOCK = 0) H Interrupt request signal BUSCLK <1> Remark <1>: Interrupt signal (active) input (b) When IDLE mode is released by RESET pin input Power supply voltage H OSC output clock (FX) OSC output stabilized Internal system clock (fCLK) fX = FX (OSC output) fX = FX x 8 (SSCG output) SSCG output stabilized (LOCK = 0) RESET (input) BUSCLK PLL lockup time (2 ms or more) <1> <2> <3> <4> <5> Remarks 1. <1>: RESET input <2>: RESET cleared (counting PLL lockup time starts) <3>: PLL lock status (LOCK bit of LOCKR register = 0) <4>: BUSCLK = fCLK/2 (CKM1 and CKM0 bits of BMC register = 01) <5>: fX = FX x 8 (CKSSEL bit of CKS register = 1) 2. The above operation is performed if BUSCLK operates with half the period of the internal system clock (fCLK). User's Manual U16031EJ4V1UD 397 CHAPTER 8 CLOCK GENERATION FUNCTION 8.6.5 Software STOP mode (1) Setting and operation status In software STOP mode, the clock generator (oscillator (OSC, SSCG) and PLL synthesizer) is stopped. The overall system is stopped, and ultra-low power consumption is achieved in which only leakage current is lost. The system is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 8.6.2 Control registers). The oscillator's oscillation stabilization time and PLL frequency stabilization time must be secured after software STOP mode is released. If the software STOP mode is released by an unmasked maskable interrupt request signalNote, program execution is started after the PLL lockup time (about 2 ms) has elapsed after the count time of the time base counter (TBC) (time set by the OSTS register) elapses. Although program execution stops in software STOP mode, the contents of all registers, internal data RAM, internal instruction RAM, and ports are maintained in the state they were in immediately before software STOP mode began. The operation of CPU and other on-chip peripheral functions is stopped. The following shows the status of each hardware unit in software STOP mode. Note INTP10, INTP11, INTP21 to INTP25, INTP50 to INTP52, INTP65 to INTP67, INTPD0 to INTPD15, INTPL0, INTPL1, INTRSUM Cautions 1. Insert at least 5 NOP instructions after the instruction that stores data in the PSC register to set the software STOP mode. 2. If the software STOP mode is released by an unmasked maskable interrupt request signal, the external bus continues to operate in the same status as in the software STOP mode during the count time (time set by the OSTS register) of the time base counter (TBC) and the PLL lockup time. 3. Before setting software STOP mode, set (1) the xxICn interrupt mask flag corresponding to the interrupt that can be used as a release source for software STOP mode but is not used for that purpose. If the timing at which such an interrupt occurs and the shift to software STOP mode conflict, the software STOP mode may be released. 398 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-8. Operation Status in Software STOP Mode Function Clock generator Main clock (fX) CPU Internal data Stopped Stopped Stopped All internal data such as CPU registers, statuses, data, and the contents of internal data RAM and internal instruction RAM are maintained in the state they were in immediately before software STOP mode began. DMAC INTC TMC0 to TMC5 TMD0 to TMD3 TMENC10, TMENC11 UARTB0, UARTB1 CSI30, CSI31 A/D converter Ports USB function controller D0 to D31 A0 to A25 RD, WE/WR, BCYST ULWR, UUWR, LLWR, LUWR, IORD, IOWR LLDQM, LUDQM, ULDQM, UUDQM LLBE, LUBE, ULBE, UUBE CS0 to CS7 SDRAS SDCAS REFRQ HLDAK HLDRQ WAIT SELFREF SDCKE BUSCLK Low-level output (outputs high level when SDRAM controller is not used) Low-level output Operating (outputs high level when SDRAM controller is not used) High-level output Input (no sampling) Self-refresh status when connected to SDRAM High-level output Stopped Stopped Stopped Stopped Stopped Stopped Stopped Stopped Maintained the state before software STOP mode set Stopped High impedance Operation Status User's Manual U16031EJ4V1UD 399 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of software STOP mode The software STOP mode is released by a non-maskable interrupt signal input, an unmasked external maskable interrupt request signal (INTPn)Note, an unmasked internal maskable interrupt request signal of a peripheral function that can operate in the software STOP mode (INTRSUM), or RESET pin input (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, or L1). When the software STOP mode is released by RESET pin input, it is necessary to make sure that the oscillation stabilization time of the oscillator elapses. When the software STOP mode is released by the non-maskable interrupt request signal or an unmasked maskable interrupt request signal, program execution starts after about 2 ms after the count time of the time base counter (TBC) elapses. Note When level detection is set, the software STOP mode cannot be released. (a) Release according to a non-maskable interrupt request signal or an unmasked maskable interrupt request signal The software STOP mode can be released by an interrupt request signal only when it has been set with the INTM and NMIM bits of the PCS register cleared to 0. Software STOP mode is released by a non-maskable interrupt request signal, an unmasked external maskable interrupt request signal (INTPn), or an unmasked internal maskable interrupt request signal of a peripheral function that can operate in the software STOP mode (INTRSUM) regardless of the priority (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, or L1). The operation after release is as follows. Caution When the INTM bit of the PSC register = 1, the software STOP mode cannot be released by the unmasked maskable interrupt request signal. Table 8-9. Operation After Software STOP Mode Is Released by Interrupt Request Signal Release Source Non-maskable interrupt request signal Unmasked maskable interrupt request signal Enable Interrupt (EI) Status Branch to handler address Disable Interrupt (DI) Status Branch to handler address or execute next instruction Execute next instruction The operation is performed as shown below if the software STOP mode is set in an interrupt servicing routine. 400 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-10. Operation If Software STOP Mode Is Set in Interrupt Servicing Routine Type of Interrupt Servicing Routine When Software STOP Mode Is Set Maskable interrupt Releasing Cause Releasing Source Maskable interrupt request signal Priority Low Same High (ID = 1) High (ID = 0) Non-maskable interrupt request signal Non-maskable interrupt Maskable interrupt request signal Non-maskable interrupt request signal Low Same High Interrupt request signal is acknowledged when software STOP mode is released. - - Note 2 Note 1 Operation Only software STOP mode is released and interrupt request signal is not acknowledged (is held pending). Interrupt request signal is acknowledged when software STOP mode is released. Only software STOP mode is released and interrupt request signal is not acknowledged (is held pending). Note 3 Notes 1. 2. 3. Remark Priority of interrupt (being serviced) when software STOP mode is set When the ID bit of the PSW is 1 (disabling acknowledging interrupt) When the ID bit of the PSW is 0 (enabling acknowledging interrupt) The software STOP mode is released by NMI regardless of the value of the NP bit of the PSW. If the system is set to software STOP mode during an NMI servicing routine, software STOP mode is released, but the interrupt is not acknowledged (interrupt is held pending). Interrupt servicing that is started when software STOP mode is released by NMI pin input is handled in the same way as normal NMI interrupt servicing that occurs during an emergency (because the NMI interrupt handler address is unique). Therefore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the PSMR register using a store instruction or a bit manipulation instruction. By checking for this status during NMI interrupt servicing, an ordinary NMI can be distinguished from the servicing that is started when software STOP mode is released by NMI pin input. (b) Release according to RESET pin input This is the same as a normal reset operation. The BUSCLK operation when the software STOP mode is released is illustrated below. User's Manual U16031EJ4V1UD 401 CHAPTER 8 CLOCK GENERATION FUNCTION Figure 8-5. BUSCLK Operation When Software STOP Mode Is Released (1/2) (a) When software STOP mode is released by non-maskable interrupt request signal or unmasked external maskable interrupt request signal Power supply voltage OSC output clock (FX) H OSC output undefined Internal system clock (fCLK) OSC output stabilized fX = FX x 8 (SSCG output), SSCG output stabilized (LOCK = 0) Interrupt request signal BUSCLK Oscillation stabilization time PLL lockup time (2 ms or more) <2> <3> <1> Remark <1>: Interrupt signal (active) input (counting the oscillation stabilization time starts) <2>: OSC output oscillation stabilization (counting of the oscillation stabilization time/PLL lockup time starts) <3>: Operation starts in the status before the software STOP mode is set after the PLL lock status (counting the PLL lockup time ends) 402 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION Figure 8-5. BUSCLK Operation When Software STOP Mode Is Released (2/2) (b) When software STOP mode is released by RESET pin input Power supply voltage H OSC output clock (FX) OSC output undefined Internal system clock (fCLK) fX = FX (OSC output) Secure oscillation stabilization time RESET (input) fX = FX x 8 (SSCG output) SSCG output stabilized (LOCK = 0) OSC output stabilized BUSCLK PLL lockup time (2 ms or more) <1> <2> <3> <4> <5> <6> Remarks 1. <1>: RESET input <2>: OSC output oscillation stabilization <3>: RESET cleared (counting PLL lockup time starts) <4>: PLL lock status (LOCK bit of LOCKR register = 0) <5>: BUSCLK = fCLK/2 (CKM1 and CKM0 bits of BMC register = 01) <6>: fX = FX x 8 (CKSSEL bit of CKS register = 1) 2. The above operation is performed if BUSCLK operates with half the period of the internal system clock (fCLK). User's Manual U16031EJ4V1UD 403 CHAPTER 8 CLOCK GENERATION FUNCTION 8.7 Securing Oscillation Stabilization Time 8.7.1 Oscillation stabilization time security specification When the software STOP mode is released by a non-maskable interrupt request signal, an unmasked external maskable interrupt request signal (INTPn)Note (n = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, or L1), or an unmasked internal maskable interrupt request signal of a peripheral function that can operate in the software STOP mode (INTRSUM), the oscillation stabilization time set by the OSTS register is secured (see Figure 8-5 (a)). About 2 ms after that, program execution is started. When the software STOP mode is released by RESET pin input, the oscillation stabilization time does not elapse. Therefore, secure the oscillation stabilization time by the low-active width of RESET (see Figure 8-5 (b)). The internal time base counter (TBC) is used as a timer that counts and secures the oscillation stabilization time. Oscillation stabilization time = Count time of TBC Note When level detection is set, the software STOP mode cannot be released. 8.7.2 Time base counter (TBC) The time base counter (TBC) is used to secure the oscillator's oscillation stabilization time when software STOP mode is released. The TBC counts the oscillation stabilization time after software STOP mode is released, and program execution begins after the count is completed. The TBC count clock is selected according to the OSTS2 to OSTS0 bits of the OSTS register, and the next counting time can be set. Table 8-11. Counting Time Examples OSTS2 to OSTS0 Bits Oscillation Stabilization Time 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 FX/2 FX/2 FX/2 FX/2 FX/2 FX/2 FX/2 FX/2 13 Counting Time FX = 16.6 MHz 0.49 ms 1.97 ms 3.95 ms 7.90 ms 15.79 ms 31.58 ms 63.17 ms 126.33 ms fX = 12.5 MHz 0.66 ms 2.62 ms 5.24 ms 10.49 ms 20.97 ms 41.94 ms 83.89 ms 167.77 ms 15 16 17 18 19 20 21 Remark FX: OSC output clock 404 User's Manual U16031EJ4V1UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.8 Cautions Cautions concerning the clock generation function are shown below. (1) Caution on setting CKC register Note that if the internal system clock (fCLK) is changed, the frequency of the bus clock (BUSCLK) is also changed. (2) Caution on setting CKS register With the V850E/ME2, it is not assumed that the CPU operates with the OSC output always supplied as the main clock (CKSSEL bit of CKS register = 0). Therefore, be sure to confirm in the initialization sequence that the LOCK bit of the LOCKR register is 0, and then supply the main clock from the SSCG output (CKSSEL bit = 1); otherwise the operation will not be guaranteed. (3) Caution on setting SSCGC register The SSCGC register can be set only when OSC output is supplied as the main clock (CKSSEL bit of CKS register = 0). If the setting of the SSCGC register is changed, the SSCG is unlocked (LOCK bit of LOCKR register = 1). Be sure to confirm that the LOCK bit = 0 before starting to supply SSCG output as the main clock (CKSSEL bit = 1); otherwise the operation will not be guaranteed. User's Manual U16031EJ4V1UD 405 CHAPTER 9 TIMER/COUNTER FUNCTION 9.1 9.1.1 Timer C Features Timer C is a 16-bit timer/counter that can perform the following operations. * Interval timer function * PWM output * External signal cycle measurement 9.1.2 Function overview * 16-bit timer/counter: 6 channels (no capture operation for 2 channels) * Capture/compare common registers: 12 sources * Interrupt request sources * Capture/match interrupt requests: 12 sources Capture register: Generates INTCCCm0 or INTCCCm1 at INTPCm0 or INTPCm1 input Compare register: Generates INTCCCn0 or INTCCCn1 at match signal of CCCn0 or CCCn1 * Overflow interrupt requests: 6 sources * Timer/counter count clock sources: 2 types (Selection of external pulse input or main clock division) * Either free-running mode or overflow stop mode can be selected as the operation mode when the timer/counter overflows * Timer/counter can be cleared by a match of the timer/counter and a compare register * External pulse outputs: 6 Remark m = 0 to 3, n = 0 to 5 406 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.3 Basic configuration Table 9-1. Timer C Configuration Timer Count Clock Register Read/Write Generated Interrupt Signal Capture Trigger - INTPC00 INTPC01 - INTPC10 INTPC11 - INTPC20 INTPC21 - INTPC30 INTPC31 - - Timer Output S/R - TOC0 (S) TOC0 (R) - TOC1 (S) TOC1 (R) - TOC2 (S) TOC2 (R) - TOC3 (S) TOC3 (R) - TOC4 (S) Other Functions Timer C fX/8, fX/16, fX/32, fX/64, fX/128, fX/256, fX/512, fX/1,024 TMC0 CCC00 CCC01 TMC1 CCC10 CCC11 TMC2 CCC20 CCC21 TMC3 CCC30 CCC31 TMC4 CCC40 Read Read/write Read/write Read Read/write Read/write Read Read/write Read/write Read Read/write Read/write Read Read/write INTOVC0 INTCCC00 INTCCC01 INTOVC1 INTCCC10 INTCCC11 INTOVC2 INTCCC20 INTCCC21 INTOVC3 INTCCC30 INTCCC31 INTOVC4 INTCCC40 A/D conversion start trigger A/D conversion start trigger CCC41 Read/write INTCCC41 - TOC4 (R) TMC5 CCC50 Read Read/write INTOVC5 INTCCC50 - - - TOC5 (S) A/D conversion start trigger A/D conversion start trigger CCC51 Read/write INTCCC51 - TOC5 (R) Remark fX: Main clock S/R: Set/reset User's Manual U16031EJ4V1UD 407 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer C (16-bit timer/counter) Figure 9-1. Timer C Block Diagram Selector fX/4 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 Clear & start TMCn (16 bits) INTOVCn Edge detector INTCMD0 of TMD0 TICm/INTPCm0 INTPCm1 Noise filter Noise filter Edge detector Edge detector CCCn0 CCCn1 S R Note Q Q Selector TOCn Selector INTCCCn0 Selector INTCCCn1 NCCCn1 NCCCn0 Noise elimination width setting register Cn (NCWCn) Internal bus Note Reset priority Remarks 1. m = 0 to 3, n = 0 to 5 2. fX: Main clock 408 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.4 Timer C (1) Timers C0 to C5 (TMC0 to TMC5) TMCn functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being mainly used for cycle measurement, TMCn can be used as pulse output (n = 0 to 5). TMCn is read-only, in 16-bit units. Cautions 1. The TMCn register can only be read. If the TMCn register is written, the subsequent operation is undefined. 2. If the CAECn bit of the TMCCn0 register is cleared to 0, a reset is performed asynchronously. 15 TMC0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF600H After reset 0000H TMC1 FFFFF620H 0000H TMC2 FFFFF640H 0000H TMC3 FFFFF660H 0000H TMC4 FFFFF680H 0000H TMC5 FFFFF6A0H 0000H TMCn performs the count-up operations of an internal count clock or external count clock. Timer start and stop are controlled by the CECn bit of timer mode control register Cn0 (TMCCn0) (n = 0 to 5). The internal or external count clock is selected by the ETICn bit of timer mode control register Cn1 (TMCCn1) (n = 0 to 5). User's Manual U16031EJ4V1UD 409 CHAPTER 9 TIMER/COUNTER FUNCTION (a) Selection of the external count clock TMCn operates as an event counter. When the ETICn bit of timer mode control register Cn1 (TMCCn1) is set to 1, TMCm counts the valid edges of the external clock input (TICm), synchronized with the internal count clock. The valid edge is specified by valid edge select register Cm (SESCm) (m = 0 to 3, n = 0 to 5). Caution When the INTPCm0/TICm pin is used as TICm (external clock input pin), disable the INTPCm0 interrupt or set CCCm0 to compare mode (m = 0 to 3, n = 0 to 5). (b) Selection of the internal count clock TMCn operates as a free-running timer. When an internal clock is specified as the count clock by timer mode control register Cn1 (TMCCn1), TMCn is counted up for each input clock cycle specified by the CSCn0 to CSCn2 bits of the TMCCn0 register (n = 0 to 5). Division by the prescaler can be selected for the count clock from among fX/8, fX/16, fX/32, fX/64, fX/128, fX/256, fX/512, and fX/1,024 by the TMCCn0 register (fX: main clock). An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following an overflow by setting the OSTCn bit of the TMCCn1 register to 1. Caution The count clock cannot be changed while the timer is operating. The conditions when the TMCn register becomes 0000H are shown below. (a) Asynchronous reset * CAECn bit of TMCCn0 register = 0 * Reset input (b) Synchronous reset * CECn bit of TMCCn0 register = 0 * The CCCn0 register is used as a compare register, and the TMCn and CCCn0 registers match when clearing the TMCn register is enabled (CCLRCn bit of the TMCCn1 register = 1) 410 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Capture/compare registers Cn0 and Cn1 (CCCn0 and CCCn1) (n = 0 to 5) These capture/compare registers (Cn0 and Cn1) are 16-bit registers. They can be used as capture registers or compare registers according to the CMSCn0 and CMSCn1 bit specifications of timer mode control register Cn1 (TMCCn1) (n = 0 to 5). These registers can be read or written in 16-bit units. (However, write operations can only be performed in compare mode.) Caution The CCC40, CCC41, CCC50, and CCC51 registers can only be used as compare registers. They cannot be used as capture registers. 15 CCC0n 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF602H, FFFFF604H After reset 0000H CCC1n FFFFF622H, FFFFF624H 0000H CCC2n FFFFF642H, FFFFF644H 0000H CCC3n FFFFF662H, FFFFF664H 0000H CCC4n FFFFF682H, FFFFF684H 0000H CCC5n FFFFF6A2H, FFFFF6A4H 0000H Remark n = 0, 1 User's Manual U16031EJ4V1UD 411 CHAPTER 9 TIMER/COUNTER FUNCTION (a) Setting these registers as capture registers (CMSCn0 and CMSCn1 bits of TMCCn1 register = 0) When these registers are set as capture registers, the valid edges of the corresponding external interrupt signals INTPCm0 and INTPCm1 are detected as capture triggers. The timer TMCm is synchronized with the capture trigger, and the value of TMCm is latched in the CCCm0 and CCCm1 registers (capture operation) (m = 0 to 3, n = 0 to 5). The valid edge of the INTPCm0 pin is specified (rising edge, falling edge, or both rising and falling edges) according to the IESC0m1 and IESC0m0 bits of the SESCm register, and the valid edge of the INTPCm1 pin is specified according to the IESC1m1 and IESC1m0 bits of the SESCm register. The capture operation is performed asynchronously to the count clock. The latched value is held in the capture register until another capture operation is performed. When the CAECn bit of timer mode control register Cn0 (TMCCn0) is 0, 0000H is read. If these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of signals INTPCm0 and INTPCm1. Caution If the capture operation contends with the timing of disabling the TMCm register from counting (when the CECn bit of the TMCCn0 register = 0), the captured data becomes undefined. In addition, the INTCCCm0 and INTCCCm1 interrupts do not occur (m = 0 to 3, n = 0 to 5). (b) Setting these registers as compare registers (CMSCn0 and CMSCn1 bits of TMCCn1 register = 1) When these registers are set as compare registers, the TMCn and register values are compared for each count clock, and an interrupt is generated by a match. If the CCLRCn bit of timer mode control register Cn1 (TMCCn1) is set to 1, the TMCn value is cleared to 0 at the same time as a match with the CCCn0 register (it is not cleared to 0 by a match with the CCCn1 register) (n = 0 to 5). A compare register is equipped with a set/reset function. The corresponding timer output (TOCn) is set or reset, in synchronization with the generation of a match signal. The interrupt selection source differs according to the function of the selected register. Cautions 1. To write to capture/compare registers Cn0 and Cn1, always set the CAECn bit to 1 first. If the CAECn bit is 0, the data that is written will be invalid. 2. Write to capture/compare registers Cn0 and Cn1 after setting them as compare registers via TMCCn0 and TMCCn1 register settings. If they are set as capture registers (CMSCn0 and CMSCn1 bits of TMCCn1 register = 0), no data is written even if a write operation is performed to CCCm0 and CCCm1 (m = 0 to 3, n = 0 to 5). 3. When these registers are set as compare registers, INTPCn0 and INTPCn1 cannot be used (n = 0 to 5). When using these registers as an external interrupt input pin, use the INTP65 and INTP66 pins. 412 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.5 Control registers (1) Timer mode control registers C00 to C50 (TMCC00 to TMCC50) The TMCCn0 registers control the operation of TMCn (n = 0 to 5). These registers can be read or written in 8-bit or 1-bit units. Be sure to clear bits 3 and 2 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. The CAECn and other bits cannot be set at the same time. The other bits and the registers of the other TMCn unit should always be set after the CAECn bit has been set. Also, to use external pins related to the timer function when timer C is used, be sure to set the CAECn bit to 1 after setting the external pins to control mode. 2. When conflict occurs between an overflow and a TMCCn0 register write, the OVFCn bit value becomes the value written during the TMCCn0 register write (n = 0 to 5). (1/2) <7> 6 CSC02 5 CSC01 4 CSC00 3 0 2 0 <1> <0> Address FFFFF606H After reset 00H TMCC00 OVFC0 CEC0 CAEC0 TMCC10 OVFC1 CSC12 CSC11 CSC10 0 0 CEC1 CAEC1 FFFFF626H 00H TMCC20 OVFC2 CSC22 CSC21 CSC20 0 0 CEC2 CAEC2 FFFFF646H 00H TMCC30 OVFC3 CSC32 CSC31 CSC30 0 0 CEC3 CAEC3 FFFFF666H 00H TMCC40 OVFC4 CSC42 CSC41 CSC40 0 0 CEC4 CAEC4 FFFFF686H 00H TMCC50 OVFC5 CSC52 CSC51 CSC50 0 0 CEC5 CAEC5 FFFFF6A6H 00H Bit position 7 Bit name OVFCn Function This is a flag that indicates TMCn overflow. 0: No overflow occurs 1: Overflow occurs When TMCn has counted up from FFFFH to 0000H, the OVFCn bit becomes 1 and an overflow interrupt request (INTOVCn) is generated at the same time. However, if TMCn is cleared to 0000H after a match at FFFFH when the CCCn0 register is set to compare mode (CMSCn0 bit of TMCCn1 register = 1) and clearing is enabled for a match when TMCn and CCCn0 are compared (CCLRCn bit of TMCCn1 register = 1), then TMCn is considered to be cleared and the OVFCn bit does not become 1. Also, no INTOVCn interrupt is generated. The OVFCn bit retains the value 1 until 0 is written directly or until an asynchronous reset is performed because the CAECn bit is 0. An interrupt operation due to an overflow is independent of the OVFCn bit, and the interrupt request flag (OVCIFn) for INTOVCn is not affected even if the OVFCn bit is manipulated. If an overflow occurs while the OVFCn bit is being read, the flag value changes, and the change is reflected when the next read operation occurs. Remark n = 0 to 5 User's Manual U16031EJ4V1UD 413 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 6 to 4 Bit name CSCn2 to CSCn0 Selects the TMCn internal count clock. CSCn2 0 0 0 0 1 1 1 1 CSCn1 0 0 1 1 0 0 1 1 CSCn0 0 1 0 1 0 1 0 1 fX/8 fX/16 fX/32 fX/64 fX/128 fX/256 fX/512 fX/1,024 Count cycle Function Caution The CSCn2 to CSCn0 bits must not be changed during timer operation. If they are to be changed, they must be changed after setting the CECn bit to 0. If these bits are overwritten during timer operation, operation cannot be guaranteed. Remark fX: Main clock 1 CECn Controls the operation of TMCn. 0: Count disabled (stops at 0000H and does not operate) 1: Counting operation is performed Caution When CECn = 0, the external pulse output (TOCn) becomes inactive (the active level of TOCn output is set by the ALVCn bit of the TMCCn1 register). 0 CAECn Controls the internal count clock. 0: The entire TMCn unit is asynchronously reset. The supply of clocks to the TMCn unit stops. 1: Clocks are supplied to the TMCn unit Cautions 1. When the CAECn bit is cleared to 0, the TMCn unit can be asynchronously reset. 2. When CAECn = 0, the TMCn unit is in a reset state. Therefore, to operate TMCn, the CAECn bit must be set to 1. 3. When the CAECn bit is changed from 1 to 0, all registers of the TMCn unit are initialized. When CAECn is set to 1 again, the TMCn unit registers must be set again. Remark n = 0 to 5 414 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer mode control registers C01 to C51 (TMCC01 to TMCC51) The TMCCn1 registers control the operation of TMCn (n = 0 to 5). These registers can be read or written in 8-bit units. Cautions 1. The various bits of the TMCCn1 register must not be changed during timer operation. If they are to be changed, they must be changed after setting the CECn bit of the TMCCn0 register to 0. If these bits are overwritten during timer operation, operation cannot be guaranteed (n = 0 to 5). 2. If the ENTOCn and ALVCn bits are changed at the same time, a glitch (spike shaped noise) may be generated in the TOCn pin output. Either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ENTOCn and ALVCn bits do not change at the same time (n = 0 to 5). 3. TOCn output is not changed by an external interrupt signal (INTPCm0 or INTPCm1). To use the TOCn signal, specify that the capture/compare registers are compare registers (CMSCn0 and CMSCn1 bits of TMCCn1 register = 1) (m = 0 to 3, n = 0 to 5). 4. The TMCC41 and TMCC51 registers can be used only when the CCC40, CCC41, CCC50, and CCC51 registers are used as compare registers. They cannot be used when the CCC40, CCC41, CCC50, and CCC51 registers are used as capture registers. 5. To clear the external interrupt signal by setting the ECLRCn bit, be sure to make the following setting. Count clock period of TMD0 > Count clock period of TMCn If this setting is not made, the falling edge of the INTCMD0 interrupt signal may not be detected. Correct example (if count clock of TMD0 is slow) CSD02 to CSD00 bits of TMCD0 register = 011: fX/64 CSCn2 to CSCn0 bits of TMCC0 register = 001: fX/16 Remark Resetting the flip-flop of the TOCn output takes precedence (n = 0 to 5). User's Manual U16031EJ4V1UD 415 CHAPTER 9 TIMER/COUNTER FUNCTION (1/2) 7 TMCC01 OSTC0 6 ENTOC0 5 ALVC0 4 ETIC0 3 2 1 0 Address FFFFF608H After reset 20H CCLRC0 ECLRC0 CMSC01 CMSC00 TMCC11 OSTC1 ENTOC1 ALVC1 ETIC1 CCLRC1 ECLRC1 CMSC11 CMSC10 FFFFF628H 20H TMCC21 OSTC2 ENTOC2 ALVC2 ETIC2 CCLRC2 ECLRC2 CMSC21 CMSC20 FFFFF648H 20H TMCC31 OSTC3 ENTOC3 ALVC3 ETIC3 CCLRC3 ECLRC3 CMSC31 CMSC30 FFFFF668H 20H TMCC41 OSTC4 ENTOC4 ALVC4 ETIC4 CCLRC4 ECLRC4 CMSC41 CMSC40 FFFFF688H 20H TMCC51 OSTC5 ENTOC5 ALVC5 ETIC5 CCLRC5 ECLRC5 CMSC51 CMSC50 FFFFF6A8H 20H Bit position 7 Bit name OSTCn Function Sets the operation when TMCn has overflowed. 0: After the overflow, counting continues (free-running mode) 1: After the overflow, the timer maintains the value 0000H, and counting stops (overflow stop mode). Counting is resumed by the following operation. When ECLRCn bit = 0: Writing 1 to CECn bit When ECLRCn bit = 1: Inputting valid edge to INTCMD0 6 ENTOCn External pulse output is enabled/disabled (TOCn). 0: External pulse output is disabled. Output of the ALVCn bit inactive level to the TOCn pin is fixed. The TOCn pin level is not changed even if a match signal from the corresponding compare register is generated. 1: External pulse output is enabled. A compare register match causes TOCn output to change. However, if capture mode is set, TOCn output does not change. The ALVCn bit inactive level is output from the time when timer output is enabled until a match signal is first generated. Caution If either CCCn0 or CCCn1 is specified as a capture register, the ENTOCn bit must be cleared to 0. 5 ALVCn Specifies the active level for external pulse output (TOCn). 0: Active level is low level 1: Active level is high level Caution The initial value of the ALVCn bit is 1. 4 ETICn Specifies a switch between the external and internal count clock. 0: Specifies the input clock (internal). The count clock can be selected according to the CSCn2 to CSCn0 bits of TMCCn0. 1: Specifies the external clock (TICm). The valid edge can be selected according to the TESCm1 and TESCm0 bit specifications of SESCm. Remark m = 0 to 3 n = 0 to 5 416 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 3 Bit name CCLRCn Function Sets whether the clearing of TMCn is enabled or disabled during a compare operation. 0: Clearing is disabled 1: Clearing is enabled (if CCCn0 and TMCn match during a compare operation, TMCn is cleared) 2 ECLRCn Enables/disables clearing TMCn by INTCMD0 (TMD0). 0: Disables clearing by INTCMD0. 1: Enables clearing by INTCMD0. After TMCn has been cleared, it resumes counting. Caution When ECLRCn = 1, unless a compare match interrupt (INTCMD0) is generated by TMD0, timer counting does not start (even if the CECn bit of the TMCCn0 register is set (1)). 1 CMSCn1 Selects the operation mode of the capture/compare register (CCCn1). 0: The register operates as a capture register (CCCm1) 1: The register operates as a compare register (CCCn1) 0 CMSCn0 Selects the operation mode of the capture/compare register (CCCn0). 0: The register operates as a capture register (CCCm0) 1: The register operates as a compare register (CCCn0) Remark m = 0 to 3 n = 0 to 5 User's Manual U16031EJ4V1UD 417 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Valid edge select registers C0 to C3 (SESC0 to SESC3) These registers specify the valid edge of an external interrupt request (INTPC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, INTPC31, and TIC0 to TIC3) from an external pin of TMCn (n = 0 to 3). The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. Each of these registers can be read or written in 8-bit units. Be sure to clear bits 5 and 4 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. The various bits of the SESCn register must not be changed during timer operation (n = 0 to 3). If they are to be changed, they must be changed after setting the CECn bit of the TMCCn0 register to 0. If the SESCn register is overwritten during timer operation, operation cannot be guaranteed. 2. Even when using the INTPC00/TIC0, INTPC10/TIC1, INTPC20/TIC2, and INTPC30/TIC3 pins as INTPC00, INTPC10, INTPC20, and INTPC30, respectively, without using timer C, be sure to set the CAECn and CECn bits of timer mode control registers C00 to C03 (TMCC00 to TMCC30) to 1. 3. Set the PMCx register before setting the trigger mode of the INPTC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, INTPC31, and TIC0 to TIC3 pins (x = 5 to 7). Then set the CAECn and CECn bits of the TMCCn0 register to 1 (n = 0 to 3). If the PMCx register is set after the SESCn register has been set, an illegal interrupt, incorrect counting, and incorrect clearing may occur depending on the timing of setting the PMCx register (n = 0 to 3, x = 5 to 7). 418 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 7 SESC0 TESC01 6 TESC00 5 0 4 0 3 2 1 0 Address FFFFF609H After reset 00H IESC101 IESC100 IESC001 IESC000 INTPC01 INTPC00 2 1 0 TIC0 7 SESC1 TESC11 6 TESC10 5 0 4 0 3 Address FFFFF629H After reset 00H IESC111 IESC110 IESC011 IESC010 INTPC11 INTPC10 2 1 0 TIC1 7 SESC2 TESC21 6 TESC20 5 0 4 0 3 Address FFFFF649H After reset 00H IESC121 IESC120 IESC021 IESC020 INTPC21 INTPC20 2 1 0 TIC2 7 SESC3 TESC31 6 TESC30 5 0 4 0 3 Address FFFFF669H After reset 00H IESC131 IESC130 IESC031 IESC030 INTPC31 INTPC30 TIC3 Bit position 7, 6 Bit name TESCn1, TESCn0 (n = 0 to 3) Function Specifies the valid edge of the INTPCm0, INTPCm1, and TICm pins (m = 0 to 3). xESCn1 0 0 1 xESCn0 0 1 0 1 Falling edge Rising edge Setting prohibited Operation 3, 2 IESCn1, IESCn0 (n = 10 to 13) 1, 0 IESCn1, IESCn0 (n = 00 to 03) 1 Both rising and falling edges User's Manual U16031EJ4V1UD 419 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Noise elimination width setting registers C0 to C3 (NCWC0 to NCWC3) The NCWCn registers are used to set the noise elimination width of the digital noise filter of the timer C input pin (n = 0 to 3). These registers can be read or written in 8-bit units. Be sure to clear bits 7 to 2 to 0. If they are set to 1, the operation is not guaranteed. In addition, do not overwrite this register during timer operation. 7 NCWC0 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFF610H After reset 02H NCCC01 NCCC00 NCWC1 0 0 0 0 0 0 NCCC11 NCCC10 FFFFF630H 02H NCWC2 0 0 0 0 0 0 NCCC21 NCCC20 FFFFF650H 02H NCWC3 0 0 0 0 0 0 NCCC31 NCCC30 FFFFF670H 02H Bit position 1, 0 Bit name NCCCn1, NCCCn0 Function Specifies the number of clocks by which noise is to be eliminated. NCCCn1 0 0 1 1 NCCCn0 0 1 0 1 Number of clocks by which noise is to be eliminated 0 (through input) 2 3 5 Remark 1 clock = fX/4 fX: Main clock Remark n = 0 to 3 420 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.6 Operation (1) Count operation Timer C can function as a 16-bit free-running timer or as an external signal event counter. The setting for the type of operation is specified by timer mode control registers Cn0 and Cn1 (TMCCn0 and TMCCn1) (n = 0 to 5). When it operates as a free-running timer, if the CCCn0 or CCCn1 register and the TMCn count value match, an interrupt signal is generated and the timer output signal (TOCn) can be set or reset. Also, a capture operation that holds the TMCm count value in the CCCm0 or CCCm1 register is performed, in synchronization with the valid edge that was detected from the external interrupt request input pin as an external trigger (m = 0 to 3). The capture value is held until the next capture trigger is generated. Caution When using the INTPCm0/TICm0 pin as TICm0 (external clock input pin), be sure to disable the INTPCm0 interrupt or set the CCCm0 register to compare mode (m = 0 to 3). Figure 9-2. Basic Operation of Timer C Count clock TMCn 0000H 0001H 0002H 0003H Count start CECn1 FBFEH FBFFH 0000H 0001H 0002H Count disabled CECn0 Count start CECn1 Remark n = 0 to 5 User's Manual U16031EJ4V1UD 421 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Overflow When the TMCn register has counted the count clock from FFFFH to 0000H, the OVFCn bit of the TMCCn0 register is set to 1, and an overflow interrupt (INTOVCn) is generated at the same time. However, if the CCCn0 register is set to compare mode (CMSCn0 bit = 1) and to the value FFFFH when match clearing is enabled (CCLRCn bit = 1), then the TMCn register is considered to be cleared and the OVFCn bit is not set to 1 when the TMCn register changes from FFFFH to 0000H. Also, the overflow interrupt (INTOVCn) is not generated . When the TMCn register is changed from FFFFH to 0000H because the CECn bit changes from 1 to 0, the TMCn register is considered to be cleared, but the OVFCn bit is not set to 1 and no INTOVCn interrupt is generated. Also, timer operation can be stopped after an overflow by setting the OSTCn bit of the TMCCn1 register to 1. When the timer is stopped due to an overflow, the count operation is not restarted until the CECn bit of the TMCCn0 register is set to 1. Operation is not affected even if the CECn bit is set to 1 during a count operation. Remark n = 0 to 5 Figure 9-3. Operation After Overflow (When OSTCn = 1) Overflow FFFFH Overflow FFFFH Count start TMCn 0 OSTCn 1 CECn 1 CECn 1 INTOVCn Remark n = 0 to 5 422 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Capture operation The TMCn register has two capture/compare registers. These are the CCCn0 register and the CCCn1 register. A capture operation or a compare operation is performed according to the settings of both the CMSCn1 and CMSCn0 bits of the TMCCn1 register. If the CMSCn1 and CMSCn0 bits of the TMCCn1 register are cleared to 0, the register operates as a capture register. A capture operation that captures and holds the TMCm count value asynchronously relative to the count clock is performed in synchronization with an external trigger. The valid edge that is detected from an external interrupt request input pin (INTPCm0 or INTPCm1) is used as an external trigger (capture trigger). The TMCm count value during counting is captured and held in the capture register, in synchronization with that capture trigger signal. The capture register value is held until the next capture trigger is generated. Also, an interrupt request (INTCCCm0 or INTCCCm1) is generated by INTPCm0 or INTPCm1 signal input. The valid edge of the capture trigger is set by valid edge select register Cm (SESCm). If both the rising and falling edges are set as capture triggers, the input pulse width from an external source can be measured. Also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. Remark m = 0 to 3 n = 0 to 5 Figure 9-4. Capture Operation Example n TMC1 0 CEC1 CCC11 (Capture register) n INTPC11 (Capture trigger) (Capture trigger) Remarks 1. When the CEC1 bit is 0, no capture operation is performed even if INTPC11 is input. 2. Valid edge of INTPC11: Rising edge User's Manual U16031EJ4V1UD 423 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-5. TMC1 Capture Operation Example (When Both Edges Are Specified) (TMC1 count values) D1 D0 D2 Overflow OVFC11 TMC1 Count start CEC11 Interrupt request (INTPC11) Capture register (CCC11) D0 D1 D2 Remark D0 to D2: TMC1 count values 424 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (4) Compare operation The TMCn register has two capture/compare registers. These are the CCCn0 register and the CCCn1 register. A capture operation or a compare operation is performed according to the settings of both the CMSCn1 and CMSCn0 bits of the TMCCn1 register. If the CMSCn1 and CMSCn0 bits of the TMCCn1 register are set to 1, the register operates as a compare register. A compare operation that compares the value that was set in the compare register and the TMCn count value is performed. If the TMCn count value matches the value of the compare register, which had been set in advance, a match signal is sent to the output controller. The match signal causes the timer output pin (TOCn) to change and an interrupt request signal (INTCCCn0 or INTCCCn1) to be generated at the same time. If the CCCn0 or CCCn1 registers are cleared to 0000H, the 0000H after the TMCn register counts up from FFFFH to 0000H is judged as a match. In this case, the TMCn register value is cleared to 0 at the next count timing, however, this 0000H is not judged as a match. Also, the 0000H when the TMCn register begins counting is not judged as a match. If match clearing is enabled (CCLRCn bit = 1) for the CCCn0 register, the TMCn register is cleared when a match with the TMCn register occurs during a compare operation. Remark n = 0 to 5 Figure 9-6. Compare Operation Example (1/2) (a) When CCLRC0 bit = 1 and CCC00 is other than 0000H Count-up TMC0 n-1 n 0000H 0001H Compare register (CCC00) n TOC0 (output) Match detection (INTCCC00) Remarks 1. The match is detected immediately after the count-up, and the match detection signal is generated. 2. n 0000H User's Manual U16031EJ4V1UD 425 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-6. Compare Operation Example (2/2) (b) When CCLRC0 bit = 1 and CCC00 is 0000H Count-up TMC0 FFFFH 0000H 0000H 0001H Compare register (CCC00) 0000H INTOVC0 TOC0 (output) Match detection (INTCCC00) Remark The match is detected immediately after the count-up, and the match detection signal is generated. 426 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (5) External pulse output Timer C has six timer output pins (TOCn). An external pulse output (TOCn) is generated when a match of the two compare registers (CCCn0 and CCCn1) and the TMCn register is detected. If a match is detected when the TMCn count value and the CCCn0 value are compared, the output level of the TOCn pin is set. Also, if a match is detected when the TMCn count value and the CCCn1 value are compared, the output level of the TOCn pin is reset. The output level of the TOCn pin can be specified by the TMCCn1 register. Remark n = 0 to 5 Table 9-2. TOCn Output Control ENTOCn ALVCn External Pulse Output 0 0 1 0 1 0 Disable Disable Enable High level Low level When the CCCn0 register is matched: low level When the CCCn1 register is matched: high level When the CCCn0 register is matched: high level When the CCCn1 register is matched: low level TOCn Output Output Level 1 1 Enable Remark n = 0 to 5 Figure 9-7. TMC1 Compare Operation Example (Set/Reset Output Mode) CCC10 CCC10 CCC11 TMC1 count value 0 Count start CEC1 1 Interrupt request (INTCCC11) CCC11 CCC11 Clear & start Clear & start Interrupt request (INTCCC10) TOC1 pin ENTOC1 1 ALVC1 0 User's Manual U16031EJ4V1UD 427 CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.7 Application examples (1) Interval timer By setting the TMCCn0 and TMCCn1 registers as shown in Figure 9-8, timer C operates as an interval timer that repeatedly generates interrupt requests with the value that was preset in the CCCn0 register as the interval. When the counter value of the TMCn register matches the setting value of the CCCn0 register, the TMCn register is cleared to 0000H and an interrupt request signal (INTCCCn0) is generated at the same time that the count operation resumes. Remark n = 0 to 5 Figure 9-8. Contents of Register Settings When Timer C Is Used as Interval Timer OVFCn CSCn2 CSCn1 CSCn0 TMCCn0 0/1 0/1 0/1 0/1 0 0 CECn CAECn 1 1 Supply input clocks to internal units Enable count operation OSTCn ENTOCn ALVCn ETICn CCLRCn ECLRCn CMSCn1 CMSCn0 TMCCn1 0 0/1 0/1 0/1 1 0/1 0/1 1 Use CCCn0 register as compare register Clear TMCn register due to match with CCCn0 register Continue counting after TMCn register overflows Remarks 1. 0/1: Set to 0 or 1 as necessary 2. n = 0 to 5 428 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-9. Interval Timer Operation Timing Example t Count clock TMCn register 0000H 0001H Count start p 0000H 0001H Clear p 0000H 0001H Clear p CCCn0 register INTCCCn0 interrupt p p p p Interval time Interval time Interval time Remarks 1. p: Setting value of CCCn0 register (0000H to FFFFH) t: Count clock cycle Interval time = (p + 1) x t 2. n = 0 to 5 User's Manual U16031EJ4V1UD 429 CHAPTER 9 TIMER/COUNTER FUNCTION (2) PWM output By setting the TMCCn0 and TMCCn1 registers as shown in Figure 9-10, timer C can output a PWM signal, whose frequency is determined according to the setting of the CSCn2 to CSCn0 bits of the TMCCn0 register, with the values that were preset in the CCCn0 and CCCn1 registers determining the intervals. When the counter value of the TMCn register matches the setting value of the CCCn0 register, the TOCn output becomes active. Then, when the counter value of the TMCn register matches the setting value of the CCCn1 register, the TOCn output becomes inactive. The TMCn register continues counting. When it overflows, its count value is cleared to 0000H, and the register continues counting. In this way, a PWM signal whose frequency is determined according to the setting of the CSCn2 to CSCn0 bits of the TMCCn0 register can be output. When the setting value of the CCCn0 register and the setting value of the CCCn1 register are the same, the TOCn output remains inactive and does not change. The active level of the TOCn output can be set by the ALVCn bit of the TMCCn1 register. Remark n = 0 to 5 Figure 9-10. Contents of Register Settings When Timer C Is Used for PWM Output OVFCn CSCn2 CSCn1 CSCn0 TMCCn0 0/1 0/1 0/1 0/1 0 0 CECn CAECn 1 1 Supply input clocks to internal units Enable count operation OSTCn ENTOCn ALVCn ETICn CCLRCn ECLRCn CMSCn1 CMSCn0 TMCCn1 0 1 0/1 0/1 0 0/1 1 1 Use CCCn0 register as compare register Use CCCn1 register as compare register Disable clearing of TMCn register due to match with CCCn0 register Enable external pulse output (TOCn) Continue counting after TMCn register overflows Remarks 1. 0/1: Set to 0 or 1 as necessary 2. n = 0 to 5 430 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-11. PWM Output Operation Timing Example t Count clock TMCn register 0000H 0001H Count start p q FFFFH 0000H 0001H Clear p q CCCn0 register CCCn1 register INTCCCn0 interrupt INTCCCn1 interrupt TOCn (output) p p p p p q q q q q Remarks 1. p: Setting value of CCCn0 register (0000H to FFFFH) q: Setting value of CCCn1 register (0000H to FFFFH) pq t: Count clock cycle PWM cycle = 65,536 x t Duty = q-p 65,536 2. In this example, the active level of the TOCn output is set to the high level. 3. n = 0 to 5 User's Manual U16031EJ4V1UD 431 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Cycle measurement By setting the TMCCn0 and TMCCn1 registers as shown in Figure 9-12, timer C can measure the cycle of signals input to the INTPCm0 or INTPCm1 pin. The valid edge of the INTPCm0 pin is selected according to the IESC0m1 and IESC0m0 bits of the SESCm register, and the valid edge of the INTPCm1 pin is selected according to the IESC1m1 and IESC1m0 bits of the SESCm register. Either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins. If the CCCm0 register is set as a capture register, the valid edge input of the INTPCm0 pin is set as the trigger for capturing the TMCm register value in the CCCm0 register. When this value is captured, an INTCCCm0 interrupt is generated. Similarly, if the CCCm1 register is set as a capture register, the valid edge input of the INTPCm1 pin is set as the trigger for capturing the TMCm register value in the CCCm1 register. When this value is captured, an INTCCCm1 interrupt is generated. The cycle of signals input to the INTPCm0 pin is calculated by obtaining the difference between the TMCm register's count value (Dx) that was captured in the CCCm0 register according to the x-th valid edge input of the INTPCm0 pin and the TMCm register's count value (D(x+1)) that was captured in the CCCm0 register according to the (x+1)-th valid edge input of the INTPCm0 pin and multiplying the value of this difference by the cycle of the clock control signal. The cycle of signals input to the INTPCm1 pin is calculated by obtaining the difference between the TMCm register's count value (Dx) that was captured in the CCCm1 register according to the x-th valid edge input of the INTPCm1 pin and the TMCm register's count value (D(x+1)) that was captured in the CCCm1 register according to the (x+1)-th valid edge input of the INTPCm1 pin and multiplying the value of this difference by the cycle of the clock control signal. Remark m = 0 to 3 n = 0 to 5 432 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-12. Contents of Register Settings When Timer C Is Used for Cycle Measurement OVFCn CSCn2 CSCn1 CSCn0 TMCCn0 0/1 0/1 0/1 0/1 0 0 CECn CAECn 1 1 Supply input clocks to internal units Enable count operation OSTCn ENTOCn ALVCn ETICn CCLRCn ECLRCn CMSCn1 CMSCn0 TMCCn1 0 0/1 0/1 0/1 0/1 0 0 0 Use CCCm0 register as capture register (when measuring the cycle of INTPCm0 input) Use CCCm1 register as capture register (when measuring the cycle of INTPCm1 input) Continue counting after TMCm register overflows Remarks 1. 0/1: Set to 0 or 1 as necessary 2. m = 0 to 3 n = 0 to 5 User's Manual U16031EJ4V1UD 433 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-13. Cycle Measurement Operation Timing Example t Count clock TMCm register 0000H 0001H Count start D0 D1 FFFFH 0000H 0001H Clear D2 D3 INTPCm0 (input) CCCm0 register INTCCCm0 interrupt INTOVCm interrupt D0 D1 D2 D3 (D1 - D0) x t No overflow {(10000H - D1) + D2} x tNote Overflow occurs (D3 - D2) x t No overflow Note When an overflow is generated once. Remarks 1. D0 to D3: TMCm register count values t: Count clock cycle 2. In this example, the valid edge of the INTPCm0 input has been set to both edges (rising and falling). 3. m = 0 to 3 434 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.8 Cautions Cautions concerning the timer C are shown below. (1) Conflict between reading CCCm0 register and capture operation If a conflict occurs between the reading of the CCCm0 register and a capture operation when the CCCm0 register is used in capture mode, an external trigger (INTPCm0) valid edge is detected and an external interrupt request (INTCCCm0) is generated, however, the timer value is not stored in the CCCm0 register. (2) Conflict between reading CCCm1 register and capture operation If a conflict occurs between the reading of the CCCm1 register and a capture operation when the CCCm1 register is used in capture mode, an external trigger (INTPCm1) valid edge is detected and an external interrupt request (INTCCCm1) is generated, however, the timer value is not stored in the CCCm1 register. (3) Rewriting during timer operation The following bits and registers must not be rewritten during timer operation (CECn bit of TMCCn0 register = 1). * CSCn2 to CSCn0 bits of TMCCn0 register * TMCCn1 register * SESCm register (4) Register setting when Timer C used The CAECn bit of the TMCCn0 register is a TMCn reset signal. To use TMCn, first set the CAECn bit to 1. (5) Valid edge detection of external interrupt request signals (INTPCm0, INTPCm1), external clock input (TICm) The digital noise elimination time (0 to 5) x fX/4 are required to detect the valid edge of the external interrupt request signal (INTPCm0 or INTPCm1) or the external clock input (TICm). Therefore, edge detection will not be performed normally for changes that are less than the digital noise elimination time. For details of digital noise elimination, see 14.6.3 Timer C and timer ENC1 input pins. (6) Operation of external interrupt request signals (INTCCCn0, INTCCCn1) The operation of an external interrupt request signal (INTCCCn0 or INTCCCn1) is automatically determined according to the operating state of the capture/compare register. When the capture/compare register is used for a capture operation, the external interrupt request signal is used for valid edge detection. When the capture/compare register is used for a compare operation, the external interrupt request signal is used for an interrupt indicating a match with the TMCn register. (7) Glitch generation If the ENTOCn and ALVCn bits of the TMCCn1 register are changed at the same time, a glitch (spike shaped noise) may be generated in the TOCn pin output. Either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ENTOCn and ALVCn bits are not changed at the same time. (8) Alternate-function pins when timer C not used Even when using the INTPC00/TIC0, INTPC10/TIC1, INTPC20/TIC2, and INTPC30/TIC3 pins as INTPC00, INTPC10, INTPC20, and INTPC30, respectively, without using timer C, be sure to set the CAECn and CECn bits of timer mode control registers C00 to C03 (TMCC00 to TMCC30) to 1. User's Manual U16031EJ4V1UD 435 CHAPTER 9 TIMER/COUNTER FUNCTION (9) When used as TICm (external clock input pin) When the INTPCm0/TICm pin is used as TICm (external clock input pin), disable the INTPCm0 interrupt or set CCCm0 to compare mode (m = 0 to 3, n = 0 to 5). (10) Count clock The count clock cannot be changed while the timer is operating. (11) CCC40, CCC41, CCC50, and CCC51 registers The CCC40, CCC41, CCC50, and CCC51 registers can only be used as compare registers. They cannot be used as capture registers. (12) INTPCn0 and INTPCn1 pins when CCCn0 and CCCn1 registers set as compare registers When the CCCn0 and CCCn1 registers are set as compare registers, INTPCn0 and INTPCn1 cannot be used (n = 0 to 5). When using these registers as an external interrupt input pin, use the INTP65 and INTP66 pins. (13) Setting trigger mode Set the PMCx register before setting the trigger mode of the INPTCm0, INTPCm1, and TICm pins (m = 0 to 3, x = 5 to 7). Then set the CAECm and CECm bits of the TMCCm0 register to 1. If the PMCx register is set after the SESCm register has been set, an illegal interrupt, incorrect counting, and incorrect clearing may occur depending on the timing of setting the PMCx register. Remark m = 0 to 3 n = 0 to 5 436 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2 9.2.1 Timer D Features Timer D functions as a 16-bit interval timer. 9.2.2 Function overview * 16-bit interval timer: 4 channels * Compare registers: 4 * Interrupt request sources: 4 sources * Count clock selected from divisions of main clock 9.2.3 Basic configuration Table 9-3. Timer D Configuration Timer Count Clock Register Read/Write Generated Interrupt Signal Timer D fX/8, fX/16, fX/32, fX/64, fX/128, fX/256, fX/512, fX/1,024 TMD1 CMD1 TMD2 CMD2 TMD3 CMD3 Read Read/write Read Read/write Read Read/write - INTCMD1 - INTCMD2 - INTCMD3 - - - - - - - - - - - - TMD0 CMD0 Read Read/write - INTCMD0 - - Capture Trigger Timer Output S/R - - - Clear & start of timer C - - - - - - Other Functions Remark fX: Main clock S/R: Set/reset (1) Timer D (16-bit timer/counter) Figure 9-14. Timer D Block Diagram fX/4 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 TMDn (16 bits) Clear & start CMDn INTCMDn Remarks 1. n = 0 to 3 2. fX: Main clock User's Manual U16031EJ4V1UD 437 CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.4 Timer D (1) Timers D0 to D3 (TMD0 to TMD3) TMDn is a 16-bit timer. It is mainly used as an interval timer for software (n = 0 to 3). Starting and stopping TMDn is controlled by the CEDn bit of the timer mode control register Dn (TMCDn) (n = 0 to 3). Division by the prescaler can be selected for the count clock from among fX/8, fX/16, fX/32, fX/64, fX/128, fX/256, fX/512, and fX/1,024 by the CSDn0 to CSDn2 bits of the TMCDn register (fX: main clock). TMDn is read-only, in 16-bit units. 15 TMD0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF540H After reset 0000H TMD1 FFFFF550H 0000H TMD2 FFFFF560H 0000H TMD3 FFFFF570H 0000H The conditions for which the TMDn register becomes 0000H are shown below (n = 0 to 3). * Reset input * CAEDn bit of TMCDn register = 0 * CEDn bit of TMCDn register = 0 * Match of TMDn register and CMDn register * Overflow Cautions 1. If the CAEDn bit of the TMCDn register is cleared to 0, a reset is performed asynchronously. 2. If the CEDn bit of the TMCDn register is cleared to 0, a reset is performed, in synchronization with the internal clock. Similarly, a synchronized reset is performed after a match with the CMDn register and after an overflow. 3. The count clock must not be changed during a timer operation. If it is to be overwritten, it should be overwritten after the CEDn bit is cleared to 0. 4. Up to 8 main clocks are required after a value is set in the CEDn bit until the set value is transferred to internal units. When a count operation begins, the count cycle from 0000H to 0001H differs from subsequent cycles. 5. After a compare match is generated, the timer is cleared at the next count clock. Therefore, if the division ratio is large, the timer value may not be zero even if the timer value is read immediately after a match interrupt is generated. 6. To initialize the TMDn register and start counting again, set the CEDn bit of the TMCDn register to 1 after 8 main clocks. 438 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Compare registers D0 to D3 (CMD0 to CMD3) CMDn and the TMDn register count value are compared, and an interrupt request signal (INTCMDn) is generated when a match occurs. TMDn is cleared, in synchronization with this match. If the CAEDn bit of the TMCDn register is cleared to 0, a reset is performed asynchronously, and the registers are initialized (n = 0 to 3). The CMDn registers are configured with a master/slave configuration. When a CMDn register is written, data is first written to the master register and then the master register data is transferred to the slave register. In a compare operation, the slave register value is compared with the count value of the TMDn register. When a CMDn register is read, data in the master side is read out. CMDn can be read or written in 16-bit units. Cautions 1. A write operation to a CMDn register requires 8 main clocks until the value that was set in the CMDn register is transferred to internal units. When writing continuously to the CMDn register, be sure to secure a time interval of at least 8 main clocks. 2. The CMDn register can be overwritten only once in a single TMDn register cycle (from 0000H until an INTCMDn interrupt is generated due to a match of the TMDn register and CMDn register). If this cannot be secured by the application, make sure that the CMDn register is not overwritten during timer operation. 3. Note that an INTCMDn interrupt will be generated after an overflow if a value less than the counter value is written in the CMDn register during TMDn register operation (Figure 9-15). 15 CMD0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF542H After reset 0000H CMD1 FFFFF552H 0000H CMD2 FFFFF562H 0000H CMD3 FFFFF572H 0000H User's Manual U16031EJ4V1UD 439 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-15. Example of Timing During TMDn Operation (a) When TMDn < CMDn TMDn M CAEDn CEDn CMDn INTCMDn N N N Remark M = TMDn value when overwritten N = CMDn value when overwritten M TMDn M CAEDn CEDn CMDn INTCMDn N FFFFH N N Remark M = TMDn value when overwritten N = CMDn value when overwritten M>N 440 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.5 Control registers (1) Timer mode control registers D0 to D3 (TMCD0 to TMCD3) The TMCDn registers control the operation of timer Dn (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units. Caution The CAEDn and other bits cannot be set at the same time. The other bits and the registers of the other TMDn units should always be set after the CAEDn bit has been set. (1/2) 7 TMCD0 0 6 CSD02 5 CSD01 4 CSD00 3 0 2 0 <1> <0> Address FFFFF544H After reset 00H CED0 CAED0 TMCD1 0 CSD12 CSD11 CSD10 0 0 CED1 CAED1 FFFFF554H 00H TMCD2 0 CSD22 CSD21 CSD20 0 0 CED2 CAED2 FFFFF564H 00H TMCD3 0 CSD32 CSD31 CSD30 0 0 CED3 CAED3 FFFFF574H 00H Bit position 6 to 4 Bit name CSDn2 to CSDn0 Function Selects the TMDn internal count clock cycle. CSDn2 0 0 0 0 1 1 1 1 CSDn1 0 0 1 1 0 0 1 1 CSDn0 0 1 0 1 0 1 0 1 fX/8 fX/16 fX/32 fX/64 fX/128 fX/256 fX/512 fX/1,024 Count cycle Caution The CSDn2 to CSDn0 bits must not be changed during timer operation. If they are to be changed, they must be changed after setting the CEDn bit to 0. If these bits are overwritten during timer operation, operation cannot be guaranteed. Remark fX: Main clock 1 CEDn Controls the operation of TMDn. 0: Count disabled (stops at 0000H and does not operate) 1: Counting operation is performed Caution The CEDn bit is not cleared even if a match is detected by the compare operation. To stop the count operation, clear the CEDn bit. Remark n = 0 to 3 User's Manual U16031EJ4V1UD 441 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 0 Bit name CAEDn Controls the internal count clock. 0: The entire TMDn unit is reset asynchronously. The supply of input clocks to the TMDn unit stops. 1: Input clocks are supplied to the TMDn unit. Cautions 1. When the CAEDn bit is cleared to 0, the TMDn unit can be asynchronously reset. 2. When CAEDn = 0, the TMDn unit is in a reset state. Therefore, to operate TMDn, the CAEDn bit must be set to 1. 3. If the CAEDn bit is cleared to 0, all the registers of the TMDn unit are initialized. If CAEDn is set to 1 again, be sure all the registers of the TMDn unit have been set again. Function Remark n = 0 to 3 442 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.6 Operation (1) Compare operation TMDn can be used for a compare operation in which the value that was set in a compare register (CMDn) is compared with the TMDn count value (n = 0 to 3). If a match is detected by the compare operation, an interrupt (INTCMDn) is generated. The generation of the interrupt causes TMDn to be cleared to 0 at the next count timing. This function enables timer D to be used as an interval timer. CMDn can also be cleared to 0. In this case, when an overflow occurs and TMDn becomes 0, a match is detected and INTCMDn is generated. Although the TMDn value is cleared to 0 at the next count timing, INTCMDn is not generated by this match. Figure 9-16. TMD0 Compare Operation Example (1/2) (a) When CMD0 is set to n (non-zero) Count clock Count up TMD0 clear Clear TMD0 n 0 1 CMD0 n Match detected (INTCMD0) Remark Interval time = (n + 1) x (Count clock cycle) n = 1 to 65,536 (FFFFH) User's Manual U16031EJ4V1UD 443 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-16. TMD0 Compare Operation Example (2/2) (b) When CMD0 is cleared to 0 Count clock Count up TMD0 clear Clear TMD0 FFFFH 0 0 1 CMD0 0 Match detected (INTCMD0) Overflow Remark Interval time = (FFFFH + 2) x (Count clock cycle) 444 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.7 Application examples (1) Interval timer This section explains an example in which timer D is used as an interval timer with 16-bit precision. Interrupt requests (INTCMDn) are output at equal intervals (see Figure 9-16 TMD0 Compare Operation Example). The setup procedure is shown below (n = 0 to 3). <1> Set the CAEDn bit of the TMCDn register to 1. <2> Set each register. * Select the count clock using the CSDn0 to CSDn2 bits of the TMCDn register. * Set the compare value in the CMDn register. <3> Start counting by setting the CEDn bit of the TMCDn register to 1. <4> If the TMDn register and CMDn register values match, an INTCMDn interrupt is generated. <5> INTCMDn interrupts are generated thereafter at equal intervals. Remark 9.2.8 Cautions n = 0 to 3 Cautions concerning the timer D are shown below. (1) Starting timer D operation To operate TMDn, first set the CAEDn bit of the TMCDn register to 1. (2) Caution on setting TMCDn register Up to 8 main clocks are required after a value is set in the CEDn bit until the set value is transferred to internal units. When a count operation begins, the count cycle from 0000H to 0001H differs from subsequent cycles. (3) Recount after TMDn register initialization To initialize the TMDn register status and start counting again, clear the CEDn bit to 0 and then set the CEDn bit to 1 after an interval of 8 main clocks has elapsed. (4) Caution on setting CMDn register Up to 8 main locks are required until the value that was set in the CMDn register is transferred to internal units. When writing continuously to the CMDn register, be sure to secure a time interval of at least 8 main clocks. * The CMDn register can be overwritten only once during a timer/counter operation (from 0000H until an INTCMDn interrupt is generated due to a match of the TMDn register and CMDn register). If this cannot be secured, make sure that the CMDn register is not overwritten during a timer/counter operation. (5) Count clock The count clock must not be changed during a timer operation. operation cannot be guaranteed. (6) Writing to CMDn register A match signal will be generated after an overflow if a value less than the counter value is written in the CMDn register during TMDn register operation. Remark n = 0 to 3 User's Manual U16031EJ4V1UD If it is to be overwritten, it should be overwritten after the CEDn bit is cleared to 0. If the count clock is overwritten during a timer operation, 445 CHAPTER 9 TIMER/COUNTER FUNCTION 9.3 9.3.1 16-Bit 2-Phase Encoder Input Up/Down Counter/General-Purpose Timer (Timer ENC1) Functions Timers ENC10 and ENC11 (TMENC10, TMENC11) perform the following operations. * General-purpose timer mode (See 9.3.6 (1) Operation in general-purpose timer mode.) Free-running timer Timer output * Up/down counter mode (See 9.3.6 (2) Operation in UDC mode.) UDC mode A (mode 1, mode 2, mode 3, mode 4) UDC mode B (mode 1, mode 2, mode 3, mode 4) 9.3.2 Features Timers ENC10 and ENC11: 2 channels Compare registers: 4 Capture/compare registers: 4 Interrupt request sources * Capture/compare match interrupt: 4 sources * Compare match interrupt request: 4 sources * * * * * Capture request signal: 4 sources * The TMENC1n value can be latched using the valid edge of the INTP1n0 and INTP1n1 pins corresponding to the capture/compare register as the capture trigger. * Count clock selectable through division by prescaler * Timer output function In the general-purpose timer mode, 16-bit resolution timer can be output from the TO1n pin. * Timer clear The following timer clear operations are performed according to the mode that is used. (a) General-purpose timer mode: Timer clear operation is possible upon occurrence of match with the CM1n0 register set value. (b) Up/down counter mode: The timer clear operation can be selected from among the following four conditions. (i) Timer clear performed upon occurrence of match with the CM1n0 register set value during TMENC1n up-count operation, and timer clear performed upon occurrence of match with the CM1n1 register set value during TMENC1n down-count operation. (ii) Timer clear performed only by external input. (iii) Timer clear performed upon occurrence of match between TMENC1n count value and the CM1n0 register set value. (iv) Timer clear performed upon occurrence of external input and match between TMENC1n count value and the CM1n0 register set value. * External pulse output (TO1n): 2 446 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.3 Basic configuration Table 9-4. Timer ENC1 Configuration Timer Count Clock Register Read/Write Generated Interrupt Request Signal Timer ENC1 fX/8, fX/16, fX/32, fX/64, fX/128, fX/256, fX/512 CM101 CC100 CC101 TMENC11 CM110 CM111 CC110 CC111 Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write INTCM101 INTCC100 INTCC101 - INTCM110 INTCM111 INTCC110 INTCC111 TMENC10 CM100 Read/write Read/write - INTCM100 Capture Trigger - - - INTP100 INTP101 - - - INTP110 INTP111 Remark fX: Main clock User's Manual U16031EJ4V1UD 447 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer ENC1 (16-bit up/down counter) Figure 9-17. Timer ENC1 Block Diagram Internal bus Timer unit mode register 1n (TUM1n) T1CMDn TOE1n0 ALVT1n0 MSELn Selector INTP1n0/ INTCC1n0 Selector INTP1n1/ INTCC1n1 INTP1n1/ TCLR1n Edge detector NCC1n NCC0n Edge detector Edge detector Edge detector Edge detector CC1n0 CC1n1 Selector INTP1n0/ TCUD1n Selector TIUD1n Noise filter Noise filter Noise filter TCLR Clear TMENC1n (16 bits) TMENC1n clear controller Clock division & selector INTOV1n INTUD1n fX/4 fX/32 Selector fX/4 1/2 1/4 1/8 1/16 1/32 1/64 1/128 CM1n0 CM1n1 S R Note Q Q Selector TO1n INTCM1n0 SRTCn SRTIn NCFn NCC1n NCC0n CE1n1 RLEN1n ENMD1n CLR1n1 CLR1n0 Timer control register 1n (TMC1n) Noise elimination width setting register 1n (NCW1n) INTCM1n1 Internal bus Note Reset priority Remark fX: Main clock 448 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.4 Timer ENC1 (1) Timers ENC10, ENC11 (TMENC10, TMENC11) TMENC1n is a general-purpose timer (in general-purpose mode) and 2-phase encoder input up/down counter (in UDC mode). This timer counts up in the general-purpose operation mode and counts up/down in the UDC mode. It can be read or written in 16-bit units. Cautions 1. Writing to TMENC1n is enabled only when the CE1n1 bit of the TMC1n register is 0 (count operation disabled). 2. Continuous reading of TMENC1n is prohibited. If TMENC1n is continuously read, the second read value may differ from the actual value. If TMENC1n must be read twice, be sure to read another register between the first and the second read operation. 3. Writing the same value to the TMENC1n register is prohibited. 15 TMENC10 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5A0H After reset 0000H TMENC11 FFFFF5D0H 0000H TMENC1n start and stop is controlled by the CE1n1 bit of timer control register 1n (TMC1n). The TMENC1n operation consists of the following two modes. (a) General-purpose timer mode In the general-purpose timer mode, TMENC1n operates as a 16-bit interval timer, free-running timer, or timer output. Counting is performed based on the count clock selected by software. Division by the prescaler can be selected for the count clock from among fX/8, fX/16, fX/32, fX/64, fX/128, fX/256, or fX/512 using the PRM1n2 to PRM1n0 bits of prescaler mode register 1n (PRM1n) (fX: main clock). User's Manual U16031EJ4V1UD 449 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Up/down counter mode (UDC mode) In the UDC mode, TMENC1n functions as a 16-bit up/down counter that performs counting based on the TCUD1n and TIUD1n input signals. This mode is divided into the UDC A mode and UDC B mode, depending on the condition of clearing TMENC1n. Cautions 1. The TCUD1n and INTP1n0 pins function alternately. pin cannot be used. 2. The TCLR1n and INTP1n1 pins function alternately. Therefore, when the TCLR1n input is used in UDC mode A, the external capture function of the INTP1n1 pin cannot be used. The conditions for clearing TMENC1n are as follows, depending on the operation mode. Table 9-5. Timer ENC1 (TMENC1n) Clear Conditions Operation Mode TUM1n Register TMC1n Register TMENC1n Clear Therefore, because the TCUD1n pin is used in the UDC mode, the external capture function of the INTP1n0 T1CMDn MSELn ENMD1n CLR1n1 CLR1n0 Bit General-purpose timer mode UDC mode A 1 0 0 Bit 0 Bit 0 1 x x x x UDC mode B 1 1 x Bit x x 0 0 Bit x x 0 1 Clearing not performed (free-running timer) Cleared upon match with CM1n0 set value Cleared only by TCLR1n input Cleared upon match with CM1n0 set value during upcount operation Cleared by TCLR1n input or upon match with CM1n0 set value during up-count operation Clearing not performed Cleared upon match with CM1n0 set value during upcount operation or upon match with CM1n1 set value during down-count operation Other than the above Setting prohibited 1 0 1 x 1 x Remark x: Indicates that the set value of that bit is ignored. 450 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.5 Control registers (1) Timer unit mode registers 10, 11 (TUM10, TUM11) The TUM1n register is an 8-bit register used to specify the TMENC1n operation mode or to control the operation of the timer output pin. TUM1n can be read or written in 8-bit or 1-bit units. Cautions 1. Changing the value of the TUM1n register during TMENC1n operation (CE1n1 bit of TMC1n register = 1) is prohibited. 2. It is prohibited to set the MSELn bit (UDC mode B) to 1 when the T1CMDn bit is cleared to 0 (general-purpose timer mode). 3. Writing the same value to the TUM1n register is permitted (writing the same value is guaranteed even during a count operation). 7 TUM10 T1CMD0 6 0 5 0 4 0 3 2 1 0 0 MSEL0 Address FFFFF5ABH After reset 00H TOE100 ALVT100 TUM11 T1CMD1 0 0 0 TOE110 ALVT110 0 MSEL1 FFFFF5DBH 00H Bit position 7 Bit name T1CMDn Specifies TMENC1n operation mode. Function 0: General-purpose timer mode (up count) 1: UDC mode (up/down count) 3 TOE1n0 Specifies timer output (TO1n) enable. 0: Timer output disabled 1: Timer output enabled Caution When T1CMDn bit = 1 (UDC mode), timer output is not performed regardless of the setting of the TOE1n0 bit. At this time, timer output consists of the negative phase level of the level set by the ALVT1n0 bit. 2 ALVT1n0 Specifies active level of timer output (TO1n). 0: Active level is high level 1: Active level is low level Caution When T1CMDn bit = 1 (UDC mode), timer output is not performed regardless of the setting of the TOE1n0 bit. At this time, timer output consists of the negative phase level of the level set by the ALVT1n0 bit. 0 MSELn Specifies operation in UDC mode (up/down count) 0: UDC mode A TMENC1n can be cleared by setting the CLR1n1 and CLR1n0 bits of the TMC1n register. 1: UDC mode B TMENC1n is cleared in the following cases. * Upon match with the CM1n0 register during TMENC1n up-count operation * Upon match with the CM1n1 register during TMENC1n down-count operation Caution When the T1CMDn bit = 0 (general-purpose timer mode), setting MSELn bit = 1 (UDC mode B) is prohibited. When UDC mode B is set, the ENMD1n, CLR1n1, and CLR1n0 bits of the TMC1n register become invalid. Remark n = 0, 1 User's Manual U16031EJ4V1UD 451 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer control registers 10, 11 (TMC10, TMC11) The TMC1n register is used to enable/disable TMENC1n operation and to set transfer and timer clear operations. TMC1n can be read or written in 8-bit or 1-bit units. Cautions 1. Changing the values of the TMC1n register bits other than the CE1n1 bit during TMENC1n operation (CE1n1 bit = 1) is prohibited. 2. Writing the same value to the TMC1n register is permitted (writing the same value is guaranteed even during a count operation). (1/2) 7 TMC10 0 <6> CE101 5 0 4 0 3 2 1 0 CLR100 Address FFFFF5ACH After reset 00H RLEN10 ENMD10 CLR101 TMC11 0 CE111 0 0 RLEN11 ENMD11 CLR111 CLR110 FFFFF5DCH 00H Bit position 6 Bit name CE1n1 Enables/disables TMENC1n operation. Function 0: TMENC1n count operation disabled 1: TMENC1n count operation enabled 3 RLEN1n Enables/disables transfer from the CM1n0 register to TMENC1n in UDC mode A. 0: Transfer disabled 1: Transfer enabled Cautions 1. When the RLEN1n bit = 1, the value set to the CM1n0 register is transferred to TMENC1n upon occurrence of a TMENC1n underflow. 2. The RLEN1n bit is valid only in UDC mode A (TUM1n register's T1CMDn bit = 1, MSELn bit = 0). In the general-purpose timer mode (T1CMDn bit = 0) and in UDC mode B (T1CMDn bit = 1, MSELn bit = 1), a transfer operation is not performed even the RLEN1n bit is set to 1. 2 ENMD1n Enables/disables clearing of TMENC1n in general-purpose timer mode (T1CMDn bit of TUM1n register = 0). 0: Clear disabled (free-running mode) Clearing is not performed even when the TMENC1n and CM1n0 register values match. 1: Clear enabled Clearing is performed when the TMENC1n and CM1n0 register values match. Caution The ENMD1n bit setting becomes invalid in UDC mode (T1CMDn bit of TUM1n register = 1). Remark n = 0, 1 452 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 1, 0 Bit name CLR1n1, CLR1n0 Function Controls TMENC1n clear operation in UDC mode A. CLR1n1 0 0 CLR1n0 0 1 Specifies TMENC1n clear source Cleared only by external input (TCLR1n) Cleared upon match of TMENC1n count value and the CM1n0 register set value 1 0 Cleared by TCLR1n input or upon match of TMENC1n count value and the CM1n0 register set value 1 1 Not cleared Cautions 1. Clearing by match of the TMENC1n count value and the CM1n0 register set value is valid only during a TMENC1n up-count operation (TMENC1n is not cleared during a TMENC1n down-count operation). 2. The CLR1n1 and CLR1n0 bit settings are invalid in general-purpose timer mode (T1CMDn bit of TUM1n register = 0). 3. The CLR1n1 and CLR1n0 bit settings are invalid in UDC mode B (MSELn bit of TUM1n register = 1). 4. When clearing by TCLR1n has been enabled by the CLR1n1 and CLR1n0 bits, clearing is performed whether the value of the CE1n1 bit is 1 or 0. Remark n = 0, 1 User's Manual U16031EJ4V1UD 453 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Capture/compare control registers 10, 11 (CCR10, CCR11) The CCR1n register specifies the operation mode of the CC1n0 and CC1n1 registers. CCR1n can be read or written in 8-bit or 1-bit units. Cautions 1. Overwriting the CCR1n register during TMENC1n operation (CE1n1 bit of TMC1n register = 1) is prohibited. 2. The TCUD1n and INTP1n0 pins function alternately. Therefore, because the TCUD1n pin is used in the UDC mode, the external capture function of the INTP1n0 pin cannot be used. 3. The TCLR1n and INTP1n1 pins function alternately. Therefore, when the TCLR1n input is used in UDC mode A, the external capture function of the INTP1n1 pin cannot be used. 4. Writing the same value to the CCR1n register is permitted (writing the same value is guaranteed even during a count operation). 7 CCR10 0 6 0 5 0 4 0 3 0 2 0 1 CMS01 0 CMS00 Address FFFFF5AAH After reset 00H CCR11 0 0 0 0 0 0 CMS11 CMS10 FFFFF5DAH 00H Bit position 1 Bit name CMSn1 Function Specifies operation mode of the CC1n1 register. 0: Capture register 1: Compare register 0 CMSn0 Specifies operation mode of the CC1n0 register. 0: Capture register 1: Compare register Remark n = 0, 1 454 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (4) Valid edge select registers 10, 11 (SESA10, SESA11) The SESA1n register is used to specify the valid edge of external interrupt request signals from external pins (INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11). The valid edge (rising edge, falling edge, or both rising and falling edges) can be specified independently for each pin. SESA1n can be read or written in 8-bit or 1-bit units. Cautions 1. Changing the values of the SESA1n register bits during TMENC1n operation (CE1n1 bit of TMC1n register = 1) is prohibited. 2. Set the PMCDH register before setting the trigger mode of the INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11 pins. If the PMCDH register is set after the SESA1n register has been set, an illegal interrupt, incorrect counting, and incorrect clearing may occur depending on the timing of setting the PMCDH register. 3. Writing the same value to the SESA1n register is permitted (writing the same value is guaranteed even during a count operation). (1/2) 7 6 5 4 3 2 IES100 1 IES001 0 IES000 Address FFFFF5ADH After reset 00H SESA10 TESUD01 TESUD00 CESUD01 CESUD00 IES101 TIUD10, TCUD10 7 6 5 TCLR10 4 3 IES111 INTP101 2 IES110 1 INTP100 0 IES010 Address FFFFF5DDH After reset 00H SESA11 TESUD11 TESUD10 CESUD11 CESUD10 TIUD11, TCUD11 TCLR11 IES011 INTP111 INTP110 Bit position 7, 6 Bit name TESUDn1, TESUDn0 Function Specifies valid edge of pins TIUD1n, TCUD1n. TESUDn1 0 0 1 1 TESUDn0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge Cautions 1. The setting of the TESUDn1 and TESUDn0 bits are only valid in UDC mode A and UDC mode B. 2. If mode 4 is specified as the operation mode of TMENC1n (specified by the PRM1n2 to PRM1n0 bits of the PRM1n register), the valid edge specifications for the TIUD1n and TCUD1n pins (bits TESUDn1 and TESUDn0) are not valid. Remark n = 0, 1 User's Manual U16031EJ4V1UD 455 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 5, 4 Bit name CESUDn1, CESUDn0 Specifies valid edge of TCLR1n pin. CESUDn1 0 0 1 1 CESUDn0 0 1 0 1 Falling edge Rising edge Low level High level Valid edge Function The set values of bits CESUDn1 and CESUDn0 and the TMENC1n operation are related as follows. 00: TMENC1n cleared after detection of rising edge of TCLR1n 01: TMENC1n cleared after detection of falling edge of TCLR1n 10: TMENC1n cleared status held while TCLR1n input is low level 11: TMENC1n cleared status held while TCLR1n input is high level Caution The setting of the CESUDn1 and CESUDn0 bits are valid only in UDC mode A. 3, 2 IES1n1, IES1n0 Specifies valid edge of INTP1n1 pin. IES1n1 0 0 1 1 IES1n0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge 1, 0 IES0n1, IES0n0 Specifies valid edge of INTP1n0 pin. IES0n1 0 0 1 1 IES0n0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge Remark n = 0, 1 456 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (5) Prescaler mode registers 10, 11 (PRM10, PRM11) The PRM1n register is used to perform the following selections. * Selection of count clock in general-purpose timer mode (T1CMDn bit of TUM1n register = 0) * Selection of count operation mode in UDC mode (T1CMDn bit = 1) PRM1n can be read or written in 8-bit or 1-bit units. Cautions 1. Overwriting the PRM1n register during TMENC1n operation (CE1n1 bit of TMC1n register = 1) is prohibited. 2. Clearing the PRM1n2 bit to 0 is prohibited in UDC mode (T1CMDn bit of TUM1n register = 1). 3. When TMENC1n is in mode 4, specification of the valid edge for the TIUD1n and TCUD1n pins is invalid. 4. Writing the same value to the PRM1n register is permitted (writing the same value is guaranteed even during a count operation). 7 PRM10 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFFF5AEH After reset 07H PRM102 PRM101 PRM100 PRM11 0 0 0 0 0 PRM112 PRM111 PRM110 FFFFF5DEH 07H Bit position 2 to 0 Bit name PRM1n2 to PRM1n0 Function Specifies the up-/down-count operation mode during input of the clock rate when the internal clock of the TMENC1n is used, or during external clock (TIUD1n) input. PRM1n2 PRM1n1 PRM1n0 T1CMDn = 0 Count clock 0 0 0 Setting prohibited 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 fX/8 fX/16 fX/32 fX/64 fX/128 fX/256 fX/512 TIUD1n Mode 1 Mode 2 Mode 3 Mode 4 T1CMDn = 1 Count clock Setting prohibited UDC mode Remark fX: Main clock Remark n = 0, 1 User's Manual U16031EJ4V1UD 457 CHAPTER 9 TIMER/COUNTER FUNCTION (a) In general-purpose timer mode (T1CMDn bit of TUM1n register = 0) The count clock is specified by the PRM1n2 to PRM1n0 bits. (b) UDC mode (T1CMDn bit of TUM1n register = 1) The TMENC1n count triggers in the UDC mode are as follows. Operation Mode Mode 1 TMENC1n Operation Down count upon detection of valid edge of TIUD1n input when TCUD1n = high level Up count upon detection of valid edge of TIUD1n input when TCUD1n = low level Up count upon detection of valid edge of TIUD1n input Down count upon detection of valid edge of TCUD1n input Mode 3 Up count upon detection of valid edge of TIUD1n input when TCUD1n = high level Down count upon detection of valid edge of TIUD1n input when TCUD1n = low level Mode 4 Automatic judgment upon detection of both edges of TIUD1n input and both edges of TCUD1n input Mode 2 458 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (6) Status registers 10, 11 (STATUS10, STATUS11) The STATUS1n register indicates the operating status of TMENC1n. STATUS1n is read-only, in 8-bit or 1-bit units. Caution Writing the same value to the STATUS1n register is prohibited. 7 STATUS10 0 6 0 5 0 4 0 3 0 <2> UDF10 <1> OVF10 <0> UBD10 Address FFFFF5AFH After reset 00H STATUS11 0 0 0 0 0 UDF11 OVF11 UBD11 FFFFF5DFH 00H Bit position 2 Bit name UDF1n TMENC1n underflow flag 0: No TMENC1n count underflow 1: TMENC1n count underflow Function Caution The UDF1n bit is cleared to 0 upon completion of a read access to the STATUS1n register from the CPU. 1 OVF1n TMENC1n overflow flag 0: No TMENC1n count overflow 1: TMENC1n count overflow Caution The OVF1n bit is cleared to 0 upon completion of a read access to the STATUS1n register from the CPU. 0 UBD1n Indicates the operating status of TMENC1n up/down count. 0: TMENC1n up count in progress 1: TMENC1n down count in progress Caution The state of the UBD1n bit differs according to the mode as follows. * The UBD1n bit is fixed to 0 in general-purpose timer mode (T1CMDn bit of TUM1n register = 0). * The UBD1n bit indicates the TMENC1n up-/down-count status in UDC mode B (MSELn bit of TUM1n register = 1). Remark n = 0, 1 User's Manual U16031EJ4V1UD 459 CHAPTER 9 TIMER/COUNTER FUNCTION (7) Noise elimination width setting registers 10, 11 (NCW10, NCW11) The NCW1n register is used to set the noise elimination width of the digital noise filter of the timer ENC1 input pin. NCW1n can be read or written in 8-bit units. Cautions 1. Whether the signal is input through or inverted can be specified for each of the INTP1n0/TCUD1n and TIUD1n pins. The setting of the noise elimination width by the NCFn, NCC1n, and NCC0n bits is for each timer and cannot be changed for each pin. 2. The setting of the SRTCn bit is valid even when the INTP1n0/TCUD1n pin is used as a capture trigger (INTP1n0). 7 NCW10 0 6 0 5 SRTC0 4 SRTI0 3 0 2 NCF0 1 NCC10 0 NCC00 Address FFFFF5C0H After reset 02H NCW11 0 0 SRTC1 SRTI1 0 NCF1 NCC11 NCC01 FFFFF5F0H 02H Bit position 5 Bit name SRTCn Function Sets the input mode of the INTP1n0/TCUD1n pin. 0: Through input 1: Inverted This bit specifies whether the signal input from the INTP1n0/TCUD1n pin is input through to TMENC1n or inverted. 4 SRTIn Sets the input mode of the TIUD1n pin. 0: Through input 1: Inverted This bit specifies whether the signal input from the TIUD1n pin is input through to TMENC1n or inverted. 2 NCFn Specifies the clock frequency for noise elimination. 0: fX/4 1: fX/32 This bit selects the clock source of the noise filter. 1, 0 NCC1n, NCC0n Specify the number of clocks by which noise is to be eliminated. NCC1n 0 0 1 1 Note 1 NCC0n 0 1 0 1 Note 1 Number of clocks by which noise is to be eliminated 0 (through input) 2 3 7 Note 2 Notes 1. Do not overwrite this bit during a count operation. 2. Clear the NCFn bit to 0 for through input. These bits select the number of clocks by which noise is to be eliminated. Remark n = 0, 1 460 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (a) Relationship between NCW1n register set value and noise elimination width Table 9-6. Relationship Between NCW1n Register Set Value and Noise Elimination Width NCW1n Register NCFn Bit 0 0 0 0 1 1 1 NCC1n Bit 0 0 1 1 0 1 1 NCC0n Bit 0 1 0 1 1 0 1 Noise Elimination Width (ns) fX = 150 MHz 0 53.3 to 80.0 80.0 to 106.7 133.3 to 160.0 426.7 to 640.0 640.0 to 853.3 fX = 133 MHz 0 60.2 to 90.2 90.2 to 120.3 150.4 to 180.5 481.2 to 721.8 721.8 to 962.9 fX = 100 MHz 0 80 to 120 120 to 160 200 to 240 640 to 960 960 to 1,280 1,600 to 1,920 Through (1/(fX/4)) x 2 (1/(fX/4)) x 3 (1/(fX/4)) x 5 (1/(fX/32)) x 2 (1/(fX/32)) x 3 (1/(fX/32)) x 5 Remark 1,066.7 to 1,280.0 1,203.0 to 1,443.6 Remarks 1. n = 0, 1 2. fX: Main clock (8) Compare registers 100, 110 (CM100, CM110) The CM1n0 register is a 16-bit register that always compares its value with the value of TMENC1n. When the value of a compare register matches the value of TMENC1n, an interrupt request signal is generated. The CM1n0 register can be read or written in 16-bit units. The interrupt request signal generation timing in the various modes is described below. * In the general-purpose timer mode (T1CMDn bit of TUM1n register = 0) and UDC mode A (MSELn bit of TUM1n register = 0), an interrupt request signal (INTCM1n0) is generated upon occurrence of a match. * In UDC mode B (MSELn bit of TUM1n register = 1), an interrupt request signal (INTCM1n0) is generated only upon occurrence of a match during an up-count operation. Cautions 1. When the CE1n1 bit of the TMC1n register is 1, it is prohibited to overwrite the value of the CM1n0 register. 2. Writing the same value to the CM1n0 register is permitted (writing the same value is guaranteed even during a count operation). 15 CM100 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5A2H After reset 0000H CM110 FFFFF5D2H 0000H User's Manual U16031EJ4V1UD 461 CHAPTER 9 TIMER/COUNTER FUNCTION (9) Compare registers 101, 111 (CM101, CM111) The CM1n1 register is a 16-bit register that always compares its value with the value of TMENC1n. When the value of the compare register matches the value of TMENC1n, an interrupt request signal is generated. The CM1n1 register can be read or written in 16-bit units. The interrupt request signal generation timing in the various modes is described below. * In the general-purpose timer mode (T1CMDn bit of TUM1n register = 0) and UDC mode A (MSELn bit of TUM1n register = 0), an interrupt request signal (INTCM1n1) is generated upon occurrence of a match. * In UDC mode B (MSELn bit of TUM1n register = 1), an interrupt request signal (INTCM1n1) is generated only upon occurrence of a match during a down-count operation. Cautions 1. When the CE1n1 bit of the TMC1n register is 1, it is prohibited to overwrite the value of the CM1n1 register. 2. Writing the same value to the CM1n1 register is permitted (writing the same value is guaranteed even during a count operation). 15 CM101 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5A4H After reset 0000H CM111 FFFFF5D4H 0000H 462 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (10) Capture/compare registers 100, 110 (CC100, CC110) The CC1n0 register is a 16-bit register. It can be specified as a capture register or as a compare register using the CCR1n register. CC1n0 can be read or written in 16-bit units. Cautions 1. When used as a capture register (CMSn0 bit of CCR1n register = 0), write access is prohibited. 2. When used as a compare register (CMSn0 bit of CCR1n register = 1) during TMENC1n operation (CE1n1 bit of TMC1n register = 1), overwriting the CC1n0 register values is prohibited. 3. When TMENC1n has been stopped (CE1n1 bit of TMC1n register = 0), the capture trigger is disabled. 4. When the operation mode is changed from capture register to compare register, set a new compare value. 5. Continuous reading of the CC1n0 register is prohibited. If the CC1n0 register is continuously read, the second read value may differ from the actual value. If the CC1n0 register must be read twice, be sure to read another register between the first and the second read operation. 6. Writing the same value to the CC1n0 register is prohibited. 15 CC100 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5A6H After reset 0000H CC110 FFFFF5D6H 0000H (a) When set as a capture register When the CC1n0 register is set as a capture register, the valid edge of the corresponding external interrupt request signal (INTP1n0) is detected as the capture trigger. TMENC1n latches the count value in synchronization with the capture trigger (capture operation). The latched value is held in the capture register until the next capture operation. The valid edge of external interrupt request signals (rising edge, falling edge, both rising and falling edges) is selected by the SESA1n register. When the CC1n0 register is specified as a capture register, interrupt request signals are generated upon detection of the valid edge of the INTP1n0 signal. Caution The TCUD1n and INTP1n0 pins function alternately. Therefore, because the TCUD1n pin is used in the UDC mode, the external capture function of the INTP1n0 pin cannot be used. (b) When set as a compare register When the CC1n0 register is set as a compare register, it always compares its own value with the value of the TMENC1n register. If the value of the CC1n0 register matches the value of the TMENC1n register, the CC1n0 register generates an interrupt request signal (INTCC1n0). User's Manual U16031EJ4V1UD 463 CHAPTER 9 TIMER/COUNTER FUNCTION (11) Capture/compare registers 101, 111 (CC101, CC111) The CC1n1 register is a 16-bit register. It can be specified as a capture register or as a compare register using the CCR1n register. The CC1n1 register can be read or written in 16-bit units. Cautions 1. When used as a capture register (CMSn1 bit of CCR1n register = 0), write access is prohibited. 2. When used as a compare register (CMSn1 bit of CCR1n register = 1) during TMENC1n operation (CE1n1 bit of TMC1n register = 1), overwriting the CC1n1 register values is prohibited. 3. When TMENC1n has been stopped (CE1n1 bit of TMC1n register = 0), the capture trigger is disabled. 4. When the operation mode is changed from capture register to compare register, newly set a compare value. 5. Continuous reading of the CC1n1 register is prohibited. If the CC1n1 register is continuously read, the second read value may differ from the actual value. If the CC1n1 register must be read twice, be sure to read another register between the first and the second read operation. 6. Writing the same value to the CC1n1 register is prohibited. 15 CC101 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5A8H After reset 0000H CC111 FFFFF5D8H 0000H (a) When set as a capture register When the CC1n1 register is set as a capture register, the valid edge of the corresponding external interrupt request signal (INTP1n1) is detected as the capture trigger. TMENC1n latches the count value in synchronization with the capture trigger (capture operation). The latched value is held in the capture register until the next capture operation. The valid edge of external interrupt request signals (rising edge, falling edge, both rising and falling edges) is selected by the SESA1n register. When the CC1n1 register is specified as a capture register, interrupts are generated upon detection of the valid edge of the INTP1n1 signal. Caution The TCLR1n and INTP1n1 pins function alternately. Therefore, when the TCLR1n input is used in UDC mode A, the external capture function of the INTP1n1 pin cannot be used. (b) When set as a compare register When the CC1n1 register is set as a compare register, it always compares its own value with the value of the TMENC1n register. If the value of the CC1n1 register matches the value of the TMENC1n register, the CC1n1 register generates an interrupt request signal (INTCC1n1). 464 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.6 Operation (1) Operation in general-purpose timer mode TMENC1n can perform the following operations in the general-purpose timer mode. (a) Interval operation (when TMC1n.ENMD1n0 bit = 1) TMENC1n and the CM1n0 register always compare their values and the INTCM1n0 interrupt request signal is generated upon occurrence of a match. TMENC1n is cleared to 0000H at the count clock following the match. Furthermore, when one more count clock is input, TMENC1n counts up to 0001H. The interval time can be calculated with the following formula. Interval time = (CM1n0 register value + 1) x TMENC1n count clock rate (b) Free-running operation (when TMC1n.ENMD1n0 bit = 0) TMENC1n fully counts from 0000H to FFFFH, is cleared to 0000H at the next count clock after the STATUS1n.OVF1n bit has been set (1), and continues counting. calculated by the following formula. Free-running cycle = 65,536 x TMENC1n count clock rate (c) Compare function TMENC1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register (CC1n0, CC1n1) channels. When the TMENC1n count value and the set value of one of the compare registers match, a match interrupt request signal (INTCM1n0, INTCM1n1, INTCC1n0Note, INTCC1n1Note) is output. Particularly in the case of interval operation, TMENC1n is cleared upon generation of the INTCM1n0 interrupt. Note This match interrupt request signal is generated when the CC1n0 and CC1n1 registers are set to the compare register mode. (d) Capture function TMENC1n connects two capture/compare register (CC1n0, CC1n1) channels. When the CC1n0 and CC1n1 registers are set to the capture register mode, the value of TMENC1n is captured in synchronization with the corresponding capture trigger signal (INTP1n0, INTP1n1). Furthermore, an interrupt request signal (INTCC1n0, INTCC1n1) is generated by the valid edge of the INTP1n0, INTP1n1 input signals specified as the capture trigger signals. The free-running cycle can be User's Manual U16031EJ4V1UD 465 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-7. Capture Trigger Signal (TMENC1n) to 16-Bit Capture Register Capture Register CC1n0 CC1n1 Capture Trigger Signal INTP1n0 INTP1n1 Remark The CC1n0 and CC1n1 registers are capture/compare registers. Which of these registers is used is specified by the CCR1n register. The valid edge of the capture trigger is specified by the SESA1n register. If both the rising edge and the falling edge are selected as the capture triggers, it is possible to measure the input pulse width externally. If a single edge is selected as the capture trigger, the input pulse cycle can be measured. (e) Timer output operation Timer output operation is performed from the TO1n pin by setting TMENC1n to the general-purpose timer mode (T1CMDn bit = 0) using the TUM1n register. During the timer output operation, the cycle and duty (CM1n0 and CM1n1 registers) cannot be rewritten. The resolution is 16 bits, and the count clock can be selected from among seven internal clocks (fX/8, fX/16, fX/32, fX/64, fX/128, fX/256, fX/512). Figure 9-18. TMENC1n Block Diagram (During Timer Output Operation) fX/8 fX/16 fX/32 fX/64 fX/128 fX/256 fX/512 TMENC1n (16 bits) 16 Compare register (CM1n0) Clear INTCM1n0 ALVT1n0 S Q TUM1n register TO1n R Compare register (CM1n1) INTCM1n1 Remarks 1. fX: Main clock 2. n = 0, 1 466 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (i) Description of operation The CM1n0 register is a compare register used to set the timer output cycle. When the value of this register matches the value of TMENC1n, the INTCM1n0 interrupt request signal is generated. The compare match is saved by hardware, and TMENC1n is cleared at the next count clock after the match. The CM1n1 register is a compare register used to set the timer output duty. Set the duty required for the timer cycle. Figure 9-19. Timer Output Example (When ALVT1n0 Bit = 0 Is Set) TMENC1n CM1n0 set value CM1n1 set value TO1n INTCM1n0 INTCM1n1 Cautions 1. Changing the values of the CM1n0 and CM1n1 registers is prohibited during TMENC1n operation (CE1n1 bit of TMC1n register = 1). 2. Changing the value of the ALVT1n0 bit of the TUM1n register is prohibited during TMENC1n operation. 3. Timer output is performed from the second timer cycle after the CE1n1 bit is set to 1. Remark n = 0, 1 User's Manual U16031EJ4V1UD 467 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Operation in UDC mode (a) Overview of operation in UDC mode The count clock input to TMENC1n in the UDC mode (T1CMDn bit of TUM1n register = 1) can only be externally input from the TIUD1n and TCUD1n pins. Up-/down-count judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting (there is a total of four choices). Table 9-8. List of Count Operations in UDC Mode PRM1n Register PRM1n2 1 PRM1n1 0 PRM1n0 0 Operation Mode Mode 1 Down count upon detection of valid edge of TIUD1n input when TCUD1n = high level Up count upon detection of valid edge of TIUD1n input when TCUD1n = low level 1 0 1 Mode 2 Up count upon detection of valid edge of TIUD1n input Down count upon detection of valid edge of TCUD1n input Up count upon detection of valid edge of TIUD1n input when TCUD1n = high level Down count upon detection of valid edge of TIUD1n input when TCUD1n = low level 1 1 1 Mode 4 Automatic judgment upon detection of both edges of TIUD1n input and both edges of TCUD1n input TMENC1n Operation 1 1 0 Mode 3 Remark n = 0, 1 The UDC mode is further divided into two modes according to the TMENC1n clear conditions (a count operation is performed only with TIUD1n and TCUD1n input in both modes). * UDC mode A (TUM1n.T1CMDn bit = 1, TUM1n.MSELn bit = 0) The TMENC1n clear source can be selected as only external clear input (TCLR1n), a match signal between the TMENC1n count value and the CM1n0 register set value during up-count operation, or the logical sum (OR) of the two signals, using bits CLR1n1 and CLR1n0 of the TMC1n register. TMENC1n can transfer the value of the CM1n0 register upon occurrence of a TMENC1n underflow. * UDC mode B (TUM1n.T1CMDn bit = 1, TUM1n.MSELn bit = 1) The status of TMENC1n after a match of the TMENC1n count value and the CM1n0 register set value is as follows. <1> In the case of an up-count operation, TMENC1n is cleared to 0000H, and the INTCM1n0 interrupt request signal is generated. <2> In the case of a down-count operation, the TMENC1n count value is decremented by 1. The status of TMENC1n after a match of the TMENC1n count value and the CM1n1 register set value is as follows. <1> In the case of an up-count operation, the TMENC1n count value is incremented by 1. <2> In the case of a down-count operation, TMENC1n is cleared to 0000H, and the INTCM1n1 interrupt request signal is generated. 468 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (b) Up-/down-count operation in UDC mode TMENC1n up-/down-count judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting. (i) Mode 1 (PRM1n.PRM1n2 bit = 1, PRM1n.PRM1n1 bit = 0, PRM1n.PRM1n0 bit = 0) In mode 1, the following count operations are performed based on the level of the TCUD1n pin upon detection of the valid edge of the TIUD1n pin. * TMENC1n down-count operation when TCUD1n pin = high level * TMENC1n up-count operation when TCUD1n pin = low level Figure 9-20. Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin) TIUD1n TCUD1n TMENC1n 0007H 0006H 0005H 0004H 0005H 0006H Up count 0007H Down count Remark n = 0, 1 Figure 9-21. Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin): In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing TIUD1n TCUD1n TMENC1n 0007H 0006H 0005H 0004H 0005H 0006H Up count 0007H Down count Remark n = 0, 1 User's Manual U16031EJ4V1UD 469 CHAPTER 9 TIMER/COUNTER FUNCTION (ii) Mode 2 (PRM1n.PRM1n2 bit = 1, PRM1n.PRM1n1 bit = 0, PRM1n.PRM1n0 bit = 1) The count conditions in mode 2 are as follows. * TMENC1n up count upon detection of valid edge of TIUD1n pin * TMENC1n down count upon detection of valid edge of TCUD1n pin Caution If the count clock is simultaneously input to the TIUD1n pin and the TCUD1n pin, count operation is not performed and the immediately preceding value is held. Figure 9-22. Mode 2 (When Rising Edge Is Specified as Valid Edge of TIUD1n, TCUD1n Pins) TIUD1n TCUD1n TMENC1n 0006H 0007H Up count 0008H Hold value 0007H 0006H 0005H Down count Remark n = 0, 1 (iii) Mode 3 (PRM1n.PRM1n2 = 1, PRM1n.PRM1n1 = 1, PRM1n.PRM1n0 = 0) In mode 3, when two signals 90 degrees out of phase are input to the TIUD1n and TCUD1n pins, the level of the TCUD1n pin is sampled at the input of the valid edge of the TIUD1n pin (see Figure 923). If the TCUD1n pin level sampled at the valid edge input to the TIUD1n pin is low, TMENC1n counts down when the valid edge is input to the TIUD1n pin. If the TCUD1n pin level sampled at the valid edge input to the TIUD1n pin is high, TMENC1n counts up when the valid edge is input to the TIUD1n pin. Figure 9-23. Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1n pin) TIUD1n TCUD1n TMENC1n 0007H 0008H 0009H 000AH 0009H 0008H 0007H Up count Down count Remark n = 0, 1 470 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-24. Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin): In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing TIUD1n TCUD1n TMENC1n 0007H 0008H 0009H 000AH 0009H 0008H 0007H Up count Down count Remark n = 0, 1 (iv) Mode 4 (PRM1n.PRM1n2 = 1, PRM1n.PRM1n1 = 1, PRM1n.PRM1n0 = 1) In mode 4, when two signals out of phase are input to the TIUD1n and TCUD1n pins, up/down operation is automatically judged and counting is performed according to the timing shown in Figure 9-25. In mode 4, counting is executed at both the rising and falling edges of the two signals input to the TIUD1n and TCUD1n pins. Therefore, TMENC1n counts four times per cycle of an input signal (x4 count). Figure 9-25. Mode 4 TIUD1n TCUD1n TMENC1n 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 0009H 0008H 0007H 0006H 0005H Up count Down count Cautions 1. When mode 4 is specified as the operation mode of TMENC1n, the valid edge specifications for the TIUD1n and TCUD1n pins are not valid. 2. If the TIUD1n pin edge and TCUD1n pin edge are input simultaneously in mode 4, TMENC1n continues the same count operation (up or down) it was performing immediately before the input. Remark n = 0, 1 User's Manual U16031EJ4V1UD 471 CHAPTER 9 TIMER/COUNTER FUNCTION (c) Operation in UDC mode A (i) Interval operation The operations at the count clock following a match of the TMENC1n count value and the CM1n0 register set value are as follows. * In case of up-count operation: TMENC1n is cleared to 0000H and the INTCM1n0 interrupt request signal is generated. * In case of down-count operation: The TMENC1n count value is decremented by 1 and the INTCM1n0 interrupt request signal is generated. Remark The interval operation can be combined with the transfer operation. (ii) Transfer operation If TMENC1n = 0000H during down counting when the TMC1n.RLEN1n bit = 1, the CM1n0 register set value is transferred to TMENC1n at the next count clock. Remarks 1. Transfer enable/disable can be set using the RLEN1n bit of the TMC1n register. 2. The transfer operation can be combined with the interval operation. Figure 9-26. Example of TMENC1n Operation When Interval Operation and Transfer Operation Are Combined CM1n0 register set value TMENC1n count value 0000H TMENC1n and CM1n0 match & timer clear Up count TMENC1n underflow & CM1n0 data transfer Down count Remark n = 0, 1 (iii) Compare function TMENC1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register (CC1n0, CC1n1) channels. When the TMENC1n count value and the set value of one of the compare registers match, a match interrupt request signal (INTCM1n0, INTCM1n1, INTCC1n0Note, INTCC1n1Note) is output. Note This match interrupt request signal is generated when the CC1n0 and CC1n1 registers are set to the compare register mode. (iv) Capture function TMENC1n connects two capture/compare register (CC1n0, CC1n1) channels. When the CC1n0 and CC1n1 registers are set to the capture register mode, the value of TMENC1n is captured in synchronization with the corresponding capture trigger signal. A capture interrupt request signal (INTCC1n0, INTCC1n1) is generated upon detection of the valid edge. 472 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (d) Operation in UDC mode B (i) Basic operation The operations at the next count clock after the count value of TMENC1n and the CM1n0 register set value match when TMENC1n is in UDC mode B are as follows. * In case of up-count operation: TMENC1n is cleared to 0000H and the INTCM1n0 interrupt request signal is generated. * In case of down-count operation: The TMENC1n count value is decremented by 1. The operations at the next count clock after the count value of TMENC1n and the CM1n1 register set value match when TMENC1n is in UDC mode B are as follows. * In case of up-count operation: The TMENC1n count value is incremented by 1. request signal is generated. Figure 9-27. Example of TMENC1n Operation in UDC Mode * In case of down-count operation: TMENC1n is cleared to 0000H and the INTCM1n1 interrupt CM1n0 register set value TMENC1n not cleared if count clock counts up Clear following match TMENC1n count value Clear TMENC1n not cleared if count clock counts down following match CM1n1 register set value * Remark n = 0, 1 (ii) Compare function TMENC1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register (CC1n0, CC1n1) channels. When the TMENC1n count value and the set value of one of the compare registers match, a match interrupt request signal (INTCM1n0 (only during up-count operation), INTCM1n1 (only during downcount operation), INTCC1n0Note, INTCC1n1Note) is output. Note This match interrupt request signal is generated when the CC1n0 and CC1n1 registers are set to the compare register mode. (iii) Capture function TMENC1n connects two capture/compare register (CC1n0, CC1n1) channels. When the CC1n0 and CC1n1 registers are set to the capture register mode, the value of TMENC1n is captured in synchronization with the corresponding capture trigger signal. A capture interrupt request signal (INTCC1n0, INTCC1n1) is generated upon detection of the valid edge. User's Manual U16031EJ4V1UD 473 CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.7 Supplementary description of internal operation (1) Clearing of count value in UDC mode B When TMENC1n is in UDC mode B, the conditions to clear the count value are as follows. * In case of TMENC1n up count operation: TMENC1n count value is cleared upon match with the CM1n0 register * In case of TMENC1n down count operation: TMENC1n count value is cleared upon match with the CM1n1 register Figure 9-28. Clear Operation After Match of CM1n0 Register Set Value and TMENC1n Count Value (a) Up count Up count TMENC1n cleared Count clock (Rising edge set as valid edge) TMENC1n FFFEH FFFFH 0000H 0001H CM1n0 register Up count FFFFH Up count (b) Up count Down count TMENC1n not cleared Count clock (Rising edge set as valid edge) TMENC1n FFFEH FFFFH FFFEH FFFDH CM1n0 register Up count FFFFH Down count Remark n = 0, 1 474 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-29. Clear Operation After Match of CM1n1 Register Set Value and TMENC1n Count Value (a) Down count Down count TMENC1n cleared Count clock (Rising edge set as valid edge) TMENC1n 00FFH 00FEH 0000H FFFFH CM1n1 register Down count 00FEH Down count (b) Down Up count TMENC1n not cleared Count clock (Rising edge set as valid edge) TMENC1n 00FFH 00FEH 00FFH 0100H CM1n1 register Down count 00FEH Up count Remark n = 0, 1 (2) Transfer operation If TMENC1n = 0000H during down counting when the RLEN1n bit of the TMC1n register = 1 in UDC mode A, the CM1n0 register set value is transferred to TMENC1n at the next count clock. The transfer operation is not performed during up counting. Figure 9-30. Internal Operation During Transfer Operation Transfer operation performed. Count clock (Rising edge set as valid edge) TMENC1n 0001H 0000H CM1n0 CM1n0 set value set value - 1 FFFFH Down count Down count CM1n0 register Remark n = 0, 1 User's Manual U16031EJ4V1UD 475 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Interrupt request signal output upon compare match An interrupt request signal is output when the count value of TMENC1n matches the set value of the CM1n0, CM1n1, CC1n0Note, or CC1n1Note register. The interrupt generation timing is as follows. Note When the CC1n0 and CC1n1 registers are set to the compare register mode. Figure 9-31. Interrupt Request Signal Output upon Compare Match (CM1n1 with Operation Mode Set to General-Purpose Timer Mode and Count Clock Set to fX/8) fX/4 Count clock TMENC1n 0007H 0008H 0009H 000AH 000BH CM1n1 register Internal match signal 0009H INTCM1n1 Remarks 1. fX: Main clock 2. n = 0, 1 An interrupt request signal such as the one illustrated in Figure 9-31 is output at the next count clock following a match of the TMENC1n count value and the set value of the corresponding compare register. (4) UBD1n flag (bit 0 of STATUS1n register) operation In the UDC mode (T1CMDn bit of TUM1n register = 1), the UBD1n flag changes as follows during TMENC1n up-/down-count operation at every internal operation clock. Figure 9-32. UBD1n Flag Operation Count clock TMENC1n 0000H 0001H 0000H 0001H 0000H 0001H UBD1n flag Remark n = 0, 1 476 User's Manual U16031EJ4V1UD CHAPTER 9 TIMER/COUNTER FUNCTION (5) Overflow interrupt request signal (INTOV1n) and underflow interrupt request signal (INTUD1n) (a) The overflow interrupt request signal (INTOV1n) is generated when the count value of TMENC1n has reached FFFFH and the next count operation is an up-count. (b) The underflow interrupt request signal (INTUD1n) is generated when the count value of TMENC1n has reached 0000H and the next count operation is a down-count. (c) TMENC1n continues counting even after occurrence of an overflow or underflow, if a count edge is detected. If the condition of the underflow (0000H FFFFH) is satisfied when the RLEN1n bit of the TMC1n register is 1 (enabling transfer), however, the CM1n0 register set value is transferred. (d) If the condition of the underflow (0000H FFFFH) is satisfied with the CM1n0 register set value = FFFFH when the RLEN1n bit of the TMC1n register is cleared to 0 (disabling transfer), the INTCM1n0 interrupt and INTUD1n interrupt occur simultaneously. 9.3.8 Cautions Cautions concerning the timer ENC1 are shown below. (1) INTP1n0 pin in UDC mode The TCUD1n and INTP1n0 pins function alternately. Therefore, because the TCUD1n pin is used in the UDC mode, the external capture function of the INTP1n0 pin cannot be used. (2) INTP1n1 pin in UDC mode A The TCLR1n and INTP1n1 pins function alternately. Therefore, when the TCLR1n input is used in UDC mode A, the external capture function of the INTP1n1 pin cannot be used. (3) Setting trigger mode Set the PMCDH register before setting the trigger mode of the INTP1n0, INTP1n1, TIUD1n, TCUD1n, and TCLR1n pins. If the PMCDH register is set after the SESA1n register has been set, an illegal interrupt, incorrect counting, and incorrect clearing may occur depending on the timing of setting the PMCDH register. (4) Caution on setting NCW1n register Whether the signal is input through or inverted can be specified for each of the INTP1n0/TCUD1n and TIUD1n pins by the SRTCn and SRTIn bits of the NCW1n register. The setting of the noise elimination width by the NCFn, NCC1n, and NCC0n bits is for each timer and cannot be changed for each pin. User's Manual U16031EJ4V1UD 477 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Features The serial interface function provides three types of serial interfaces equipped with five transmit/receive channels of which four channels can be used simultaneously. The following three interface formats are available. (1) Asynchronous serial interfaces B0 and B1 (UARTB0 and UARTB1): 2 channels (2) Clocked serial interfaces 30 and 31 (CSI30 and CSI31): 2 channels (3) USB function controller (USBF): 1 channel Remark For details of the USB function, see CHAPTER 11 USB FUNCTION CONTROLLER (USBF). UARTB0 and UARTB1, which use the method of transmitting/receiving one byte of serial data following a start bit, enable full-duplex communication to be performed. CSI30 and CSI31 transfer data according to three types of signals (3-wire serial I/O). These signals are the serial clock (SCK0 and SCK1), serial input (SI0 and SI1), and serial output (SO0 and SO1) signals. The USB supports full-speed transfer of 12 Mbps and consists of seven endpoints. 10.1.1 Switching between UARTB0 and CSI30 modes In the V850E/ME2, since UARTB0 and CSI30 are alternate function pins, they cannot be used at the same time. The registers must be set in advance. 478 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2 Asynchronous Serial Interfaces B0, B1 (UARTB0, UARTB1) 10.2.1 Features * Transfer rate: Maximum 1.5 Mbps (using a dedicated baud rate generator) * Full-duplex communications * Single mode and FIFO mode selectable * Single mode: 8-bit x 1-stage data register (UBnTX register or UBnRX register) is used for each of transmission and reception. * FIFO mode Transmit FIFOn: UBnTX register (8 bits x 16 stages). Receive FIFOn: UBnRXAP register (16 bits x 16 stages) 2 bits of the higher 8 bits of the UBnRXAP register are for an error flag. * Two-pin configuration TXDn: Transmit data output pin RXDn: Receive data input pin * Reception error detection function * Overflow error (FIFO mode only) * Parity error * Framing error * Overrun error (single mode only) * Interrupt sources: 5 types * Reception error interrupt (UBTIREn) * Reception completion interrupt (UBTIRn) * Transmission completion interrupt (UBTITn) * FIFO transmission completion interrupt (UBTIFn) (FIFO mode only) * Reception timeout interrupt (UBTITOn) (FIFO mode only) * The character length of transmit/receive data is specified according to the UBnCTL0 register * Character length: 7 or 8 bits * Parity functions: Odd, even, 0, or none * Transmission stop bits: 1 or 2 bits * MSB first/LSB first selectable for transfer data * On-chip dedicated baud rate generator Remark n = 0, 1 User's Manual U16031EJ4V1UD 479 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 Configuration UARTBn is controlled by UARTBn control register 0 (UBnCTL0), the UARTBn status register (UBnSTR), UARTBn control register 2 (UBnCTL2), UARTBn FIFO control register 0 (UBnFIC0), UARTBn FIFO control register 1 (UBnFIC1), UARTBn FIFO control register 2 (UBnFIC2), UARTBn FIFO status register 0 (UBnFIS0), and UARTBn FIFO status register 1 (UBnFIS1) (n = 0, 1). Receive data is stored in a receive data register (the UBnRX register in the single mode or receive FIFOn in the FIFO mode (the UBnRXAP register)) and transmit data is written to a transmit data register (the UBnTX register in the single mode or transmit FIFOn in the FIFO mode). If a reception error (such as a parity error or a framing error) occurs in the FIFO mode, the error data can be identified by reading UARTBn receive data register AP (UBnRXAP) in 16-bit (halfword) units. Figure 10-1 shows the configuration of the asynchronous serial interface. (1) UARTBn control register 0 (UBnCTL0) (n = 0, 1) This register controls the transfer operation of UARTBn. (2) UARTBn status register (UBnSTR) (n = 0, 1) This register indicates the transfer status during transmission and the contents of a reception error. The status flag of this register, which indicates the transfer status during transmission, indicates the data retention status of transmit shift register n and transmit data register n (the UBnTX register in the single mode or transmit FIFOn in the FIFO mode). Each reception error flag is set to 1 when a reception error occurs, and cleared to 0 when 0 is written to the UBnSTR register. (3) UARTBn control register 2 (UBnCTL2) (n = 0, 1) This register is used to specify the division rate by which to control the baud rate (serial transfer speed) of UARTBn. (4) UARTBn FIFO control register 0 (UBnFIC0) (n = 0, 1) This register is used to select the operation mode of UARTBn, clear the transmit FIFOn/receive FIFOn that becomes valid in the FIFO mode, and specify the timing mode in which the transmission completion interrupt (UBTITn)/reception completion interrupt (UBTIRn) occurs. (5) UARTBn FIFO control register 1 (UBnFIC1) (n = 0, 1) This register is valid in the FIFO mode. It generates a reception timeout interrupt request (UBTITOn) if data is stored in the receive FIFOn when the next data does not come (start bit is not detected) even after the reception wait time of the next data has elapsed. (6) UARTBn FIFO control register 2 (UBnFIC2) (n = 0, 1) This register is valid in the FIFO mode. It is used to set the timing to generate the transmission completion interrupt (UBTITn)/reception completion interrupt (UBTIRn), using the number of data transmitted or received as a trigger. (7) UARTBn FIFO status register 0 (UBnFIS0) (n = 0, 1) This register is valid in the FIFO mode. The number of bytes of data stored in the receive FIFO can be read from this register. (8) UARTBn FIFO status register 1 (UBnFIS1) (n = 0, 1) This register is valid in the FIFO mode. The number of vacant bytes of the transmit FIFOn can be read from this register. 480 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (9) Receive shift register n (n = 0, 1) This is a shift register that converts the serial data that was input to the RXDn pin into parallel data. One byte of data is received, and if a stop bit is detected, the received data is transferred to receive data register n. This register cannot be directly manipulated. (10) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) (n = 0, 1) Receive data register n holds receive data. In the single mode, the 8-bit x 1-stage UBnRX register is used. The 16-bit x 16-stage receive FIFOn (UBnRXAP register) is used in the FIFO mode. The receive data is stored in the lower 8 bits of the receive FIFOn (UBnRXAP register) and the error information of the received data is stored in the higher 8 bits (bit 8 and bit 9). If a reception error (such as a parity error or a framing error) occurs in the FIFO mode, the error data can be identified by reading the UBnRXAP register in 16-bit (halfword) units (error information is appended as UBnPEF bit = 1 or UBnFEF bit = 1). When the lower 8 bits of the UBnRXAP register are read in 8-bit (byte) units, the higher 8 bits are discarded. Therefore, if no error has occurred, the receive data of the UBnRXAP register can be read consecutively by being read in 8-bit (byte) units in the same way as the UBnRX register. When 7-bit length data is received with the LSB first, the received data is transferred to bits 6 to 0 of receive data register n from the LSB (bit 0), with the MSB (bit 7) always being 0. When data is received with the MSB first, the received data is transferred to bits 7 to 1 of receive data register n from the MSB (bit 7), with the LSB (bit 0) always being 0. If an overrun error occurs, the receive data at that time is not transferred to receive data register n. While reception is enabled, the received data is transferred from receive shift register n to receive data register n, in synchronization with the shift-in processing of one frame. A reception completion interrupt request (UBTIRn) is generated by transferring the data to the UBnRX register in the single mode, or transferring the number of receive data set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register to receive FIFOn in the FIFO mode. If data is stored in receive FIFOn when the next data does not come (start bit is not detected) after the next data reception wait time specified by the UBnTC4 to UBnTC0 bits of the UBnFIC1 register has elapsed in the FIFO mode, a reception timeout interrupt request (UBTITOn) is generated. (11) Transmit shift register n (n = 0, 1) This is a shift register that converts the parallel data that was transferred from transmit data register n into serial data. When one byte of data is transferred from transmit data register n, transmit shift register n data is output from the TXDn pin. This register cannot be directly manipulated. User's Manual U16031EJ4V1UD 481 CHAPTER 10 SERIAL INTERFACE FUNCTION (12) UARTBn transmit data register n (UBnTX) (n = 0, 1) Transmit data register n is a buffer for transmit data. The 8-bit x 1-stage UBnTX register is used as this buffer in the single mode. In the FIFO mode, the 8-bit x 16-stage transmit FIFOn is used. When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of transmit data register n are transmitted as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0. When data is transmitted with the MSB first, bits 7 to 1 of transmit data register n are transmitted as the transmit data from the MSB (bit 7) with the LSB (bit 0) always being 0. In the single mode, transmission is started by writing transmit data to the UBnTX register while transmission is enabled (UBnTXE bit = 1 in the UBnCTL0 register). When writing the transmit data to the UBnTX register is enabled (when 1-byte data is transferred from the UBnTX register to transmit shift register n), a transmission completion interrupt request (UBTITn) is generated. In the FIFO mode, transmission is started by writing at least the number of transmit data set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register and 16 bytes or less to transmit FIFOn and then enabling transmission (UBnTXE bit = 1). When the number of transmit data set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register have been transferred from transmit FIFOn to transmit shift register n (transmit data of the number set as the trigger can be written), a transmission completion interrupt request (UBTITn) is generated. In the FIFO mode, a FIFO transmission completion interrupt request (UBTIFn) is generated when there is no more data in transmit FIFOn and transmit shift register n (when FIFOn and the register become empty). (13) Timeout counter This counter is used to recognize that data exists (remains) in receive FIFOn when the number of received data does not reach the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register, and is valid only in the FIFO mode. If data is stored in receive FIFOn when the next data does not come (start bit is not detected) after the next data reception wait time specified by the UBnTC4 to UBnTC0 bits of the UBnFIC1 register has elapsed after the stop bit has been received, a reception timeout interrupt request (UBTITOn) is generated. (14) Sampling block This block samples the RXDn signal at the rising edge of the input clock (fX/4) (fX: main clock). If the same sampling value is detected two times, output of the match detector changes, and the value is sampled as input data. Data of less than one clock width is judged as noise and is not transmitted to the internal circuitry. 482 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-1. Block Diagram of Asynchronous Serial Interfaces B0 and B1 Internal bus Reception unit Receive FIFOn UARTBnFIFO status register 1 (UBnFIS1) UARTBnFIFO status register 0 (UBnFIS0) UARTBnFIFO control register 2 (UBnFIC2) UARTBnFIFO control register 1 (UBnFIC1) UARTBnFIFO control register 0 (UBnFIC0) UARTBn status register (UBnSTR) UARTBn control register 2 (UBnCTL2) UARTBn control register 0 (UBnCTL0) Transmission unit Transmit FIFOn UBnTX UBTIFn UBnRX Receive shift register n UBTIREn RXDn UBTIRn UBTITOn Timeout counter Sampling block Baud rate generator n Baud rate generator n Transmit shift register n TXDn Receive controller Transmit controller UBTITn fX/4 Remarks 1. n = 0, 1 2. fX: Main clock User's Manual U16031EJ4V1UD 483 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Control registers (1) UARTBn control register 0 (UBnCTL0) (n = 0, 1) The UBnCTL0 register controls the transfer operations of UARTBn. This register can be read or written in 8-bit or 1-bit units. Cautions 1. When using UARTBn, set the external pins related to the UARTBn function in the control mode, set UARTBn control register 2 (UBnCTL2). Then set the UBnPWR bit to 1 before setting the other bits. 2. Be sure to input a high level to the RXDn pin when setting the external pins related to the UARTBn function in the control mode. If a low level is input, it is judged that a falling edge is input after the UBnRXE bit has been set to 1, and reception may be started. (1/3) 7 6 5 4 3 2 1 UB0CL 0 UB0SL Address FFFFFA00H After reset 10H UB0CTL0 UB0PWR UB0TXE UB0RXE UB0DIR UB0PS1 UB0PS0 UB1CTL0 UB1PWR UB1TXE UB1RXE UB1DIR UB1PS1 UB1PS0 UB1CL UB1SL FFFFFA20H 10H Bit position 7 Bit name UBnPWR Controls the operation clock. 0: Stops supply of clocks to UARTBn 1: Supplies clocks to UARTBn Function Cautions 1. When the UBnPWR bit is cleared to 0, the UARTBn can be asynchronously reset. 2. When UBnPWR = 0, the UARTBn is in a reset state. Therefore, to operate UARTBn, the UBnPWR bit must be set to 1. 3. When the UBnPWR bit is changed from 1 to 0, all registers of the UARTBn are initialized. When the UBnPWR is set to 1 again, the UARTBn registers must be set again. The TXDn pin output is high level when the UBnPWR bit is cleared to 0. 6 UBnTXE Specifies whether transmission is enabled or disabled. 0: Transmission is disabled 1: Transmission is enabled Cautions 1. On startup, set UBnPWR to 1 and then set UBnTXE to 1. To stop transmission, clear UBnTXE to 0 and then UBnPWR to 0. 2. When the transmission unit status is to be initialized, the transmission status may not be able to be initialized unless the UBnTXE bit is set to 1 again after an interval of two cycles of fX/4 (fX: main clock) has elapsed since the UBnTXE bit was cleared to 0. Remark n = 0, 1 484 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Bit position 5 Bit name UBnRXE Function Specifies whether reception is enabled or disabled. 0: Reception is disabled 1: Reception is enabled Cautions 1. On startup, set UBnPWR to 1 and then set UBnRXE to 1. To stop reception, clear UBnRXE to 0 and then UBnPWR to 0. 2. When the reception unit status is to be initialized, the reception status may not be able to be initialized unless the UBnRXE bit is set to 1 again after an interval of two cycles of fX/4 (fX: main clock) has elapsed since the UBnRXE bit was cleared to 0. 4 UBnDIR Specifies the transfer direction mode (MSB/LSB). 0: The first bit of transfer data is the MSB. 1: The first bit of transfer data is the LSB. Caution Clear the UBnPWR bit or UBnTXE and UBnRXE bits to 0 before changing the setting of the UBnDIR bit. 3, 2 UBnPS1, UBnPS0 Controls the parity bit. UBnPS1 0 0 1 1 UBnPS0 0 1 0 1 Transmit operation Do not output a parity bit Output 0 parity Output odd parity Output even parity Receive operation Receive with no parity Receive as 0 parity Judge as odd parity Judge as even parity Cautions 1. Clear the UBnTXE and UBnRXE bits to 0 before overwriting the UBnPS1 and UBnPS0 bits. 2. If "0 parity" is selected for reception, no parity judgment is made. Therefore, no error interrupt is generated because the UBnPE bit of the UBnSTR register is not set to 1. * Even parity If the transmit data contains an odd number of bits with the value "1", the parity bit is set to 1. If it contains an even number of bits with the value "1", the parity bit is cleared to 0. This controls the number of bits with the value "1" contained in the transmit data and the parity bit so that it is an even number. During reception, the number of bits with the value "1" contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. * Odd parity In contrast to even parity, odd parity controls the number of bits with the value "1" contained in the transmit data and the parity bit so that it is an odd number. During reception, the number of bits with the value "1" contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. Remark n = 0, 1 User's Manual U16031EJ4V1UD 485 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) Bit position 3, 2 Bit name UBnPS1, UBnPS0 * 0 parity During transmission, the parity bit is cleared to 0 regardless of the transmit data. During reception, no parity error is generated because no parity bit is checked. * No parity No parity bit is added to transmit data. During reception, the receive data is considered to have no parity bit. No parity error is generated because there is no parity bit. 1 UBnCL Specifies the character length of the transmit/receive data. 0: 7 bits 1: 8 bits Caution Clear the UBnTXE and UBnRXE bits to 0 before overwriting the UBnCL bit. 0 UBnSL Specifies the stop bit length of the transmit data. 0: 1 bit 1: 2 bits Cautions 1. Clear the UBnTXE bit to 0 before overwriting the UBnSL bit. 2. Since reception always operates by using a single stop bit length, the UBnSL bit setting does not affect receive operations. Function Remarks 1. When reception is disabled, receive shift register n does not detect a start bit. No shift-in processing or transfer processing to receive data register n is performed, and the contents of receive data register n are retained. When reception is enabled, the receive shift operation starts, in synchronization with the detection of the start bit, and when the reception of one frame is completed, the contents of receive shift register n are transferred to receive data register n. A reception completion interrupt (UBTIRn) is also generated, in synchronization with the transfer to receive data register n (in FIFO mode, transfer triggered by reaching set number of receive data). If data is stored in receive FIFOn when the next data does not come (start bit is not detected) after the next data reception wait time specified by the UBnTC4 to UBnTC0 bits of the UBnFIC1 register has elapsed in the FIFO mode, a reception timeout interrupt request (UBTITOn) is generated. 2. n = 0, 1 486 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) UARTBn status register (UBnSTR) (n = 0, 1) The UBnSTR register indicates the transfer status and reception error contents while UARTBn is transmitting data. The status flag that indicates the transfer status during transmission indicates the data retention status of transmit shift register n and transmit data register n (the UBnTX register in the single mode or transmit FIFOn in the FIFO mode). The status flag that indicates a reception error holds its status until it is cleared to 0. This register can be read or written in 8-bit or 1-bit units. Caution When the UBnPWR bit or UBnRXE bit of the UBnCTL0 register is cleared to 0, or when 0 is written to the UBnSTR register, the UBnOVF, UBnPE, UBnFE, and UBnOVE bits of the UBnSTR register are cleared to 0. (1/2) 7 UB0STR UB0TSF 6 0 5 0 4 0 3 UB0OVF 2 UB0PE 1 UB0FE 0 UB0OVE Address FFFFFA04H After reset 00H UB1STR UB1TSF 0 0 0 UB1OVF UB1PE UB1FE UB1OVE FFFFFA24H 00H Bit position 7 Bit name UBnTSF Function This is a status flag indicating the transfer status. * In single mode (UBnMOD bit = 0 in the UBnFIC0 register) 0: Data to be transferred to transmit shift register n and UBnTX register does not exist (cleared (0) when UBnPWR bit = 0 or UBnTXE bit = 0 in the UBnCTL0 register). 1: Data to be transferred to transmit shift register n or UBnTX register exists (transmission in progress). * In FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register) 0: Data to be transferred to transmit shift register n and transmit FIFOn does not exist (cleared (0) when UBnPWR bit = 0 or UBnTXE bit = 0 in the UBnCTL0 register). 1: Data to be transferred to transmit shift register n and transmit FIFOn exists (transmission in progress). Caution The value of the UBnTSF bit is reflected after two periods of fX/4 (fX: main clock) have elapsed, after the transmit data is written to the UBnTX register. Therefore, exercise care when referencing the UBnTSF bit after transmit data has been written to the UBnTX register. 3 UBnOVF This is a status flag indicating an overflow. The setting of this flag is valid only in the FIFO mode (when UBnMOD bit = 1 in the UBnFIC0 register), and invalid in the single mode (when UBnMOD bit = 0 in the UBnFIC0 register). 0: Overflow did not occur. 1: Overflow occurred (during reception). Caution If an overflow occurs, the received data is not written to receive FIFOn but discarded. Remark n = 0, 1 User's Manual U16031EJ4V1UD 487 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/2) Bit position 2 Bit name UBnPE Function This is a status flag that indicates a parity error. The setting of this flag is valid only in the single mode (when UBnMOD bit = 0 in the UBnFIC0 register), and invalid in the FIFO mode (when UBnMOD bit = 1 in the UBnFIC0 register). 0: Parity error did not occur. 1: Parity error occurred (during reception). Caution The operation of the UBnPE bit differs according to the settings of the UBnPS1 and UBnPS0 bits of the UBnCTL0 register. 1 UBnFE This is a status flag that indicates a framing error. The setting of this flag is valid only in the single mode (when UBnMOD bit = 0 in the UBnFIC0 register), and invalid in the FIFO mode (when UBnMOD bit = 1 in the UBnFIC0 register). 0: Framing error did not occur. 1: Framing error occurred (during reception). Caution Only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. 0 UBnOVE This is a status flag that indicates an overrun error. The setting of this flag is valid only in the single mode (when UBnMOD bit = 0 in the UBnFIC0 register), and invalid in the FIFO mode (when UBnMOD bit = 1 in the UBnFIC0 register). 0: Overrun error did not occur. 1: Overrun error occurred (during reception). Caution When an overrun error occurs, the next receive data value is not written to the UBnRX register and the data is discarded. Remark n = 0, 1 488 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) UARTBn control register 2 (UBnCTL2) (n = 0, 1) The UBnCTL2 register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of UARTBn. This register can be read or written in 16-bit units. Caution When rewriting the UBnBRS15 to UBnBRS0 bits of this register, clear the UBnTXE and UBnRXE bits of the UBnCTL0 register to 0 or clear the UBnPWR bit (n = 0, 1). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFA02H After reset FFFFH UB0CTL2 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 UB0 BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UB1CTL2 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 UB1 BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS BRS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FFFFFA22H FFFFH Bit position 15 to 0 Bit name UBnBRS15 to UBnBRS0 Function Specify the division value of the 16-bit counter (see Table 10-1). Remark n = 0, 1 Table 10-1. Division Value of 16-Bit Counter UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB UBnB RS15 RS14 RS13 RS12 RS11 RS10 RS9 0 0 0 0 * * * 1 1 1 1 0 0 0 0 * * * 1 1 1 1 0 0 0 0 * * * 1 1 1 1 0 0 0 0 * * * 1 1 1 1 0 0 0 0 * * * 1 1 1 1 0 0 0 0 * * * 1 1 1 1 0 0 0 0 * * * 1 1 1 1 RS8 0 0 0 0 * * * 1 1 1 1 RS7 0 0 0 0 * * * 1 1 1 1 RS6 0 0 0 0 * * * 1 1 1 1 RS5 0 0 0 0 * * * 1 1 1 1 RS4 0 0 0 0 * * * 1 1 1 1 RS3 0 0 0 0 * * * 1 1 1 1 RS2 0 1 1 1 * * * 1 1 1 1 RS1 x 0 0 1 * * * 0 0 1 1 RS0 x 0 1 0 * * * 0 1 0 1 4 4 5 6 * * * 65,532 65,533 65,534 65,535 k Output Clock Selected fX/(4 x k) fX/(4 x k) fX/(4 x k) fX/(4 x k) * * * fX/(4 x k) fX/(4 x k) fX/(4 x k) fX/(4 x k) Remarks 1. fX: Main clock 2. k: Value set by UBnBRS15 to UBnBRS0 bits of UBnCTL2 register (k = 4, 5, 6, ..., 65,535) 3. x: Don't care User's Manual U16031EJ4V1UD 489 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) UARTBn transmit data register (UBnTX) (n = 0, 1) The UBnTX register is used to set transmit data. It functions as the 8-bit x 1-stage UBnTX register, in the single mode (UBnMOD bit = 0 in the UBnFIC0 register), and as the 8-bit x 16-stage transmit FIFOn in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register). In the single mode, transmission is started by writing transmit data to the UBnTX register when transmission is enabled (the UBnTXE bit = 1 in the UBnCTL0 register). When data can be written to the UBnTX register (when 1 byte of data is transferred from the UBnTX register to transmit shift register n), a transmission completion interrupt request (UBTITn) is generated. In the FIFO mode, transmission is started by enabling transmission (UBnTXE bit = 1) after writing at least the number of transmit data set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register and 16 bytes or less to transmit FIFOn. When the number of transmit data set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register have been transferred from transmit FIFOn to transmit shift register n (transmit data of the number set as the trigger can be written to transmit FIFOn), a transmission completion interrupt request (UBTITn) is generated. In the FIFO mode, a FIFO transmission completion interrupt request (UBTIFn) is generated when there is no more data in transmit FIFOn and transmit shift register n (when the FIFOn and register become empty). For the generation timing of the interrupt, see 10.2.4 Interrupt requests. When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of transmit data register n are transmitted as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0. When data is transmitted with the MSB first, bits 7 to 1 of transmit data register n are transmitted as the transmit data from the MSB (bit 7) with the LSB (bit 0) always being 0. This register is write-only, in 8-bit units. Data is written to transmit data register n. 7 UB0TX 6 5 4 3 2 1 0 Address FFFFFA08H After reset FFH UB0TD7 UB0TD6 UB0TD5 UB0TD4 UB0TD3 UB0TD2 UB0TD1 UB0TD0 UB1TX UB1TD7 UB1TD6 UB1TD5 UB1TD4 UB1TD3 UB1TD2 UB1TD1 UB1TD0 FFFFFA28H FFH Bit position 7 to 0 Bit name UBnTD7 to UBnTD0 Write transmit data. Function Remark n = 0, 1 490 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) (n = 0, 1) These registers store parallel data converted by receive shift register n. They function as the 8-bit x 1-stage UBnRX register, in the single mode (UBnMOD bit = 0 in the UBnFIC0 register), and as the 16-bit x 16-stage receive FIFOn (UBnRXAP register) in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register). The receive data is stored in the lower 8 bits of the receive FIFOn (UBnRXAP register) and the error information of the received data is stored in the higher 8 bits (bit 8 and bit 9). If a reception error (such as a parity error or a framing error) occurs in the FIFO mode, the UBnRXAP register is read in 16-bit (halfword) units. In this way, the flag of the data stored in receive FIFOn can be checked (error information is appended as UBnPEF bit = 1 or UBnFEF bit = 1), so that the error data can be recognized (when the lower 8 bits of the UBnRXAP register are read in 8-bit (byte) units, the higher 8 bits are discarded. Therefore, if no error has occurred, the receive data of the UBnRXAP register can be read consecutively by being read in 8-bit (byte) units in the same way as the UBnRX register). If reception is enabled (UBnRXE bit = 1 in the UBnCTL0 register), the receive data is transferred from receive shift register n to receive data register n, in synchronization with the completion of the shift-in processing of one frame. By transferring the receive data to the UBnRX register in the single mode or by transferring the number of receive data set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register to the receive FIFOn in the FIFO mode, a reception completion interrupt request (UBTIRn) is generated. If data is stored in receive FIFOn when the next data does not come (start bit is not detected) even after the next data reception wait time specified by the UBnTC4 to UBnTC0 bits of the UBnFIC1 register has elapsed in the FIFO mode, a reception timeout interrupt request (UBTITOn) is generated. For information about the timing for generating these interrupt requests, see 10.2.4 Interrupt requests. If data is received with the LSB first when the data length is specified as 7 bits, the received data is transferred to bits 6 to 0 of receive data register n from the LSB (bit 0), with the MSB (bit 7) always being 0. If data is received with the MSB first, it is transferred to bits 7 to 1 of receive data register n from the MSB (bit 7) with the LSB (bit 0) always being 0. However, if an overrun error occurs, the receive data at that time is not transferred to receive data register n. The UBnRXAP register is read-only, in 16-bit units. However, the lower 8 bits of the UBnRXAP register are read-only, in 8-bit units. The UBnRX register is read-only, in 8-bit units. In addition to reset input, the value of these registers can be set to FFH in the single mode or to 00FFH in the FIFO mode, by clearing the UBnPWR bit of the UBnCTL0 register to 0. Cautions 1. The UBnPEF and UBnFEF bits cannot be read because these registers serve as 8-bit registers in the single mode. 2. When no reception error has occurred in the FIFO mode, the receive data of the UBnRXAP register can be read consecutively by reading the lower 8 bits of the UBnRXAP register in 8-bit (byte) units. An 8-bit access to the higher 8 bits is prohibited. If they are accessed, the operation is not guaranteed. User's Manual U16031EJ4V1UD 491 CHAPTER 10 SERIAL INTERFACE FUNCTION Cautions 3. Do not perform the following operations when debugging a system that uses the single mode. * Setting a break for an instruction immediately after the UBnRX register is read * Setting a break before DMA transfer with the UBnRX register specified as the transfer source is completed * Setting a break before completion of reception of the next data after reception of data and reading the UBnRX register, and checking the UBnRX register in the I/O register window of the debugger If any of these operations is performed, an overrun error may occur during the subsequent reception. [UARTBn receive data register AP] 15 UB0RXAP 0 14 0 13 0 12 0 11 0 10 0 9 UB0 PEF 8 UB0 FEF 7 UB0 6 UB0 5 4 3 UB0 RD3 2 1 0 UB0 RD0 Address FFFFFA06H After reset 00FFH UB0 UB0 UB0 UB0 RD2 RD1 RD7 RD6 RD5 RD4 UB1RXAP 0 0 0 0 0 0 UB1 PEF UB1 FEF UB1 UB1 UB1 UB1 UB1 RD3 UB1 UB1 RD2 RD1 UB1 RD0 FFFFFA26H 00FFH RD7 RD6 RD5 RD4 [UARTBn receive data register] 7 UB0RX UB0 6 UB0 5 4 3 UB0 RD3 2 1 0 UB0 RD0 Address FFFFFA06H After reset FFH UB0 UB0 UB0 UB0 RD2 RD1 RD7 RD6 RD5 RD4 UB1RX UB1 UB1 UB1 UB1 UB1 RD3 UB1 UB1 RD2 RD1 UB1 RD0 FFFFFA26H FFH RD7 RD6 RD5 RD4 Bit position 9 (UBnRXAP) Bit name UBnPEF Function This is a status flag that indicates a parity error. Status is valid only in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register), and is invalid in the single mode (UBnMOD bit = 0 in the UBnFIC0 register). 0: No parity error 1: Parity error occurs (during reception). Caution The operation of the UBnPEF bit differs depending on the set values of the UBnPS1 and UBnPS0 bits of the UBnCTL0 register. 8 (UBnRXAP) UBnFEF This is a status flag indicating a framing error. Status is valid only in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register), and is invalid in the single mode (UBnMOD bit = 0 in the UBnFIC0 register). 0: No framing error 1: Framing error occurs (during reception). Caution Only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. 7 to 0 UBnRD7 to UBnRD0 Stores receive data. Remark n = 0, 1 492 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (6) UARTBn FIFO control register 0 (UBnFIC0) (n = 0, 1) The UBnFIC0 register is used to select the operation mode of UARTBn and the functions that become valid in the FIFO mode (UBnMOD bit = 1). In the FIFO mode, it clears transmit FIFOn/receive FIFOn and specifies the timing mode in which the transmission completion interrupt (UBTITn)/reception completion interrupt (UBTIRn) is generated. This register can be read or written in 8-bit or 1-bit units. (1/2) 7 UB0FIC0 UB0MOD 6 0 5 0 4 0 3 2 1 0 UB0IRM Address FFFFFA0AH After reset 00H UB0TFC UB0RFC UB0ITM UB1FIC0 UB1MOD 0 0 0 UB1TFC UB1RFC UB1ITM UB1IRM FFFFFA2AH 00H Bit position 7 Bit name UBnMOD Function Specifies an operation mode of UARTBn. 0: Single mode 1: FIFO mode 3 UBnTFC This is a transmit FIFOn clear trigger bit. The setting of this bit is valid only in the FIFO mode (UBnMOD bit = 1) and invalid in the single mode (UBnMOD bit = 0). 0: Normal status 1: Clear (This bit automatically returns to 0 after transmit FIFOn is cleared.) When 1 is written to the UBnTFC bit, the pointer to transmit FIFOn is cleared to 0. In the pending mode (UBnITM bit = 0), the interrupt request (UBTITn) held pending is cleared Note . However, bit 7 (UTIFn) of the interrupt control register (UTICn) is not cleared to 0. Clear this bit to 0 as necessary. When 0 is written to the UBnTFC bit, the status is retained. No operation, such as clearing or setting, is executed. Note After transmit FIFOn is cleared (UBnTFC bit = 1), accessing the registers related to UARTB is prohibited for the duration of four cycles of fX/4 (fX: main clock) or until clearing the UBnTFC bit (automatic recovery) is confirmed by reading the UBnFIC0 register. If these registers are accessed, the operation is not guaranteed. Caution When writing 1 to the UBnTFC bit, be sure to clear the UBnTXE bit of the UBnCTL0 register to 0 (disabling transmission). If 1 is written to the UBnTFC bit when the UBnTXE bit is 1 (transmission enabled), the operation is not guaranteed. Remark n = 0, 1 User's Manual U16031EJ4V1UD 493 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/2) Bit position 2 Bit name UBnRFC Function This is a receive FIFOn (UBnRXAP) clear trigger bit. The setting of this bit is valid only in the FIFO mode (UBnMOD bit = 1) and invalid in the single mode (UBnMOD bit = 0). 0: Normal status 1: Clear (This bit automatically returns to 0 after receive FIFOn is cleared.) When 1 is written to the UBnRFC bit, the pointer to receive FIFOn is cleared to 0. In the pending mode (UBnIRM bit = 0), the interrupt request (UBTIRn) held pending is cleared Note . However, bit 7 (URIFn) of the interrupt control register (URICn) is not cleared to 0. Clear this bit to 0 as necessary. When 0 is written to the UBnRFC bit, the status is retained. No operation, such as clearing or setting, is executed. Note After receive FIFOn (UBnRXAP) is cleared (UBnRFC bit = 1), accessing the registers related to UARTB is prohibited for the duration of four cycles of fX/4 (fX: main clock) or until clearing the UBnRFC bit (automatic recovery) is confirmed by reading the UBnFIC0 register. If these registers are accessed, the operation is not guaranteed. Caution When writing 1 to the UBnRFC bit, be sure to clear the UBnRXE bit of the UBnCTL0 register to 0 (disabling reception). If 1 is written to the UBnRFC bit when the UBnRXE bit is 1 (reception enabled), the operation is not guaranteed. 1 UBnITM This bit specifies the timing mode in which the UBTITn interrupt is generated in FIFO mode. 0: Pending mode 1: Pointer mode In the FIFO mode, the UBTITn interrupt is generated as soon as transmit data of the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register have been transferred from transmit FIFOn to transmit shift register n. After the UBTITn interrupt request has been generated, specify the timing of actually generating the UBTITn interrupt as the pending mode or pointer mode. For details, see 10.2.5 (2) Pending mode/pointer mode. 0 UBnIRM This bit specifies the timing mode in which the UBTIRn interrupt is generated in FIFO mode. 0: Pending mode 1: Pointer mode In the FIFO mode, the UBTIRn interrupt is generated as soon as receive data of the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register have been transferred from receive shift register n to receive FIFOn. After the UBTIRn interrupt request has been generated, specify the timing of actually generating the UBTIRn interrupt as the pending mode or pointer mode. For details, see 10.2.5 (2) Pending mode/pointer mode. Remark n = 0, 1 494 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (7) UARTBn FIFO control register 1 (UBnFIC1) (n = 0, 1) The UBnFIC1 register is valid in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register). It generates a reception timeout interrupt request (UBTITOn) if data is stored in receive FIFOn when the next data does not come (start bit is not detected) after the lapse of the time set by the UBnTC4 to UBnTC0 bits (next data reception wait time), after the stop bit has been received. This register can be read or written in 8-bit or 1-bit units. 7 UB0FIC1 UB0TCE 6 0 5 0 4 3 2 1 0 Address FFFFFA0BH After reset 00H UB0TC4 UB0TC3 UB0TC2 UB0TC1 UB0TC0 UB1FIC1 UB1TCE 0 0 UB1TC4 UB1TC3 UB1TC2 UB1TC1 UB1TC0 FFFFFA2BH 00H Bit position 7 Bit name UBnTCE Specifies the timeout counter function. Function 0: Disable use of timeout counter function. 1: Enable use of timeout counter function. 4 to 0 UBnTC4 to UBnTC0 Specify the time to wait for the next data reception. UBn TC4 0 0 0 0 * * * 1 1 1 1 UBn TC3 0 0 0 0 * * * 1 1 1 1 UBn TC2 0 0 0 0 * * * 1 1 1 1 UBn TC1 0 0 1 1 * * * 0 0 1 1 UBn TC0 0 1 0 1 * * * 0 1 0 1 Next data reception wait time 32 bytes (32 x 8 / baud rate) 31 bytes (31 x 8 / baud rate) 30 bytes (30 x 8 / baud rate) 29 bytes (29 x 8 / baud rate) * * * 4 bytes (4 x 8 / baud rate) 3 bytes (3 x 8 / baud rate) 2 bytes (2 x 8 / baud rate) 1 byte (1 x 8 / baud rate) Caution When the count set by the UBnTC4 to UBnTC0 bits is up, the count value of the timeout counter is cleared to 0, regardless of the status of the data stored in receive FIFOn. When the next start bit is later detected, counting is started again from the stop bit of that data. Remark n = 0, 1 User's Manual U16031EJ4V1UD 495 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) UARTBn FIFO control register 2 (UBnFIC2) (n = 0, 1) The UBnFIC2 register is valid in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register). It sets the timing of generating an interrupt, using the number of transmit/receive data as a trigger. When data is transmitted, the number of data transferred from transmit FIFOn is specified as the condition of generating the interrupt. When data is received, the number of data stored in receive FIFOn is specified as the interrupt generation condition. This register can be read or written in 16-bit units. When the higher 8 bits of the UBnFIC2 register can be used as the UBnFIC2H register and the lower 8 bits, as the UBnFIC2L register, these registers can be read or written in 8-bit units. Caution Be sure to clear the UBnTXE bit (to disable transmission) and UBnRXE bit (to disable reception) of the UBnCTL0 register to 0 before writing data to the UBnFIC2 register. If data is written to the UBnFIC2 register with the UBnTXE or UBnRXE bit set to 1, the operation is not guaranteed. 496 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (1/2) 15 UB0FIC2 0 14 0 13 0 12 0 11 10 9 8 7 0 6 0 5 0 4 0 3 2 1 0 Address FFFFFA0CH After reset 0000H UB0 UB0 UB0 UB0 TT3 TT2 TT1 TT0 UB0 UB0 UB0 UB0 RT3 RT2 RT1 RT0 UB1FIC2 0 0 0 0 UB1 UB1 UB1 UB1 TT3 TT2 TT1 TT0 0 0 0 0 UB1 UB1 UB1 UB1 RT3 RT2 RT1 RT0 FFFFFA2CH 0000H Bit position 11 to 8 Bit name UBnTT3 to UBnTT0 Function Set the number of transmit FIFOn transmit data to be the trigger. Each time data of the specified number has shifted out from transmit FIFOn to transmit shift register n, the UBTITn interrupt is generated. In the pending mode (UBnITM bit = 0 in the UBnFIC0 register), the UBTITn interrupt is generated under the conditions of the pending mode. UBn TT3 UBn TT2 UBn TT1 UBn TT0 Number of data of transmit FIFOn set as trigger 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes Pointer mode Pending mode 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Settable Setting prohibited Settable Caution In the pointer mode (UBnITM bit = 1 in the UBnFIC0 register), the number of transmit data set as the trigger can be only 1 byte (UBnTT3 to UBnTT0 bits = 0000), and other settings are prohibited. If a setting of other than 1 byte is made, the operation is not guaranteed. Remark n = 0, 1 User's Manual U16031EJ4V1UD 497 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/2) Bit position 3 to 0 Bit name UBnRT3 to UBnRT0 Function Set the number of receive FIFOn receive data to be the trigger. Each time data of the specified number has been stored from receive shift register n to receive FIFOn, the UBTIR interrupt is generated. In the pending mode (UBnITM bit = 0 in the UBnFIC0 register), the UBTIRn interrupt is generated under the conditions of the pending mode. UBn RT3 UBn RT2 UBn RT1 UBn RT0 Number of data of receive FIFOn set as trigger 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes Pointer mode Pending mode 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Settable Setting prohibited Settable Caution In the pointer mode (UBnIRM bit = 1 in the UBnFIC0 register), the number of receive data set as the trigger can be only 1 byte (UBnRT3 to UBnRT0 bits = 0000), and other settings are prohibited. If a setting of other than 1 byte is made, the operation is not guaranteed. Remark n = 0, 1 498 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (9) UARTBn FIFO status register 0 (UBnFIS0) (n = 0, 1) The UBnFIS0 register is valid in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register). It is used to read the number of bytes of the data stored in receive FIFOn. This register is read-only, in 8-bit units. 7 UB0FIS0 0 6 0 5 0 4 3 2 1 0 Address FFFFFA0EH After reset 00H UB0RB4 UB0RB3 UB0RB2 UB0RB1 UB0RB0 UB1FIS0 0 0 0 UB1RB4 UB1RB3 UB1RB2 UB1RB1 UB1RB0 FFFFFA2EH 00H Bit position 4 to 0 Bit name UBnRB4 to UBnRB0 Function Indicates the number of bytes (readable bytes) of the data stored in receive FIFOn as a receive FIFOn pointer. UBn RB4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 UBn RB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 UBn RB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 UBn RB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 UBn RB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes Invalid Receive FIFOn pointer Other than above Remark n = 0, 1 User's Manual U16031EJ4V1UD 499 CHAPTER 10 SERIAL INTERFACE FUNCTION (10) UARTBn FIFO status register 1 (UBnFIS1) (n = 0, 1) The UBnFIS1 register is valid in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register). This register can be used to read the number of vacant bytes of transmit FIFOn. This register is read-only, in 8-bit units. Caution The values of the UBnTB4 to UBnTB0 bits are reflected after transmit data has been written to the UBnTX register and then time of two cycles of fX/4 (fX: main clock) has passed. Therefore, care must be exercised when referencing the UBnFIS1 register after transmit data has been written to the UBnTX register. 7 UB0FIS1 0 6 0 5 0 4 UB0TB4 3 UB0TB3 2 UB0TB2 1 UB0TB1 0 UB0TB0 Address FFFFFA0FH After reset 10H UB1FIS1 0 0 0 UB1TB4 UB1TB3 UB1TB2 UB1TB1 UB1TB0 FFFFFA2FH 10H Bit position 4 to 0 Bit name UBnTB4 to UBnTB0 Function Indicates the number of vacant bytes of transmit FIFOn (bytes that can be written) as a transmit FIFOn pointer. UBn TB4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 UBn TB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 UBn TB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 UBn TB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 UBn TB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes Invalid Transmit FIFOn pointer Other than above Remark n = 0, 1 500 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.4 Interrupt requests The following five types of interrupt requests are generated from UARTBn (n = 0, 1). * Reception error interrupt (UBTIREn) * Reception completion interrupt (UBTIRn) * Transmission completion interrupt (UBTITn) * FIFO transmission completion interrupt (UBTIFn) * Reception timeout interrupt (UBTITOn) The default priorities among these five types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, transmission completion interrupt, FIFO transmission completion interrupt, and reception timeout interrupt. Table 10-2. Generated Interrupts and Default Priorities Interrupt Reception error Reception completion Transmission completion FIFO transmission completion Reception timeout Priority 1 2 3 4 5 (1) Reception error interrupt (UBTIREn) (a) Single mode When reception is enabled, a reception error interrupt is generated according to the logical OR of the three types of reception errors (parity error, framing error, overrun error) explained for the UBnSTR register. When reception is disabled, no reception error interrupt is generated. (b) FIFO mode When reception is enabled, a reception error interrupt is generated according to the logical OR of the three types of reception errors (parity error, framing error, overflow error) explained for the UBnSTR register. When reception is disabled, no reception error interrupt is generated. User's Manual U16031EJ4V1UD 501 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Reception completion interrupt (UBTIRn) (a) Single mode When reception is enabled, a reception completion interrupt is generated if data is shifted into receive shift register n and stored in the UBnRX register (if the receive data can be read). When reception is disabled, no reception completion interrupt is generated. (b) FIFO mode When reception is enabled, a reception completion interrupt is generated if data is shifted into receive shift register n and receive data of the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register is transferred to receive FIFOn (if receive data of the specified number can be read). When reception is disabled, no reception completion interrupt is generated. (3) Transmission completion interrupt (UBTITn) (a) Single mode The transmission completion interrupt is generated if transmit data of one frame, including 7 or 8 bits of characters, is shifted out from transmit shift register n and the UBnTX register becomes vacant (if transmit data can be written). (b) FIFO mode The transmission completion interrupt is generated if transmit data of the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register is transferred to transmit shift register n from transmit FIFOn (if transmit data of the specified number can be written). (4) FIFO transmission completion interrupt (UBTIFn) (a) Single mode Cannot be used. (b) FIFO mode The FIFO transmission completion interrupt is generated when no more data is in transmit FIFOn and transmit shift register n (when the FIFO and register become empty). After the FIFO transmission completion interrupt has occurred, clear the interrupt held pending (UBTITn) in the pending mode (UBnITM bit = 0 in the UBnFIC0 register) by clearing the FIFO (UBnTFC bit = 1 in the UBnFIC0 register). Caution If the FIFO transmission completion interrupt is generated (all transmit data are not transmitted) because writing the next transmit data to transmit FIFOn is delayed, do not clear the FIFO. 502 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Reception timeout interrupt (UBTITOn) (a) Single mode Cannot be used. (b) FIFO mode The reception timeout interrupt is generated if data is stored in receive FIFOn when the next data does not come (start bit is not detected) even after the next data reception wait time specified by the UBnTC4 to UBnTC0 bits of the UBnFIC1 register has elapsed, when the timeout counter function is used (UBnTCE bit = 1 in the UBnFIC1 register). The reception timeout interrupt is not generated while reception is disabled. If receive data of the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register is not received, the timing of reading the number of receive data less than the specified number can be set by the reception timeout interrupt. Since the timeout counter starts counting at start bit detection, a receive timeout interrupt does not occur if data of 1 character has not been received. User's Manual U16031EJ4V1UD 503 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.5 Control method (1) Single mode/FIFO mode The single mode or FIFO mode can be selected by using the UBnMOD bit of the UBnFIC0 register. (a) Single mode * Each of the UBnRX and UBnTX registers consists of 8 bits x 1 stage. * When 1 byte of data is received, the UBTIRn interrupt is generated. * If the next reception operation of UARTBn is completed before the receive data of the UBnRX register is read after the UBTIRn interrupt has been generated, the UBTIREn interrupt is generated and an overrun error occurs. (b) FIFO mode * Receive FIFOn (UBnRXAP register) consists of 16 bits x 16 stages and transmit FIFOn consists of 8 bits x 16 stages. * Receive FIFOn can recognize error data by reading the 16-bit UBnRXAP register only when a reception error (parity error or framing error) occurs. * Transmission is started when transmission is enabled (UBnTXE bit = 1 in the UBnCTL0 register) after transmit data of at least the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register and 16 bytes or less are written to transmit FIFOn. * The pending mode or pointer mode can be selected for the generation timing of the UBTITn and UBTIRn interrupts. 504 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Pending mode/pointer mode The pending mode or pointer mode can be selected by using the UBnITM and UBnIRM bits of the UBnFIC0 register in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register). If transmission is started by writing data of more than double the amount set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register to transmit FIFOn, the transmission completion interrupt (UBTITn) may occur more than once. The reception completion interrupt (UBTIRn) may also occur more than once if the number of receive data set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register is 8 bytes or less in receive FIFOn. In the pending or pointer mode, it can be specified how an interrupt is handled after it has been held pending. (a) Pending mode (i) During transmission (writing to transmit FIFOn) * If the data of the first transmission completion interrupt (UBTITn) is not written to transmit FIFOn after the interrupt has occurred, the second UBTITn interrupt does not occur (is held pending) even if the generation condition of the second UBTITn interrupt is satisfied (when transmit data of the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register is transferred from transmit FIFOn to the transmit shift register). When data for the first UBTITn interrupt is later written to transmit FIFOn, the pending UBTITn interrupt is generatedNote. Note The number of pending interrupts is as follows. When trigger is set to 1 byte (UBnTT3 to UBnTT0 bits of UBnFIC2 register = 0000): 15 times max. When trigger is set to 2 bytes (UBnTT3 to UBnTT0 bits of UBnFIC2 register = 0001): 7 times max. : When trigger is set to 6 bytes (UBnTT3 to UBnTT0 bits of UBnFIC2 register = 0101): 1 time max. When trigger is set to 7 bytes (UBnTT3 to UBnTT0 bits of UBnFIC2 register = 0110): 1 time max. When trigger is set to 8 bytes (UBnTT3 to UBnTT0 bits of UBnFIC2 register = 0111): 1 time max. * In the pending mode, transmit data of the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register is always written to transmit FIFOn when the transmission completion interrupt (UBTITn) occurs. Writing data to transmit FIFOn is prohibited if the data is more or less than the specified number. If data more or less than the specified number is written, the operation is not guaranteed. * Fix the UBnTT3 to UBnTT0 bits of the UBnFIC2 register to 0000 (set number of transmit data: 1 byte) to write transmit data to transmit FIFOn by DMA. If any other setting is made, the operation is not guaranteed. User's Manual U16031EJ4V1UD 505 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) During reception (reading from receive FIFOn) * If data for the first reception completion interrupt (UBTIRn) is not read from receive FIFOn, the second UBTIRn interrupt does not occur (is held pending) even if the generation condition of the second UBTIRn is satisfied (if receive data of the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register can be read from receive FIFOn). When data for the first UBTIRn interrupt is later read from the receive FIFOn, the pending UBTIRn interrupt is generatedNote. Note The number of pending interrupts is as follows. When trigger is set to 1 byte (UBnRT3 to UBnRT0 bits of UBnFIC2 register = 0000): 15 times max. When trigger is set to 2 bytes (UBnRT3 to UBnRT0 bits of UBnFIC2 register = 0001): 7 times max. : When trigger is set to 6 bytes (UbnRT3 to UBnRT0 bits of UBnFIC2 register = 0101): 1 time max. When trigger is set to 7 bytes (UBnRT3 to UBnRT0 bits of UBnFIC2 register = 0110): 1 time max. When trigger is set to 8 bytes (UBnRT3 to UBnRT0 bits of UBnFIC2 register = 0111): 1 time max. * In the pending mode, receive data of the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register is always read from receive FIFOn when the reception completion interrupt (UBTIRn) occurs. Reading data from receive FIFOn is prohibited if the data is more or less than the specified number. If data more or less than the specified number is read, the operation is not guaranteed. * Fix the UBnRT3 to UBnRT0 bits of the UBnFIC2 register to 0000 (set number of receive data: 1 byte) to read receive data from receive FIFOn by DMA. If any other setting is made, the operation is not guaranteed. (b) Pointer mode (i) During transmission (writing to transmit FIFOn) * Each time the data of 1 byte is transferred to transmit shift register n from transmit FIFOn, a transmission completion interrupt (UBTITn) occurs. * In the pointer mode, be sure to fix the UBnTT3 to UBnTT0 bits of the UBnFIC2 register to 0000 (set number of transmit data: 1 byte) as the number of transmit data set as the trigger for transmit FIFOn when the transmission completion interrupt (UBTITn) occurs. If any other setting is made, the operation is not guaranteed. * Writing transmit data to transmit FIFOn by DMA is prohibited. The operation is not guaranteed if DMA control is used. * After the transmission completion interrupt (UBTITn) has been acknowledged, data of the number of vacant bytes of transmit FIFOn can be written to transmit FIFOn by referencing the UBnFIS1 register. 506 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) During reception (reading from receive FIFOn) * Each time the data of 1 byte is transferred to receive FIFOn from receive shift register n, a reception completion interrupt (UBTIRn) occurs. * In the pointer mode, be sure to fix the UBnRT3 to UBnRT0 bits of the UBnFIC2 register to 0000 (set number of receive data: 1 byte) as the number of receive data set as the trigger for receive FIFOn when the reception completion interrupt (UBTIRn) occurs. If any other setting is made, the operation is not guaranteed. * Reading receive data from receive FIFOn by DMA is prohibited. The operation is not guaranteed if DMA control is used. * After the reception completion interrupt (UBTIRn) has been acknowledged, data of the number of bytes stored in receive FIFOn can be read from receive FIFOn by referencing the UBnFIS0 register. In some cases, however, data is not stored in receive FIFOn even though the UBTIRn interrupt is generated (UBnRB4 to UBnRB0 bits = 00000 in the UBnFIS0 register). In these cases, do not read data from receive FIFOn. Always read data from receive FIFOn when the number of bytes stored in receive FIFOn is 1 byte or more (UBnRB4 to UBnRB0 bits = other than 00000). 10.2.6 Operation (1) Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 10-2. The character bit length within one data frame, the type of parity, and the stop bit length are specified by the UARTBn control register 0 (UBnCTL0) (n = 0, 1). Also, data is transferred with LSB first/MSB first. Figure 10-2. Asynchronous Serial Interface Transmit/Receive Data Format (LSB-First Transfer) 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bits Character bits * Start bit *** 1 bit * Character bits *** 7 bits or 8 bits * Parity bit *** Even parity, odd parity, 0 parity, or no parity * Stop bits *** 1 bit or 2 bits User's Manual U16031EJ4V1UD 507 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmit operation In the single mode (UBnMOD bit = 0 in the UBnFIC0 register), transmission is enabled when the UBnTXE bit of the UBnCTL0 register is set to 1, and transmission is started when transmit data is written to the UBnTX register (n = 0, 1). In the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register), transmission is started when transmit data of at least the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register and 16 bytes or less is written to transmit FIFOn and then the UBnTXE bit is set to 1. Caution Setting the UBnTXE bit of the UBnCTL0 register to 1 before writing transmit data to transmit FIFOn in the FIFO mode is prohibited. The operation is not guaranteed if this setting is made. (a) Transmission enabled state This state is set by the UBnTXE bit in the UBnCTL0 register (n = 0, 1). * UBnTXE = 1: Transmission enabled state * UBnTXE = 0: Transmission disabled state However, when the transmission enabled state is set, to use UARTB0, which shares pins with clocked serial interface 30 (CSI30), the CSICAE0 bit of clocked serial interface mode register 30 (CSIM30) should be cleared to 0. Since UARTBn does not have a CTS (transmission enabled signal) input pin, a port should be used to confirm whether the destination is in the reception enabled state. (b) Starting a transmit operation * In single mode (UBnMOD bit = 0 in UBnFIC0 register) In the single mode, transmission is started when transmit data is written to the UBnTX register while transmission is enabled (n = 0, 1). * In FIFO mode (UBnMOD bit = 1 in UBnFIC0 register) In the FIFO mode, transmission is started when transmit data of at least the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register and 16 bytes or less is written to transmit FIFOn and then transmission is enabled (UBnTXE bit = 1). Data in transmit data register n (UBnTX register in single mode or transmit FIFOn in the FIFO mode) is transferred to transmit shift register n when transmission is started. Then, transmit shift register n outputs data to the TXDn pin sequentially beginning with the LSB (the transmit data is transferred sequentially starting with the start bit). The start bit, parity bit, and stop bits are added automatically (n = 0, 1). 508 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transmission interrupt request (i) Transmission completion interrupt (UBTITn) * In single mode (UBnMOD bit = 0 in UBnFIC0 register) In the single mode, the transmission completion interrupt (UBTITn) occurs when transmit data can be written to the UBnTX register (when 1 byte of data is transferred from the UBnTX register to transmit shift register n) (n = 0, 1). * In FIFO mode (UBnMOD bit = 1 in UBnFIC0 register) In the FIFO mode, the UBTITn interrupt occurs when transmit data of the number set as the trigger specified by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register is transferred from transmit FIFOn to transmit shift register n (if transmit data of the number set as the trigger can be written) (n = 0, 1). * If pending mode is specified (UBnITM bit = 0 in UBnFIC0 register) in FIFO mode If the pending mode is specified in the FIFO mode, the second UBTITn interrupt is held pending after the first UBTITn interrupt has occurred, until as many transmit data as the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register are written to transmit FIFOn, even if the generation condition of the second UBTITn interrupt is satisfied. When as many transmit data as the number set as the trigger are written to transmit FIFOn in response to the first UBTITn interrupt, the second pending UBTITn interrupt is generated (n = 0, 1). * If pointer mode is specified (UBnITM bit = 1 in UBnFIC0 register) in FIFO mode If the pointer mode is specified in the FIFO mode, the second UBTITn interrupt occurs when the generation condition of the second UBTITn interrupt is satisfied even if as many transmit data as the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register are not written to transmit FIFOn when the first UBTITn interrupt occurs (n = 0, 1). (ii) FIFO transmission completion interrupt (UBTIFn) The FIFO transmission completion interrupt (UBTIFn) occurs when no more data is in transmit FIFOn and transmit shift register n in the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register) (n = 0, 1). After the UBTIFn interrupt has occurred, clear the pending UBTITn interrupt in the pending mode (UBnITM bit = 0 in the UBnFIC0 register) by clearing the FIFO (UBnTFC bit = 1 in the UBnFIC0 register). If the UBTIFn interrupt occurs because writing the next transmit data to transmit FIFOn is delayed (if all transmit data have not been transmitted), do not clear the FIFO. If the data to be transmitted next has not been written to transmit data register n, the transmit operation is suspended. Caution In the single mode, the transmission completion interrupt (UBTITn) occurs when the UBnTX register becomes empty (when 1 byte of data is transferred from the UBnTX register to transmit shift register n). In the FIFO mode, the FIFO transmission completion interrupt (UBTIFn) occurs when data is no longer in transmit FIFOn and transmit shift register n (when the FIFO and register are vacant). However, the UBTITn interrupt or UBTIFn interrupt is not generated if transmit data register n becomes empty due to RESET input. User's Manual U16031EJ4V1UD 509 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-3. Timing of Asynchronous Serial Interface Transmission Completion Interrupt (UBTITn) TXDn (output) Start D0 D1 D2 D6 D7 Parity Stop UBTITn (output) Remarks 1. In the FIFO mode, the UBTITn interrupt occurs at the above timing when as many transmit data as the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register are serially transferred. 2. n = 0, 1 Figure 10-4. Timing of Asynchronous Serial Interface FIFO Transmission Completion Interrupt (UBTIFn) TXDn (output) Start D0 D1 D2 D6 D7 Parity Stop UBTIFn (output) Remarks 1. The UBTIFn interrupt occurs at the above timing when data is no longer in transmit FIFOn and transmit shift register n (when the FIFO and register are vacant). 2. n = 0, 1 510 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission operation * In single mode (UBnMOD bit = 0 in UBnFIC0 register) In the single mode, the next data can be written to the UBnTX register as soon as transmit shift register n has started a shift operation (n = 0, 1). The timing of transfer can be identified by the transmission completion interrupt (UBTITn). By writing the next transmit data to the UBnTX register via the UBTITn interrupt within one data frame transmission period, data can be transmitted without an interval and an efficient communication rate can be realized. Caution Confirm that the UBnTSF bit of the UBnSTR register is 0 before executing initialization during transmission processing. If initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed. * If pending mode is specified (UBnITM bit = 0 in UBnFIC0 register) in FIFO mode If transmit data of at least the number set as the transmit trigger by UBnTT3 to UBnTT0 bits of the UBnFIC2 register and 16 bytes or less is written to transmit FIFOn, transmission starts. If the pending mode is specified in the FIFO mode, as many of the next transmit data as the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register can be written to transmit FIFOn as soon as transmit shift register n has started shifting the last data of the specified number of data. The timing of transfer can be identified by the UBTITn interrupt. By writing as many of the next transmit data as the number set as the trigger to transmit FIFOn or writing the data to the FIFO within the transmission period of the data in transmit FIFOn via the UBTITn interrupt, data can be transmitted without an interval and an efficient communication rate can be realized. Caution Confirm that the UBnTSF bit of the UBnSTR register is 0 before executing initialization during transmission processing (this can also be done by the FIFO transmission completion interrupt (UBTIFn)). If initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed. To write transmit data to transmit FIFOn by DMA control, set the number of transmit data specified as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register to 1 byte; otherwise the operation will not be guaranteed. * If pointer mode is specified (UBnITM bit = 1 in UBnFIC0 register) in FIFO mode If the pointer mode is specified in the FIFO mode, a UBTITn interrupt occurs and the next data can be written to transmit FIFOn as soon as transmit shift register n has started shifting the number of transmit data set as the trigger. At this time, as many data as the number of vacant bytes of transmit FIFOn can be written by referencing the UBnFIS1 register. The timing of transfer can be identified by the UBTITn interrupt. By writing as many of the next transmit data as the number specified as the trigger to transmit FIFOn (= 1 byte) or writing the data to the FIFO within the transmission period of the data in transmit FIFOn via the UBTITn interrupt, data can be transmitted without an interval and an efficient communication rate can be realized. Caution Confirm that the UBnTSF bit of the UBnSTR register is 0 before executing initialization during transmission processing (this can also be done by the FIFO transmission completion interrupt (UBTIFn)). If initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed. User's Manual U16031EJ4V1UD 511 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Receive operation The awaiting reception state is set by setting the UBnPWR bit to 1 in the UBnCTL0 register and then setting UBnRXE to 1 in the UBnCTL0 register (n = 0, 1). RXDn pin sampling begins and a start bit is detected. When the start bit is detected, the receive operation begins, and data is stored sequentially in receive shift register n according to the baud rate that was set. In the single mode (UBnMOD bit = 0 in the UBnFIC0 register), a reception completion interrupt (UBTIRn) is generated each time the reception of one frame of data is completed. transferred from the UBnRX register to memory by this interrupt servicing. In the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register), the UBTIRn interrupt occurs when as many receive data as the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register are transferred to receive FIFOn. If the pending mode is specified (UBnIRM bit = 0 in the UBnFIC0 register) in the FIFO mode, as many receive data as the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register can be read from receive FIFOn. If the pointer mode is specified (UBnIRM bit = 1 in the UBnFIC0 register) in the FIFO mode, as many data as the number of bytes stored in receive FIFOn (0 bytes or more) can be read from receive FIFOn by referencing the number of receive data specified as the trigger by the UBnRT3 to UBnRT0 bits (1 byte) or the UBnFIS0 register. Caution If the pointer mode is specified in the FIFO mode and if as many data as the number of bytes stored in receive FIFOn are read by referencing the UBnFIS0 register, no data may be stored in receive FIFOn (UBnRB4 to UBnRB0 bits = 00000 in the UBnFIS0 register) even though the reception completion interrupt (UBTIRn) has occurred. In this case, do not read data from receive FIFOn. Be sure to read data from receive FIFOn after confirming that the number of bytes stored in receive FIFOn = 1 byte or more (UBnRB4 to UBnRB0 bits = other than 00000). (a) Reception enabled state This state is set by the UBnRXE bit in the UBnCTL0 register (n = 0, 1). * UBnRXE = 1: Reception enabled state * UBnRXE = 0: Reception disabled state However, when the reception enabled state is set, to use UARTB0, which shares pins with clocked serial interface 30 (CSI30), the operation of CSI30 must be disabled by clearing the CSICAE0 bit of clocked serial interface mode register 30 (CSIM30) to 0 (n = 0, 1). In the reception disabled state, the reception hardware stands by in the initial state. At this time, the reception completion interrupt or reception error interrupt does not occur, and the contents of receive data register n (UBnRX register in the single mode or receive FIFOn in the FIFO mode (UBnRXAP register)) are retained. (b) Starting a receive operation A receive operation is started by the detection of a start bit. The RXDn pin is sampled using the serial clock from UARTBn control register 2 (UBnCTL2) (n = 0, 1). Normally, the receive data is 512 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Reception completion interrupt (i) Reception completion interrupt (UBTIRn) * In single mode (UBnMOD bit = 0 in UBnFIC0 register) When UBnRXE bit = 1 in the UBnCTL0 register and the reception of one frame of data is completed (the stop bit is detected) in the single mode, a reception completion interrupt request (UBTIRn) is generated and the receive data in receive shift register n is transferred to the UBnRX register at the same time (n = 0, 1). Also, if an overrun error occurs, the receive data at that time is not transferred to the UBnRX register, and a reception error interrupt (UBTIREn) is generated. If a parity error or framing error occurs during the reception operation, the reception operation continues up to the position at which the stop bit is received. After completion of reception, an UBTIREn interrupt occurs (the receive data in receive shift register n is transferred to the UBnRX register). If the UBnRXE bit is reset (0) during a receive operation, the receive operation is immediately stopped. At this time, the contents of the UBnRX register remain unchanged, the contents of the UARTBn status register (UBnSTR) are cleared, and the UBTIRn and UBTIREn interrupts do not occur. No UBTIRn interrupt is generated when UBnRXE = 0 (reception is disabled). * In FIFO mode (UBnMOD bit = 1 in UBnFIC0 register) In the FIFO mode, the reception completion interrupt (UBTIRn) occurs when data of one frame has been received (stop bit is detected) and when as many receive data as the number specified as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register are transferred from receive shift register n to receive FIFOn (n = 0, 1). If an overflow error occurs, the receive data is not transferred to receive FIFOn and the reception error interrupt (UBTIREn) occurs. If a parity error or framing error occurs during reception, reception continues up to the reception position of the stop bit. After reception has been completed, the UBTIREn interrupt occurs and the receive data in receive shift register n is transferred to receive FIFOn. At this time, error information is appended as the UBnPEF or UBnFEF bit = 1 in the UBnRXAP register. If the UBTIREn interrupt occurs, the error data can be recognized by reading receive FIFOn as a 16-bit register, UBnRXAP. User's Manual U16031EJ4V1UD 513 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) Reception timeout interrupt (UBTITOn) (in FIFO mode only) When the timeout counter function (UBnTCE bit = 1 in the UBnFIC1 register) is used in the FIFO mode, the reception timeout interrupt (UBTITOn) occurs if the next data does not come even after the next data reception wait time specified by the UBnTC4 to UBnTC0 bits of the UBnFIC1 register has elapsed and if data is stored in receive FIFOn (n = 0, 1). The UBTITOn interrupt does not occur while reception is disabled. If as many receive data as the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register are not received, the timing of reading less receive data than the specified number can be set by the UBTITOn interrupt. Since the timeout counter starts counting at start bit detection, a receive timeout interrupt does not occur if data of 1 character has not been received. Figure 10-5. Timing of Asynchronous Serial Interface Reception Completion Interrupt (UBTIRn) RXDn (input) Start D0 D1 D2 D6 D7 Parity Stop UBTIRn (output) Receive data register n Cautions 1. Be sure to read all the data (the number of data indicated by the UBnRB4 to UBnRB0 bits of the UBnFIS0 register) stored in receive data register n (UBnRX register in the single mode or receive FIFOn in the FIFO mode (UBnRXAP register)) even when a reception error occurs. Unless receive data register n is read, an overrun error occurs when the next data is received, causing the reception error status to persist. If the pending mode is specified in the FIFO mode, however, be sure to clear the FIFO (UBnRFC bit = 1 in the UBnFIC0 register) after reading the data stored in receive FIFOn. In the FIFO mode, the FIFO can be cleared even without reading the data stored in receive FIFOn. If a parity error or framing error occurs in the FIFO mode, the UBnRXAP register can be read in 16-bit (halfword) units. 2. Data is always received with one stop bit. A second stop bit is ignored. Remark n = 0, 1 514 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Reception error In the single mode (UBnMOD bit = 0 in the UBnFIC0 register), the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. In the FIFO mode (UBnMOD bit = 1 in the UBnFIC0 register), the three types of errors that can occur during a receive operation are a parity error, framing error, and overflow error. As a result of data reception, the UBnPE, UBnFE, or UBnOVE bit of the UBnSTR register is set to 1 if a parity error, framing error, or overrun error occurs in the single mode. The UBnOVF bit of the UBnSTR register is set to 1 if an overflow error occurs in the FIFO mode. The UBnPEF or UBnFEF bit of the UBnRXAP register is set to 1 if a parity error or framing error occurs in the FIFO mode. At the same time, a reception error interrupt (UBTIREn) occurs. The contents of the error can be detected by reading the contents of the UBnSTR or UBnRXAP register. The contents of the UBnSTR register are reset when 0 is written to the UBnOVF, UBnPE, UBnFE, or UBnOVE bit, or the UBnPWR or UBnRXE bit of the UBnCTL0 register. The contents of the UBnRXAP register are reset when 0 is written to the UBnPWR bit of the UBnCTL0 register. Table 10-3. Reception Error Causes Error Flag Valid Operation Mode UBnPE Single mode UBnPE Parity error The parity specification during transmission does not match the parity of the receive data No stop bit detected The reception of the next data is completed before data is read from the UBnRX register UBnOVF FIFO mode UBnOVF Overflow error The reception of the next data is completed while receive FIFOn is full and before data is read. UBnPEF UBnPEF Parity error The parity specification during transmission does not match the parity of the data to be received. UBnFEF UBnFEF Framing error The stop bit is not detected when the target data is loaded. Error Flag Reception Error Cause UBnFE UBnOVE UBnFE UBnOVE Framing error Overrun error Remark n = 0, 1 User's Manual U16031EJ4V1UD 515 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is even. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 1 * If the number of bits with the value "1" within the transmit data is even: 0 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) Odd parity (i) During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is odd. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 0 * If the number of bits with the value "1" within the transmit data is even: 1 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity During transmission the parity bit is set to "0" regardless of the transmit data. During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of whether the parity bit is "0" or "1". (d) No parity No parity bit is added to the transmit data. During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit, no parity error is generated. 516 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Receive data noise filter The RXDn signal is sampled at the rising edge of the input clock (fX/4) (fX: main clock). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 10-7). Also, since the circuit is configured as shown in Figure 10-6, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. Figure 10-6. Noise Filter Circuit fX/4 RXDn In Q Internal signal A In LD_EN Q Internal signal B Match detector Remarks 1. n = 0, 1 2. fX: Main clock Figure 10-7. Timing of RXDn Signal Judged as Noise fX/4 RXDn (input) Internal signal A Match Mismatch (judged as noise) Match Mismatch (judged as noise) Internal signal B Remarks 1. n = 0, 1 2. fX: Main clock User's Manual U16031EJ4V1UD 517 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.7 Dedicated baud rate generators 0, 1 (BRG0, BRG1) A dedicated baud rate generator, which consists of a 16-bit programmable counter, generates serial clocks during transmission/reception in UARTBn. The dedicated baud rate generator output can be selected as the serial clock for each channel. Separate 16-bit counters exist for transmission and for reception. The baud rate for transmission/reception is the same at the same channel. (1) Baud rate generator configuration Figure 10-8. Baud Rate Generator Configuration UBnPWR, UBnTXE (or UBnRXE) fX/4 Clock 16-bit counter Match detector 1/2 Baud rate UBnCTL2: UBnBRS15 to UBnBRS0 Remarks 1. n = 0, 1 2. fX: Main clock (a) Base clock (Clock) When UBnPWR bit = 1 in the UBnCTL0 register, the input clock (fX/4) is supplied to the transmission/reception unit (fX: main clock). This clock is called the base clock. When UBnPWR = 0, the clock signal is fixed at low level. 518 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Serial clock generation A serial clock can be generated according to the settings of the UBnCTL2 register (n = 0, 1). The 16-bit counter divisor value can be selected according to the UBnBRS15 to UBnBRS0 bits of the UBnCTL2 register. (a) Baud rate The baud rate is the value obtained according to the following formula. Baud rate = Base clock frequency 2xk [bps] Base clock frequency = fX/4 (fX: main clock) k = Value set according to UBnBRS15 to UBnBRS0 bits of UBnCTL2 register (k = 4, 5, 6, ..., 65,535) (b) Baud rate error The baud rate error is obtained according to the following formula. Error (%) = Actual baud rate (baud rate with error) Desired baud rate (normal baud rate) - 1 x 100 [%] Cautions 1. Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. Make sure that the baud rate error during reception is within the allowable baud rate range during reception, which is described in paragraph (4). Example: Main clock (fX) = 150 MHz = 150,000,000 Hz Settings of UBnBRS15 to UBnBRS0 bits in UBnCTL2 register = 0000000001111010B (k = 122) Target baud rate = 153,600 bps Baud rate = 150 M/4/(2 x 122) = 150,000,000/4/(2 x 122) = 153,689 [bps] Error = (153,689/153,600 - 1) x 100 = 0.058 [%] User's Manual U16031EJ4V1UD 519 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate setting example Table 10-4. Baud Rate Generator Setting Data Baud Rate (bps) 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 153,600 312,500 fX = 150 MHz k 62,500 31,250 15,625 7,813 3,906 1,953 977 600 488 244 122 60 ERR 0.000 0.000 0.000 -0.006 0.006 0.006 -0.045 0.000 0.058 0.058 0.058 0.000 k 55,417 27,708 13,854 6,927 3,464 1,732 866 532 433 216 108 53 fX = 133 MHz ERR -0.001 0.001 0.001 0.001 -0.013 -0.013 -0.013 0.000 -0.013 0.218 0.218 0.377 k 41,667 20,833 10,417 5,208 2,604 1,302 651 400 326 163 81 40 fX = 100 MHz ERR -0.001 0.002 -0.003 0.006 0.006 0.006 0.006 0.000 -0.147 -0.147 0.469 0.000 k 33,333 16,667 8,333 4,167 2,083 1,042 521 320 260 130 65 32 fX = 80 MHz ERR 0.001 -0.002 0.004 -0.008 0.016 -0.032 -0.032 0.000 0.160 0.160 0.160 0.000 Caution Remark The maximum allowable frequency of the main clock (fX) is 150 MHz. fX: k: ERR: Main clock Settings of UBnBRS15 to UBnBRS0 bits in UBnCTL2 register (n = 0, 1) Baud rate error [%] 520 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination's baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range. Figure 10-9. Allowable Baud Rate Range During Reception Latch timing UARTBn Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum allowable value Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable value Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax Remark n = 0, 1 As shown in Figure 10-9, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the UBnCTL2 register. If all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. Applying this to 11-bit reception is, theoretically, as follows. FL = (Brate)-1 Brate: UARTBn baud rate (n = 0, 1) k: FL: UBnCTL2 setting value (n = 0, 1) 1-bit data length Latch timing margin: 2 clocks Minimum allowable value: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL User's Manual U16031EJ4V1UD 521 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the maximum baud rate that can be received at the transfer destination is as follows. BRmax = (FLmin/11) = -1 22 k 21k + 2 Brate Similarly, the maximum allowable value can be obtained as follows. 10 11 x FLmax = 11 x FL - FLmax = 21k - 2 20 k k+2 2xk FL x 11 x FL = 21k - 2 2xk FL Therefore, the minimum baud rate that can be received at the transfer destination is as follows. BRmin = (FLmax/11) = -1 20 k 21k - 2 Brate The allowable baud rate error of UARTBn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. Table 10-5. Maximum and Minimum Allowable Baud Rate Error Division Ratio (k) 4 8 16 32 64 128 256 512 1,024 2,048 4,096 8,192 16,384 32,768 65,535 Maximum Allowable Baud Rate Error +2.33 % +3.53 % +4.14 % +4.45 % +4.61 % +4.68 % +4.72 % +4.74 % +4.75 % +4.76 % +4.76 % +4.76 % +4.76 % +4.76 % +4.76 % Minimum Allowable Baud Rate Error -2.44 -3.61 -4.19 -4.48 -4.62 -4.69 -4.73 -4.74 -4.75 -4.76 -4.76 -4.76 -4.76 -4.76 -4.76 Remarks 1. The reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). The higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: UBnCTL2 setting value (n = 0, 1) 522 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. Figure 10-10. Transfer Rate During Continuous Transmission 1 data frame Start bit of second byte Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Start bit FL Bit 0 FL FL FL FL FL FLstp FL Representing the 1-bit data length by FL, the stop bit length by FLstp, and the base clock frequency by fX/4 (fX: main clock) yields the following equation. FLstp = FL + 2/(fX/4) Therefore, the transfer rate during continuous transmission is as follows. Transfer rate = 11 x FL + 2/(fX/4) User's Manual U16031EJ4V1UD 523 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.8 Control flow (1) Example of continuous transmission processing flow in single mode (CPU control) Figure 10-11. Example of Continuous Transmission Processing Flow in Single Mode (CPU Control) START Set UARTB-related registers UBnTXE = 1 (UBnCTL0) : Enable transmission Write UBnTX register : Write transmit data UBTITn interrupt = 1? Yes No : UBnTX register can be written? End of transmission? Yes No : All transmit data written? UBnTSF = 0? (UBnSTR) Yes UBnTXE = 0 (UBnCTL0) No : Transmission completed? : Disable transmission END Remark n = 0, 1 524 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Example of continuous reception processing flow in single mode (CPU control) Figure 10-12. Example of Continuous Reception Processing Flow in Single Mode (CPU Control) START Set UARTB-related registers UBnRXE = 1 (UBnCTL0) : Enable reception UBTIREn interrupt = 1? Yes No : Reception error occurred? No UBTIRn interrupt = 1? Yes Error processing in single mode Read UBnRX register : 1-byte reception completed? : Read receive data Reception completed? Yes UBnRXE= 0 (UBnCTL0) No : Reception completed? : Disable reception END Remark n = 0, 1 User's Manual U16031EJ4V1UD 525 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Example of continuous transmission processing flow in single mode (DMA control) Figure 10-13. Example of Continuous Transmission Processing Flow in Single Mode (DMA Control) START Set UARTB/DMAC-related registersNote DTFRm register = 3CH : Assign DMA transfer destination (in the case of UBTIT0) : Clear DFm bit DTFRm register = 3CH Emm = 1 (DCHCm) : Enable DMA transfer UBnTXE = 1 (UBnCTL0) : Enable transmission Write UBnTX register : Write transmit data DMA completed? Yes No : DMA transfer completed? UBnTSF = 0? (UBnSTR) Yes UBnTXE = 0 (UBnCTL0) No : Transmission completed? : Disable transmission END Note In this control flow example, transmission of the first byte of the data is executed by a CPU write operation. Exercise care in setting the number of data for DMA transfer (DBCm register) and the source address (DSAmH and DSAmL registers). Remark n = 0, 1 m = 0 to 3 526 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Example of continuous reception processing flow in single mode (DMA control) Figure 10-14. Example of Continuous Reception Processing Flow in Single Mode (DMA Control) START Set UARTB/DMAC-related registers DTFRm register = 3BH : Assign DMA transfer destination (in the case of UBTIR0) : Clear DFm bit DTFRm register = 3BH Emm = 1 (DCHCm) : Enable DMA transfer UBnRXE = 1 (UBnCTL0) : Enable reception DMA completed? Yes UBnRXE = 0 (UBnCTL0) No : DMA transfer (reception) completed? : Disable reception END Remark n = 0, 1 m = 0 to 3 User's Manual U16031EJ4V1UD 527 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Example of continuous transmission processing flow in FIFO mode (CPU control) Figure 10-15. Example of Continuous Transmission Processing Flow in FIFO Mode (CPU Control) START Set UARTB-related registers Write transmit FIFOnNote 1 : Write transmit data UBnTXE = 1 (UBnCTL0) : Enable transmission UBTIFn interrupt = 1? Yes No : Transmission completed?Note 2 No UBTITn interrupt = 1? Yes Transmission completed? Yes : Writing to transmit FIFOn enabled? No : Writing all transmit data completed? Write transmit FIFOnNote 3 UBTIFn interrupt = 1? Yes No : Transmission completed? UBnTXE = 0 (UBnCTL0) : Disable transmission Clear transmit FIFOn END Notes 1. 2. Write more transmit data than the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register to transmit FIFOn. This is the case where transmission is completed (transmit FIFOn and transmit shift register n become empty) before the next transmit data is written. To continue data transmission, clear the UBTIFn and UBTITn interrupts and write the next data to transmit FIFOn. 3. In the pending mode (UBnITM bit of the UBnFIC0 register = 0), write as many transmit data as the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register to transmit FIFOn. In the pointer mode (UBnITM bit = 1), reference the UBnTB4 to UBnTB0 bits of the UBnFIS1 register and write as many data as the number of vacant bytes in transmit FIFOn to transmit FIFOn. Write 16-byte data to fully use the 8-bit x 16-stage FIFO function. Remark n = 0, 1 528 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Example of continuous reception processing in FIFO mode (CPU control) Figure 10-16. Example of Continuous Reception Processing in FIFO Mode (CPU Control) START Set UARTB-related registers UBnRXE = 1 (UBnCTL0) : Enable reception UBTIREn interrupt = 1? No UBTITOn interrupt = 1? Yes Yes Error processing in FIFO mode No : Reception error occurred? : Reception timeout occurred? No UBTIRn interrupt = 1? Yes Read receive FIFOnNote 1 : Reading from receive FIFOn enabled? : Read receive data Reception completed? Yes UBnRXE= 0 (UBnCTL0) No : Reading all receive data completed? : Disable reception Check UBnFIS0 register Read receive FIFOnNote 2 : Read receive data remaining in receive FIFOn Clear receive FIFOn END Notes 1. Read as many receive data as the number set as the trigger by the UBnRT3 to UBnRT0 bits of the UBnFIC2 register from receive FIFOn in the pending mode (UBnITM bit of the UBnFIC0 register = 0). In the pointer mode (UBnITM bit = 1), reference the UBnRB4 to UBnRB0 bits of the UBnFIS0 register and read as many data as the number of bytes stored in receive FIFOn from receive FIFOn. 2. Read as many data (remaining receive data less than the number set as the trigger) as the number of bytes stored in receive FIFOn from receive FIFOn by referencing the UBnRB4 to UBnRB0 bits of the UBnFIS0 register. Remark n = 0, 1 User's Manual U16031EJ4V1UD 529 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Example of continuous transmission (pending mode) processing in FIFO mode (DMA control) Figure 10-17. Example of Continuous Transmission (Pending Mode) Processing in FIFO Mode (DMA Control) START Set UARTB/DMAC-related registersNote 1 Write transmit FIFOnNote 2 : Write transmit data DTFRm register = 3CH : Assign DMA transfer destination (in the case of UBTIT0) : Clear DFm bit DTFRm register = 3CH Emm = 1 (DCHCm) : Enable DMA transfer UBnTXE = 1 (UBnCTL0) : Enable transmission DMA completed? Yes No : DMA transfer completed? UBTIFn interrupt = 1? Yes UBnTXE = 0 (UBnCTL0) No : Transmission completed? : Disable transmission Clear transmit FIFOn END Notes 1. In this control flow example, transmission of the data described in Note 2 is executed by a CPU write operation. Exercise care in setting the number of data for DMA transfer (DBCm register) and the source address (DSAmH and DSAmL registers). 2. Write as many transmit data as the number set as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register (= 1 byte) to transmit FIFOn. Remark n = 0, 1, m = 0 to 3 530 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Example of continuous reception (pending mode) processing flow in FIFO mode (DMA control) Figure 10-18. Example of Continuous Reception (Pending Mode) Processing Flow in FIFO Mode (DMA Control) START Set UARTB/DMAC-related registers DTFRm register = 3BH : Assign DMA transfer destination (in the case of UBTIR0) : Clear DFm bit DTFRm register = 3BH Emm = 1 (DCHCm) : Enable DMA transfer UBnRXE = 1 (UBnCTL0) : Enable reception DMA completed? Yes UBnRXE = 0 (UBnCTL0) No : DMA transfer (reception) completed? : Disable reception Clear receive FIFOn END Remark n = 0, 1 m = 0 to 3 User's Manual U16031EJ4V1UD 531 CHAPTER 10 SERIAL INTERFACE FUNCTION (9) Example of reception error processing in single mode Figure 10-19. Example of Reception Error Processing in Single Mode START Read UBnSTR register : Check error flag Clear error flag Read UBnRX register : Extract receive data (error data) END Caution Reception can be continued by completing this control flow before reception of the next data is completed. If the next data is received before this control flow is completed, a reception error interrupt (UBTIREn) may occur even if the data has been received correctly. Remark n = 0, 1 532 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (10) Example of reception error processing flow in FIFO mode (1) Figure 10-20. Example of Reception Error Processing Flow in FIFO Mode (1) START Read UBnSTR register : Check error flag Clear error flag UBnRXE = 0 (UBnCTL0)Note : Stop reception Read UBnFIS0 register : Check receive FIFOn pointer Read UBnRXAP register : Extract receive data and check error UBnRFC = 1 (UBnFIC0) : Clear receive FIFOn END Note If the error flag is cleared when UBnRXE bit = 0, the UBnCTL0 register does not have to be set. Remark n = 0, 1 User's Manual U16031EJ4V1UD 533 CHAPTER 10 SERIAL INTERFACE FUNCTION (11) Example of reception error processing flow in FIFO mode (2) Figure 10-21. Example of Reception Error Processing Flow in FIFO Mode (2) START Read UBnSTR register : Check error flag Clear error flag Read UBnFIS0 register : Check receive FIFOn pointer Read UBnRXAP register : Extract receive data and check error END Note Reception can be continued by completing this control flow before reception of the next data is completed. Extract the receive data and check if a reception error has occurred before receive FIFOn becomes empty. Note that this control flow is valid only when a parity error or a framing error occurs. If an overflow error occurs, receive FIFOn must be cleared (UBnRFC bit of the UBnFIC0 register = 1). If the next data is received before this control flow is completed, a reception error interrupt (UBTIREn) may occur even if the data has been received correctly. Remark n = 0, 1 534 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.9 Cautions Cautions concerning UARTB are shown below. (1) When supply clock to UARTBn is stopped When the supply of clocks to UARTBn is stopped (for example, IDLE or STOP mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. The TXDn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of clocks is restarted, the circuits should be initialized by setting UBnPWR = 0, UBnRXE = 0, and UBnTXE = 0. (2) Caution on setting UBnCTL0 register * When using UARTBn, set the external pins related to the UARTBn function to the control mode and set the UBnCTL2 register. Then set the UBnPWR bit of the UBnCTL0 register to 1 before setting the other bits. * Be sure to input a high level to the RXDn pin when setting the external pins related to the UARTBn function to the control mode. If a low level is input, it is judged that a falling edge is input after the UBnRXE bit of the UBnCTL0 register has been set to 1, and reception may be started. (3) Caution on setting UBnFIC2 register Be sure to clear the UBnTXE bit (to disable transmission) and UBnRXE bit (to disable reception) of the UBnCTL0 register to 0 before writing data to the UBnFIC2 register. If data is written to the UBnFIC2 register with the UBnTXE or UBnRXE bit set to 1, the operation is not guaranteed. (4) Transmission interrupt request signal In the single mode, the transmission completion interrupt (UBTITn) occurs when the UBnTX register becomes empty (when 1 byte of data is transferred from the UBnTX register to transmit shift register n). In the FIFO mode, the FIFO transmission completion interrupt (UBTIFn) occurs when data is no longer in transmit FIFOn and transmit shift register n (when the FIFO and register are vacant). However, the UBTITn interrupt or UBTIFn interrupt does not occur if transmit data register n becomes empty due to RESET input. (5) Initialization during continuous transmission in single mode Confirm that the UBnTSF bit of the UBnSTR register is 0 before executing initialization during transmission processing. If initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed. (6) Initialization during continuous transmission (pending mode) in FIFO mode Confirm that the UBnTSF bit of the UBnSTR register is 0 before executing initialization during transmission processing (this can also be done by checking the FIFO transmission completion interrupt (UBTIFn)). If initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed. To write transmit data to transmit FIFOn by DMA control, set the number of transmit data specified as the trigger by the UBnTT3 to UBnTT0 bits of the UBnFIC2 register to 1 byte; otherwise the operation will not be guaranteed. (7) Initialization during continuous transmission (pointer mode) in FIFO mode Confirm that the UBnTSF bit of the UBnSTR register is 0 before executing initialization during transmission processing (this can also be done by checking the FIFO transmission completion interrupt (UBTIFn)). If initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed. User's Manual U16031EJ4V1UD 535 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Receive operation in FIFO mode (pointer mode specified) If the pointer mode is specified in the FIFO mode and if as many data as the number of bytes stored in receive FIFOn are read by referencing the UBnFIS0 register, no data may be stored in receive FIFOn (UBnRB4 to UBnRB0 bits = 00000 in the UBnFIS0 register) even though the reception completion interrupt (UBTIRn) has occurred. In this case, do not read data from receive FIFOn. Be sure to read data from receive FIFOn after confirming that the number of bytes stored in receive FIFOn = 1 byte or more (UBnRB4 to UBnRB0 bits = other than 00000). 536 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 Clocked Serial Interfaces 30, 31 (CSI30, CSI31) 10.3.1 Features * Transfer rate: Master mode/slave mode: Maximum 5.5 Mbps * Half-duplex communications * Master mode and slave mode can be selected * Transmission data length: 8 to 16 bits (selectable in 1-bit units) * Transfer data direction can be switched between MSB first and LSB first * 3-wire mode SOn: SIn: SCKn: * Bit rate In master mode: BRG output (selected by the CKS3n2 to CKS3n0 bits and MDLn2 to MDLn0 bits of clocked serial interface clock select register n (CSIC3n)) In slave mode: Clock input from master (when CKS3n2 to CKS3n0 bits = 111 in the CSIC3n register) * Interrupt sources: 2 types * Transmission/reception completion interrupt (INTCSI3n) * CSIBUFn overflow interrupt (INTCOVF3n) * Transmission mode, reception mode, or transmission/reception mode can be selected * Transmission mode: Transmission is started by writing transmit data to transmit data CSI buffer register 3n (SFDB3n) while transmission is enabled (see 10.3.5 (11) Transmission mode). * Reception mode: Reception is started by using processing that writes dummy data to transmit data CSI buffer register 3n (SFDB3n) as a trigger while reception is enabled (see 10.3.5 (12) Reception mode). * Transmission/reception mode: Transmission/reception is started by using processing that writes transmit data to transmit data CSI buffer register 3n (SFDB3n) while transmission/reception is enabled (see 10.3.5 (13) Transmission/reception mode). * Sixteen on-chip 16-bit transmit/receive buffers (CSIBUFn) * On-chip dedicated baud rate generator Remark n = 0, 1 Serial data output Serial data input Serial clock I/O User's Manual U16031EJ4V1UD 537 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 Configuration CSI3n is controlled by the clocked serial interface mode register 3n (CSIM3n) (n = 0, 1). (1) Clocked serial interface mode registers 30, 31 (CSIM30, CSIM31) The CSIM3n register is an 8-bit register for specifying the operation of CSI3n. (2) Clocked serial interface clock select registers 30, 31 (CSIC30, CSIC31) The CSIC3n register is an 8-bit register for controlling the operation clock and operating mode of CSI3n. (3) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is an 8-bit register for converting between serial data and parallel data. SIOn is used for both transmission and reception. Data is shifted in (reception) or shifted out (transmission) beginning at either the MSB side or the LSB side. (4) Receive data buffer registers 30, 31 (SIRB30, SIRB31) The SIRB3n register is a 16-bit buffer register that stores receive data. This register is also divided into two registers: the higher 8 bits (SIRB3nH) and lower 8 bits (SIRB3nL). (5) Transmit data CSI buffer registers 30, 31 (SFDB30, SFDB31) The SFDB3n register is a 16-bit buffer register that stores transmit data. This register is also divided into two registers: the higher 8 bits (SFDB3nH) and lower 8 bits (SFDB3nL). (6) CSIBUF status registers 30, 31 (SFA30, SFA31) The SFA3n register is an 8-bit register that indicates the status of CSI data buffer register n (CSIBUFn) or the transfer status. (7) Transfer data length select registers 30, 31 (CSIL30, CSIL31) The CSIL3n register is an 8-bit register that selects the CSI3n transfer data length. (8) Transfer data number specification registers 30, 31 (SFN30, SFN31) The SFN3n register is an 8-bit register that sets the number of CSI3n transfer data in continuous mode. (9) CSI data buffer registers 0, 1 (CSIBUF0, CSIBUF1) By consecutively writing transmit data to the SFDB3n register from where it is transferred, the data can be stored in the CSIBUFn register while the CSIBUFn pointer for writing is automatically incremented (CSIBUFn). The CSIBUFn is a 16-bit buffer register. In the continuous mode, the data received in the CSIBUFn register can be sequentially read while the read CSIBUFn pointer is automatically incremented, by continuously reading the receive data from the SIRB3n register. 538 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Block Diagram of Clocked Serial Interfaces 30 and 31 Internal bus CSIBUF status register 3n (SFA3n) Transfer data control Transmit data CSI buffer register 3n (SFDB3n) INTCOVF3n 15 0 CSI data buffer register n (CSIBUFn) SIn SCKn Selector fX/4 Prescaler output fXCLK BRGn Shift register n (SIOn) Note 1 Note 2 SOn SCKn INTCSI3n Receive data buffer register 3n (SIRB3n) Transfer control MDLn2 MDLn1 MDLn0 CKS3n2 CKS3n1 CKS3n0 Clocked serial interface clock select register 3n (CSIC3n) Internal bus Notes 1. 2. In single mode In continuous mode Remarks 1. n = 0, 1 2. fX: Main clock fXCLK: Base clock selected by CKS3n2 to CKS3n0 bits of CSIC3n register User's Manual U16031EJ4V1UD 539 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 Control registers Because CSI30 shares pins with UARTB0, the CSI30 mode must be set in advance by using the PMC1 and PFC1 registers (see 10.1.1 Switching between UARTB0 and CSI30 modes). (1) Clocked serial interface mode registers 30, 31 (CSIM30, CSIM31) The CSIM3n register controls the operation of CSI3n (n = 0, 1). These registers can be read or written in 8-bit or 1-bit units. Be sure to clear bit 0 to 0. If it is set to 1, the operation is not guaranteed. Cautions 1. Writing the TRMDn, DIRn, CSITn, and CSWEn bits is enabled only when CTXEn bit = 0 and CRXEn bit = 0. 2 Be sure to set the external pins related to the CSI3n function to control the mode before using CSI3n. Then set the CSICAEn bit to 1 before setting the other bits. (1/2) 7 CSIM30 CSICAE0 6 CTXE0 5 CRXE0 4 TRMD0 3 DIR0 2 CSIT0 1 CSWE0 0 0 Address FFFFFD00H After reset 00H CSIM31 CSICAE1 CTXE1 CRXE1 TRMD1 DIR1 CSIT1 CSWE1 0 FFFFFD20H 00H Bit position 7 Bit name CSICAEn Controls the operating clock. 0: Stop clock supply to CSI3n. 1: Supply clock to CSI3n. Function Cautions 1. The CSI3n unit is reset when the CSICAEn bit = 0, and CSI3n is stopped. To operate CSI3n, first set the CSICAEn bit to 1. 2. When rewriting the CSICAEn bit from 0 to 1 or from 1 to 0, simultaneously rewriting the bits other than the CSICAEn bit of the CSIM3n register is prohibited. When the CSICAEn bit = 0, rewriting the bits other than the CSICAEn bit of the CSIM3n register, and the SFDB3n, SFDB3nL, and SFA3n registers is prohibited. 6 CTXEn Enables or disables transmission. 1: Disables transmission. 0: Enables transmission. Caution The CTXEn bit is reset when the CSICAEn bit is cleared to 0. Remark n = 0, 1 540 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2/2) Bit position 5 Bit name CRXEn Enables or disables reception. 1: Disables reception. 0: Enables reception. Caution The CRXEn bit is reset when the CSICAEn bit is cleared to 0. 4 TRMDn Specifies the transfer mode. 0: Single mode 1: Continuous mode 3 DIRn Specifies the transfer direction when data is written from the SFDB3n register to the CSIBUFn register or read from the SIRB3n and CSIBUFn registers. 0: The first bit of transfer data is the MSB. 1: The first bit of transfer data is the LSB. 2 CSITn Controls delay of the transmission completion interrupt signal (INTCSI3n) (see 10.3.5 (14) Delay control of transmission/reception completion interrupt (INTCSI3n)). 0: No delay 1: Delay mode (In the continuous mode (TRMDn = 1), the next data transfer is delayed half a cycle because a delay of half a cycle is inserted when transfer of 1bit data is complete.) Cautions 1. The delay mode (CSIT bit = 1) is valid only in the master mode (when the CKS3n2 to CKS3n0 bits of the CSIC3n register are other than 111). In the slave mode (when the CKS3n2 to CKS3n0 bits are 111), do not set the delay mode. Even if the delay mode is set, INTCSI3n is not affected by the CSITn bit. 2. If the CSITn bit is set to 1 in the continuous mode (TRMDn bit = 1), the INTCSI3n interrupt is not output except when the last data set by the SFNn3 to SFNn0 bits of the SFN3n register is transferred, but a delay of half a clock can be inserted between each data transfer. 1 CSWEn Enables or disables transfer wait. 0: Disables transfer wait (1 wait cycle not inserted on starting transfer). 1: Enables transfer wait (1 wait cycle inserted on starting transfer). Caution Inserting a transfer wait cycle (CSWEn bit = 1) is valid only in the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register). In the slave mode (CKS3n2 to CKS3n0 bits = 111), do not insert a transfer wait cycle. Even if set, a transfer wait cycle is not inserted. Function Remark n = 0, 1 User's Manual U16031EJ4V1UD 541 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock select registers 30, 31 (CSIC30, CSIC31) The CSIC3n register is an 8-bit register that controls the operation clock and operating mode of CSI3n. These registers can be read or written in 8-bit or 1-bit units. Caution Data can be written to the CSIC3n register only when the CTXEn bit = 0 and CRXEn bit = 0 in the CSIM3n register. (1/3) 7 CSIC30 MDL02 6 MDL01 5 MDL00 4 CKP0 3 DAP0 2 CKS302 1 CKS301 0 CKS300 Address FFFFFD01H After reset 07H CSIC31 MDL12 MDL11 MDL10 CKP1 DAP1 CKS312 CKS311 CKS310 FFFFFD21H 07H Bit position 7 to 5 Bit name MDLn2 to MDLn0 Function Specify the transfer clock (BRGn output signal). MDLn2 MDLn1 MDLn0 Set value (N) - 1 2 3 4 5 6 7 Transfer clock (BRGn output signal) BRGn stop mode (power save) fXCLK/2 fXCLK/4 fXCLK/6 fXCLK/8 fXCLK/10 fXCLK/12 fXCLK/14 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Caution In the slave mode (CKS3n2 to CKS3n0 bits = 111), it is recommended to clear the MDLn2 to MDLn0 bits to 000 (BRGn stop mode). Remark fXCLK: Base clock selected by CKS3n2 to CKS3n0 bits Remark n = 0, 1 542 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Bit position Bit name Function Specify the data transmission/reception timing for SCKn. CKPn 0 DAPn 0 SCKn (I/O) SOn (output) SIn capture D7 D6 D5 D4 D3 D2 D1 D0 4, 3 CKPn, DAPn Operation mode 0 1 SCKn (I/O) SOn (output) SIn capture D7 D6 D5 D4 D3 D2 D1 D0 1 Note 0 SCKn (I/O) SOn (output) SIn capture D7 D6 D5 D4 D3 D2 D1 D0 1 Note 1 SCKn (I/O) SOn (output) SIn capture D7 D6 D5 D4 D3 D2 D1 D0 Note If the CKPn bit is set to 1 in the master mode (CKS3n2 to CKS3n0 bits are other than 111), the SCKn pin outputs a low level when it is inactive. If the CTXEn bit of the CSIM3n register is cleared to 0 (disabling transmission) and CRXEn bit is cleared to 0 (disabling reception), the SCKn pin outputs a high level. Therefore, take the following measures to fix the SCKn pin to low level when CSI3n is not used. [SCK0 pin (SCK1 pin)] <1> Clearing the P11 bit of the P1 register to 0 (clearing the P23 bit of the P2 register to 0): The port output level is set to low. <2> Clearing the PM11 bit of the PM1 register to 0 (clearing the PM23 bit of the PM2 register to 0): The port is set in the output mode. <3> Clearing the PMC11 bit of the PMC1 register to 0 (clearing the PMC23 bit of the PMC2 register to 0): The pin is set in the port mode (fixed to low-level output). <4> Clearing the CTXE0 and CRXE0 bits of the CSIM30 register to 0 (clearing the CTXE1 and CRXE1 bits of the CSIM31 register to 0): Transmission and reception are disabled. <5> Setting the CTXE0 or CRXE0 bit of the CSIM30 register to 1 (setting the CTXE1 or CRXE1 bit of the CSIM31 register to 1): Transmission or reception is enabled (both transmission and reception can also be enabled). <6> Setting the PMC11 bit of the PMC1 register to 1 (setting the PMC23 bit of the PMC2 register to 1): The pin is set in the control mode (SCK0 and SCK1 pin output). Because the register set values <1> and <2> are retained, control can be performed only by <3> to <6> once they have been set. Remark n = 0, 1 User's Manual U16031EJ4V1UD 543 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) Bit position 2 to 0 Bit name CKS3n2 to CSK3n0 Function Specify the base clock (prescaler output). CKS3n2 CKS3n1 CKS3n0 Set value (k) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 fX/4 fX/8 fX/16 fX/32 fX/64 fX/128 fX/256 External clock (SCKn) Caution If the CKS3n2 to CKS3n0 bits of the CSIC3n register are cleared to 000, setting the MDLn2 to MDLn0 bits of the CSIC3n register to 001 is prohibited. Remark fX: Main clock Base clock (fXCLK) Master mode Master mode Master mode Master mode Master mode Master mode Master mode Slave mode Mode Remark n = 0, 1 544 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Receive data buffer registers 30, 31 (SIRB30, SIRB31) The SIRB3n register is a 16-bit buffer register that stores receive data. By consecutively reading this register in the continuous mode (TRMDn bit = 1 in the CSIM3n register), the received data in the CSIBUFn register can be sequentially read while the CSIBUFn pointer for reading is incremented. In the single mode (TRMDn bit = 0 in the CSIM3n register), received data is read by reading the SIRB3n register and it is judged that the SIRB3n register has become empty. The SIRB3n register is read-only, in 16-bit units. When the higher 8 bits of the SIRB3n register are used as the SIRB3nH register and the lower 8 bits as the SIRB3nL register, these registers are read-only, in 8-bit units. When reading in 8-bit units, be sure to read the SIRB3nH register and SIRB3nL register in that order. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFD02H After resetNote 0000H SIRB30 SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB 015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 00 SIRB31 SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB 115 114 113 112 111 110 19 18 17 16 15 14 13 12 11 10 FFFFFD22H 0000H Note In continuous mode (TRMDn bit = 1 in the CSIM3n register): Undefined Bit position 15 to 0 Bit name SIRBn15 to SIRBn0 Store receive data. Function Remarks 1. n = 0, 1 2. The SIRB3n register is cleared to 0000H when the CSICAEn bit of the CSIM3n register is cleared to 0. User's Manual U16031EJ4V1UD 545 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Transmit data CSI buffer registers 30, 31 (SFDB30, SFDB31) The SFDB3n register is a 16-bit buffer register that stores transmit data. When transmit data is written to this register, the data is sequentially stored in the CSIBUFn register while the CSIBUFn pointer for writing is incremented. When the data of this register is read, the value of the transmit data written last is read. The SFDB3n register can be read or written in 16-bit units. When the higher 8 bits of the SFDB3n register are used as the SFDB3nH register, and the lower 8 bits as the SFDB3nL register, these registers can be read or written in 8-bit units. When reading in 8-bit units, be sure to read the SFDB3nH register and SFDB3nL register in that order. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFD06H After reset 0000H SFDB30 SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB 015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 00 SFDB31 SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB SFDB 115 114 113 112 111 110 19 18 17 16 15 14 13 12 11 10 FFFFFD26H 0000H Bit position 15 to 0 Bit name SFDBn15 to SFDBn0 Store transmit data. Function Remark n = 0, 1 546 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) CSIBUF status registers 30, 31 (SFA30, SFA31) These registers indicate the status of the CSIBUFn register or the transfer status. These registers can be read or written in 8-bit or 1-bit units (however, bits 6 to 0 can only be read. They do not change even if they are written). Cautions 1. Reading the SFA3n register is prohibited when the CSICAEn bit of the CSIM3n register is 1 and when the main clock (fX) is stopped. 2. Because the values of the SFFULn, SFEMPn, CSOTn, and SFPn3 to SFPn0 bits may change at any time during transfer, their values during transfer may differ from the actual values. Especially, use the CSOTn bit independently (do not use this bit in relation with the other bits). To detect the end of transfer by the SFA3n register, check to see if the SFEMPn bit is 1 after the data to be transferred has been written to the CSIBUFn register. 3. If the SFA3n register is read immediately after data has been written to the SFDB3n and SFDB3nL registers when the main clock (fX) is 84 MHz or lower, the values of the SFFULn, SFEMPn, and SFPn3 to SFPn0 bits do not change in time. 4. If the SFA3n register is read before the SFFULn bit is set to 1 and the 17th data is written, the CSIBUFn overflow interrupt (INTCOVF3n) is generated. (1/3) 7 SFA30 FPCLR0 6 5 4 CSOT0 3 SFP03 2 SFP02 1 SFP01 0 SFP00 Address FFFFFD08H After reset 20H SFFUL0 SFEMP0 SFA31 FPCLR1 SFFUL1 SFEMP1 CSOT1 SFP13 SFP12 SFP11 SFP10 FFFFFD28H 20H Bit position 7 Bit name FPCLRn Function Specifies clearing of the CSIBUFn pointer. 0: No operation 1: Clear all CSIBUFn pointers to 0. Cautions 1. This bit is always 0 when it is read. 2. If 1 is written to the FPCLRn bit in the middle of transfer, transfer is aborted. Because all the CSIBUFn pointers are cleared to 0, the remaining data in the CSIBUFn register is ignored. If 1 is written to the FPCLRn bit, be sure to read the SFA3n register to check to see if all the CSIBUFn pointers have been correctly cleared to 0 (SFFULn bit = 0, SFEMPn bit = 1, SFPn3 to SFPn0 bits = 0000). Nothing happens even if 0 is written to the FPCLRn bit. Remarks 1. n = 0, 1 2. The SFA3n register is set to 20H when the CSICAEn bit of the CSIM3n register is cleared to 0. User's Manual U16031EJ4V1UD 547 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Bit position 6 Bit name SFFULn Function This flag indicates the full status of the CSIBUFn register. 0: CSIBUFn register has a vacancy. 1: CSIBUFn register is full. Cautions 1. This bit is cleared to 0 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLR bit is set to 1. 2. If transfer of 16 data is specified in the continuous mode (TRMDn bit = 1 in the CSIM3n register) (SFNn3 to SFNn0 bits = 0000 in the SFN3n register), the SFFULn bit is set to 1 in the same way as in the single mode (TRMDn bit = 0 in the CSIM3n register) when 16 data are in the CSIBUFn register. If even one of the data has been completely transferred, the SFFULn bit is cleared to 0. However, this does not mean that the CSIBUFn register has a vacancy. 5 SFEMPn This flag indicates the empty status of the CSIBUFn register. 0: Data is in CSIBUFn register. 1: CSIBUFn register is empty. Cautions 1. This flag is set to 1 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLR bit is set to 1. 2. If the data written to the CSIBUFn register has been transferred, the SFEMPn bit is set to 1 (even if receive data is stored in the CSIBUFn register). 4 CSOTn This flag indicates transfer status. 0: Idle status 1: Transfer or transfer start processing in progress Cautions 1. This flag is cleared to 0 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLRn bit is set to 1, or when the CTXEn and CRXEn bits of the CSIM3n register are cleared to 0. 2. This flag is "1" from when transfer is started until there is no more transfer data in the CSIBUFn register in the single mode (TRMDn bit = 0 in the CSIM3n register) or until the specified number of data has been transferred in the continuous mode (TRMDn bit = 1 in the CSIM3n register). Remark n = 0, 1 548 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) Bit position 3 to 0 Bit name SFPn3 to SFPn0 Function * In the single mode (TRMDn bit = 0 in the CSIM3n register), the "number of transfer data remaining in CSIBUFn register (CSIBUFn pointer value for writing - CSIBUFn pointer value for SIOn loading)" can be read. * In the continuous mode (TRMDn bit = 1 in the CSIM3n register), the "number of data completely transferred (value of CSIBUFn pointer for SIOn loading/storing)" can be read. If the SFPn3 to SFPn0 bits are 0H, however, the number of transferred data is as follows, depending on the setting of the SFEMPn bit. When SFEMPn bit = 0: Number of transferred data = 0 When SFEMPn bit = 1: Number of transferred data = 16 or status before starting transfer (before writing transfer data) Caution These bits are cleared to 0 in synchronization with the operating clock when the FPCLRn bit = 1. However, the values of these bits are held until the CSICAEn bit of the CSIM3n register is cleared to 0 or the FPCLRn bit is set to 1. Remark n = 0, 1 User's Manual U16031EJ4V1UD 549 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Transfer data length select registers 30, 31 (CSIL30, CSIL31) The CSIL3n register is used to select the transfer data length of CSI3n. These registers can be read or written in 8-bit or 1-bit units. Be sure to clear bits 7 to 4 to 0. If they are set to 1, the operation is not guaranteed. Caution The CSIL3n register may be transferring data when the CTXEn or CRXEn bit of the CSIM3n register is 1. Be sure to clear the CTXEn and CRXEn bits to 0 before writing data to the CSIL3n register. 7 CSIL30 0 6 0 5 0 4 0 3 CCL03 2 CCL02 1 CCL01 0 CCL00 Address FFFFFD09H After reset 00H CSIL31 0 0 0 0 CCL13 CCL12 CCL11 CCL10 FFFFFD29H 00H Bit position 3 to 0 Bit name CCLn3 to CCLn0 Specifies a transfer data length. CCLn3 0 1 1 1 1 1 1 1 1 CCLn2 0 0 0 0 0 1 1 1 1 CCLn1 0 0 0 1 1 0 0 1 1 Function CCLn0 0 0 1 0 1 0 1 0 1 16 bits 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits Transfer data length Other than above Setting prohibited Caution If a transfer data length other than 16 bits is specified (CCLn3 to CCLn0 bits = 0000), an undefined value is read to the higher excess bits of the SIRB3n and CSIBUFn registers (see 10.3.5 (3) Data transfer direction specification function). Remark n = 0, 1 550 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Transfer data number specification registers 30, 31 (SFN30, SFN31) The SFN3n register is used to set the number of transfer data of CSI3n in the continuous mode (TRMDn bit = 1 in the CSIM3n register). These registers can be read or written in 8-bit or 1-bit units. 7 SFN30 - - 6 - - 5 - - 4 - - 3 SFN03 2 SFN02 1 SFN01 0 SFN00 Address FFFFFD0CH After reset 00H SFN31 SFN13 SFN12 SFN11 SFN10 FFFFFD2CH 00H Bit position 3 to 0 Bit name SFNn3 to SFNn0 Specify the number of transfer data. SFNn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SFNn2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SFNn1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Function SFNn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Number of transfer data Caution Writing data exceeding the value set by the SFNn3 to SFNn0 bits (number of CSI3n transfer data) to the CSIBUFn register is prohibited (data is ignored even if written). Remark n = 0, 1 User's Manual U16031EJ4V1UD 551 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 Dedicated baud rate generators 0, 1 (BRG0, BRG1) The transfer clock of CSI3n can be selected from the output of a dedicated baud rate generator or external clock (n = 0, 1). The serial clock source is specified by the CSIC3n register. In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), BRGn is selected as the clock source. (1) Transfer clock Figure 10-23. Transfer Clock of CSI3n SCKn Selector Prescaler BRGn fXCLK (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14) Transfer clock fX/4 MDLn2 MDLn1 MDLn0 CKS3n2 CKS3n1 CKS3n0 Clocked serial interface clock select register 3n (CSIC3n) Remarks 1. n = 0, 1 2. fX: Main clock fXCLK: Base clock selected by CKS3n2 to CKS3n0 bits of CSIC3n register 552 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Baud rate The baud rate is calculated by the following expression. Baud rate = F N x 2(K + 1) [bps] F = fX/4 (fX: main clock) K = Value set by CKS3n2 to CKS3n0 bits of CSIC3n register (K = 0, 1, 2, ..., 6) N = Value set by MDLn2 to MDLn0 bits of CSIC3n register (N = 1, 2, 3, ..., 7) Cautions 1. If the CKS3n2 to CKS3n0 bits of the CSIC3n register are cleared to 000, setting the MDLn2 to MDLn0 bits of the CSIC3n register to 001 is prohibited. 2. Because the maximum transfer rate in the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register) is 5.5 Mbps, do not exceed this value. Example: When CSI3n operates at 133 MHz, the maximum transfer rate is set when the CKS3n2 to CKS3n0 bits = 000 and the MDLn2 to MDLn0 bits = 011, and at 150 MHz, when the CKS3n2 to CKS3n0 bits = 000 and MDLn2 to MDLn0 bits = 100, in the CSIC3n register. User's Manual U16031EJ4V1UD 553 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 Operation (1) Operation modes Table 10-6. Operation Modes TRMDn Bit CKS3n2 to CKS3n0 Bits Master mode CTXEn and CRXEn Bits DIRn Bit CSITn Bit CSWEn Bit Single mode Transmission/reception/ transmission and reception MSB/LSB first Enables/disables INTCSI3n delay mode - Enables/disables INTCSI3n delay mode Disables transfer wait Enables transfer wait - Disables transfer wait Enables transfer wait - Slave mode Consecutive mode Slave mode Master mode - Remarks 1. CTXEn bit: Bit 6 of CSIM3n register CRXEn bit: Bit 5 of CSIM3n register TRMDn bit: Bit 4 of CSIM3n register DIRn bit: CSITn bit: Bit 3 of CSIM3n register Bit 2 of CSIM3n register CSWEn bit: Bit 1 of CSIM3n register CKS3n2 to CKS3n0 bits: Bits 2 to 0 of CSIC3n register 2. n = 0, 1 (2) Function of CSI data buffer registers 0, 1 (CSIBUF0, CSIBUF1) By consecutively writing the transmit data to the SFDB3n register from where it is transferred, the data can be stored in the CSIBUFn register while the CSIBUFn pointer for writing is automatically incremented (the CSIBUFn register size is 16 bits x 16) (n = 0, 1). The condition under which transfer is to be started (SFEMPn bit = 0 in the SFA3n register) is satisfied when data is written to the lower 8 bits (SFDB3nL register) of the SFDB3n register. If a transfer data length of 9 bits or more is specified (CCLn3 to CCLn0 bits = 0000 or 1001 to 1111 in the CSIL3n register), data must be written to the SFDB3n register in 16-bit units or to the SFDB3nH and SFDB3nL registers, in that order, in 8-bit units. If the transfer data length is set to 8 bits (CCLn3 to CCLn0 bits = 1000 in the CSIL3n register), data must be written to the SFDB3nL register in 8-bit units or to the SFDB3n register in 16-bit units. (If data is written to the SFDB3nL register in 16-bit units, however, the higher 8 bits of the data (of the SFDB3nH register) are ignored and not transferred). The SFFULn bit of the SFA3n register is set to 1 when 16 data exist in the CSIBUFn register and outputs a CSIBUFn overflow interrupt (INTCOVF3n) when the SFFULn bit = 1 and when the 17th transfer data is written (17th transfer data is not written and ignored). Sixteen data exist in the CSIBUFn register in the single mode (TRMDn bit = 0 in the CSIM3n register) when "CSIBUFn pointer value for writing = CSIBUFn pointer value for SIOn loading, and SFFULn bit = 1 in the SFA3n register". When the CSIBUFn pointer for SIOn loading is incremented after completion of transfer, the CSIBUFn register has a vacancy of one data (in the continuous mode (TRMDn bit = 1 in the CSIM3n register), the CSIBUFn register does not have a vacancy even if one data has been transferred). 554 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-24. Function of CSI Data Buffer Register n (CSIBUFn) 15 15 0 Transfer data 4 Transfer data 3 Transfer data 2 Transfer data 1 0 Transfer data 0 SIOn load CSIBUFn pointer Write CSIBUFn pointer Incremented Incremented CSI data buffer register n (CSIBUFn) 15 SFDB3nH 87 SFDB3nL 0 7 43 0 SFPn3 to SFPn0 CSIBUF status register 3n (SFA3n) Transmit data CSI buffer register 3n (SFDB3n) Remark n = 0, 1 User's Manual U16031EJ4V1UD 555 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Data transfer direction specification function The data transfer direction can be changed by using the DIRn bit of the CSIM3n register (n = 0, 1). (a) MSB first (DIRn bit = 0) Figure 10-25. Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register), Transfer Direction: MSB First (DIRn Bit = 0 in CSIM3n Register) (1/2) (i) Transfer direction: MSB first SCKn (I/O) SIn (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 (ii) Writing from SFDB3n register to CSIBUFn register 15 SFDB3n 87 0 CSIBUFn Data 00H SOn SIOn SIn Remark n = 0, 1 556 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-25. Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register), Transfer Direction: MSB First (DIRn Bit = 0 in CSIM3n Register) (2/2) (iii) Reading from SIRB3n register (in single mode (TRMDn bit of CSIM3n register = 0)) 15 SIRB3n (read value) Undefined value 87 Data 0 SOn SIOn SIn (iv) Reading from SIRB3n register (in continuous mode (TRMDn bit of CSIM3n register = 1)) 15 SIRB3n (read value) Undefined value 87 Data 0 CSIBUFn SOn SIOn SIn Remark n = 0, 1 User's Manual U16031EJ4V1UD 557 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) LSB first (DIRn bit = 1) Figure 10-26. Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register), Transfer Direction: LSB First (DIRn Bit = 1 in CSIM3n Register) (1/2) (i) Transfer direction: LSB first SCKn (I/O) SIn (input) DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SOn (output) DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 (ii) Writing from SFDB3n register to CSIBUFn register 15 SFDB3n 87 0 CSIBUFn Data 00H SOn SIOn SIn Remark n = 0, 1 558 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register), Transfer Direction: LSB First (DIRn Bit = 1 in CSIM3n Register) (2/2) (iii) Reading from SIRB3n register (in single mode (TRMDn bit of CSIM3n register = 0)) 15 SIRB3n (read value) 00H 87 Data 0 SOn SIOn SIn (iv) Reading from SIRB3n register (in continuous mode (TRMDn bit of CSIM3n register = 1)) 15 SIRB3n (read value) 00H 87 Data 0 CSIBUFn SOn SIOn SIn Remark n = 0, 1 User's Manual U16031EJ4V1UD 559 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Transfer data length changing function The transfer data length can be set from 8 to 16 bits in 1-bit units, by using the CCLn3 to CCLn0 bits of the CSIL3n register (n = 1, 0). Figure 10-27. Transfer Data Length: 16 Bits (CCLn3 to CCLn0 Bits = 0000 in CSIL3n Register), Transfer Direction: MSB First (DIRn Bit = 0 in CSIM3n Register) SCKn (I/O) SIn (input) DI15 DI14 DI13 DI12 DI2 DI1 DI0 SOn (output) DO15 DO14 DO13 DO12 DO2 DO1 DO0 Remark n = 0, 1 560 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Function to select serial clock and data phase The serial clock and data phase can be changed by using the CKPn and DAPn bits of the CSIC3n register (n = 0, 1). Figure 10-28. Clock Timing (a) When CKPn bit = 0, DAPn bit = 0 SCKn SIn capture SOn INTCSI3n interrupt D7 D6 D5 D4 D3 D2 D1 D0 (b) When CKPn bit = 0, DAPn bit = 1 SCKn SIn capture SOn INTCSI3n interrupt D7 D6 D5 D4 D3 D2 D1 D0 (c) When CKPn bit = 1, DAPn bit = 0 SCKn SIn capture SOn INTCSI3n interrupt D7 D6 D5 D4 D3 D2 D1 D0 (d) When CKPn bit = 1, DAPn bit = 1 SCKn SIn capture SOn INTCSI3n interrupt D7 D6 D5 D4 D3 D2 D1 D0 Remark n = 0, 1 User's Manual U16031EJ4V1UD 561 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Master mode The master mode is set and data is transferred with the transfer clock output to the SCKn pin when the CKS3n2 to CKS3n0 bits of the CSIC3n register are set to a value other than 111 (SCKn pin input is invalid) (n = 0, 1). The default output level of the SCKn pin is high when the CKPn bit of the CSIC3n register is 0, and low when the CKPn bit is 1. Figure 10-29. Master Mode (CKPn and DAPn Bits = 00 in CSIC3n Register, CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register (Transfer Data Length: 8 Bits)) SCKn (output) SIn (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Remark n = 0, 1 562 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Slave mode The slave mode is set when the CKS3n2 to CKS3n0 bits of the CSIC3n register are set to 111, and data is transferred with the transfer clock input to the SCKn pin (in the slave mode, it is recommended to set the MDLn2 to MDLn0 bits of the CSIC3n register to 000 and set the BRGn stop mode) (n = 0, 1). Figure 10-30. Slave Mode (CKPn and DAPn Bits = 00 in CSIC3n Register, CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register (Transfer Data Length: 8 Bits)) SCKn (input) SIn (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Remark n = 0, 1 The conditions under which data can be transferred in the slave mode are listed in the table below. Table 10-7. Conditions Under Which Data Can Be Transferred in Slave Mode Transfer Mode CTXEn Bit Single mode Transmission mode Reception mode 1 CRXEn Bit 0 Data is in CSIBUFn register (SFEMPn bit = 0). Dummy data is in CSIBUFn register (SFEMPn bit = 0). Transmission/ reception mode Consecutive mode Transmission mode Reception mode 0 1 1 0 1 1 Data is in CSIBUFn register (SFEMPn bit = 0). Data is in CSIBUFn register (SFEMPn bit = 0). Dummy data is in CSIBUFn register (SFEMPn bit = 0). Transmission/ reception mode 1 1 Data is in CSIBUFn register (SFEMPn bit = 0). - - - CSIBUFn Register SIRB3n Register and SIOn Register - SIRB3n register or SIOn register is empty. 0 1 Caution Transfer is not performed normally while data transfer is not enabled, even if the transfer clock is input from the master. Remarks 1. CTXEn bit: CRXEn bit: 2. n = 0, 1 Bit 6 of CSIM3n register Bit 5 of CSIM3n register SFEMPn bit: Bit 5 of SFA3n register User's Manual U16031EJ4V1UD 563 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Transfer clock selection function In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), the bit transfer rate can be selected by setting the CKS3n2 to CKS3n0 and MDLn2 to MDLn0 bits of the CSIC3n register (see 10.3.3 (2) Clocked serial interface clock select registers 30, 31 (CSIC30, CSIC31)). (9) Single mode The single mode is set when the TRMDn bit of the CSIM3n register is 0 (n = 0, 1). In this mode, transfer is started when the CTXEn bit or CRXEn bit is set to 1 and when data is in the CSIBUFn register (SFEMPn bit = 0 in the SFA3n register). If no data is in the CSIBUFn register (SFEMPn bit = 1), transfer is kept waiting until transmit data or dummy data is written to the SFDB3n register. When data is transferred to the CSIBUFn register while transmission or reception is enabled (CTXEn or CRXEn bit is 1), the CSOTn bit of the SFA3n register (transfer status flag) is set to 1. If transfer is not in the wait status, the transfer data indicated by the SIOn load CSIBUFn pointer is loaded from the CSIBUFn register to the SIOn register, and transfer processing is started. If the SIRB3n register is empty when one data has been transferred in the reception mode or transmission/reception mode, the received data is stored from the SIOn register to the SIRB3n register, the transmission/reception completion interrupt (INTCSI3n) is output, and the SIOn load CSIBUFn pointer is incremented. If transmit data or dummy data is stored in the CSIBUFn register, the next transfer processing is started. However, storing the receive data in the SIRB3n register, outputting the INTCSI3n interrupt, and incrementing the SIOn load CSIBUFn pointer are held pending, until the previously received data is read from the SIRB3n register and the SIRB3n register becomes empty. In the transmission mode, the INTCSI3n interrupt is output and the SIOn load pointer is incremented when transfer processing of one data has been completed (the SIRB3n register is always empty because no data is stored from the SIOn register to the SIRB3n register). In all modes (transmission, reception, and transmission/reception modes), if the CSIBUFn register is empty (write CSIBUFn pointer value = SIOn load CSIBUFn pointer value) when transfer processing of one data has been completed, the CSOTn bit is cleared to 0. The value of the "number of remaining data in the CSIBUFn register (write CSIBUFn pointer - SIOn load pointer)" can always be read from the SFPn3 to SFPn0 bits of the SFA3n register. Caution Be sure to confirm that the SFFULn bit of the SFA3n register is 0 when writing data to the SFDB3n register. Even if data is written to this register when SFFULn bit is 1, the CSIBUFn overflow interrupt (INTCOVF3n) is output, and the written data is ignored. 564 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Single Mode 15 15 0 Write CSIBUFn pointer Transfer data 4 Transfer data 3 Transfer data 2 Transfer data 1 0 CSI data buffer register n (CSIBUFn) 15 SFDB3nH 87 SFDB3nL 0 7 Transfer data 0 Difference 43 0 SIOn load CSIBUFn pointer Incremented Incremented SFPn3 to SFPn0 CSIBUF status register 3n (SFA3n) Transmit data CSI buffer register 3n (SFDB3n) SOn SIOn SIn SIRB3n Remark n = 0, 1 User's Manual U16031EJ4V1UD 565 CHAPTER 10 SERIAL INTERFACE FUNCTION (10) Continuous mode The continuous mode is set when the TRMDn bit of the CSIM3n register is 1 (n = 0, 1). In this mode, transfer is started when the CTXEn bit or CRXEn bit is 1 and when data is in the CSIBUFn register (SFEMPn bit = 0 in the SFA3n register). At this time, set the number of transfer data in advance by using the SFNn3 to SFNn0 bits of the SFN3n register. data are ignored and not transferred. If no data is in the CSIBUFn register (SFEMPn bit = 1), transfer is kept waiting until transmit data or dummy data is written to the SFDB3n register. If data is transferred to the CSIBUFn register when transmission or reception is enabled (CTXEn or CRXEn bit is 1), the CSOTn bit (transfer status flag) of the SFA3n register is set to 1 and the transfer data indicated by the SIOn load/store CSIBUFn pointer is loaded from the CSIBUFn register to SIOn register. Then transfer processing is started. When transfer processing of one data is completed in the reception mode or transmission/reception mode, the received data is overwritten from the SIOn register to the transfer data in the CSIBUFn register indicated by the SIOn load/store CSIBUFn pointer, and then the pointer is incremented. By consecutively reading the transfer data from the SIRB3n register after all data in the CSIBUFn register have been transferred (when the INTCSI3n interrupt has occurred), the receive data can be sequentially read while the read CSIBUFn pointer is incremented. In the transmission mode, the SIOn load/store CSIBUFn pointer is incremented when transfer processing of one data has been completed. In all modes (transmission, reception, and transmission/reception modes), when data has been transferred by the value set by the SFNn3 to SFNn0 bits of the SFN3n register, the CSOTn bit is cleared to 0 and the transmission/reception completion interrupt (INTCSI3n) is output. To transfer the next data, be sure to write 1 to the FPCLRn bit of the SFA3n register and clear all the CSIBUFn pointers to 0. The "number of transferred data (SIOn load/store CSIBUFn pointer value)" can always be read from the SFPn3 to SFPn0 bits of the SFA3n register. Caution The SFA3n register is in the same status when transfer data is written (before start of transfer) after the CSIBUFn pointer is cleared (FPCLRn bit = 1 in the SFA3n register) and when 16 data have been transferred (SFFULn bit = 0, SFEMPn bit = 1, SFPn3 to SFPn0 bits = 0000 in the SFA3n register). If data exceeding the number of transfer data specified by the SFNn3 to SFNn0 bits of the SFN3n register are written to the CSIBUFn register, the excess 566 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-32. Continuous Mode 15 15 0 Write CSIBUFn pointer Transfer data 3 Transfer data 2 Transfer data 1 0 CSI data buffer register n (CSIBUFn) 15 SFDB3nH 87 SFDB3nL 0 7 43 0 Transfer data 0 Read CSIBUFn pointer SIOn load/store CSIBUFn pointer Incremented Incremented Incremented SFPn3 to SFPn0 CSIBUF status register 3n (SFA3n) Note 1 Transmit data CSI buffer register 3n (SFDB3n) Note 2 Note 1 SOn SIOn SIn SIRB3n Notes 1. 2. Remark Reception Transmission n = 0, 1 User's Manual U16031EJ4V1UD 567 CHAPTER 10 SERIAL INTERFACE FUNCTION (11) Transmission mode The transmission mode is set when the CTXEn bit of the CSIM3n register is set to 1 and the CRXEn bit is cleared to 0. In this mode, transmission is started by a trigger that writes transmit data to the SFDB3n register or sets the CTXEn bit to 1 when transmit data is in the CSIBUFn register (n = 0, 1). Even in the single mode (TRMDn bit = 0 in the CSIM3n register), whether the SIRB3n or SIOn register is empty has nothing to do with starting transmission. The value input to the SIn pin during transmission is latched in the shift register (SIOn) but is not transferred to the SIRB3n and CSIBUFn registers at the end of transmission. The transmission/reception completion interrupt (INTCSI3n) occurs immediately after data is sent out from the SIOn register. (12) Reception mode The reception mode is set when the CTXEn bit of the CSIM3n register is cleared to 0 and CRXEn bit is set to 1. In this mode, reception is started by using the processing of writing dummy data to the SFDB3n register as a trigger (n = 0, 1). In the single mode (TRMDn bit = 0 in the CSIM3n register), however, the condition of starting reception includes that the SIRB3n or SIOn register is empty. (If reception to the SIOn register is completed when the previously received data is held in the SIRB3n register without being read, the previously received data is read from the SIRB3n register and the wait status continues until the SIRB3n register becomes empty.) In the continuous mode, reception starts by writing dummy data of the number of receive data to the SFDB3n register with the first dummy data write processing taken as a trigger. The SOn pin outputs a low level. The transmission/reception completion interrupt (INTCSI3n) occurs immediately after receive data is transferred from the SIOn register to the SIRB3n register. (13) Transmission/reception mode The transmission/reception mode is set when both the CTXEn and CRXEn bits of the CSIM3n register are set to 1. In this mode, transmission/reception is started by using the processing to write transmit data to the SFDB3n register as a trigger (n = 0, 1). In the single mode (TRMDn bit = 0 in the CSIM3n register), however, the condition of starting transmission/reception includes that the SIRB3n or SIOn register is empty. (If reception to the SIOn register is completed when the previously received data is held in the SIRB3n register without being read, the previously received data is read from the SIRB3n register and the wait status continues until the SIRB3n register becomes empty.) 568 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (14) Delay control of transmission/reception completion interrupt (INTCSI3n) In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), occurrence of the transmission/reception completion interrupt (INTCSI3n) can be delayed by half a clock (1/2 serial clock), depending on the setting (1) of the CSITn bit of the CSIM3n register. The CSITn bit is valid only in the master mode. In the slave mode (CKS3n2 to CKS3n0 bits = 111 in the CSIC3n register), setting the CSITn bit to 1 is prohibited (even if set, the INTCSI3n interrupt is not affected). Caution If the CSITn bit of the CSIM3n register is set to 1 in the continuous mode (TRMDn bit = 1 in the CSIM3n register), the INTCSI3n interrupt is not output at the end of data other than the last data set by the SFNn3 to SFNn0 bits of the SFN3n register, but a delay of half a clock can be inserted between each data transfer. Figure 10-33. Delay Control of Transmission/Reception Completion Interrupt (INTCSI3n): CSITn Bit = 1 in CSIC3n Register, CSWEn Bit = 0, CKPn and DAPn Bits = 00, CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register (Transfer Data Length: 8 Bits) Delay SCKn (output) SIn (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI7 SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note DO7 INTCSI3n interrupt Delay Note If the CSITn bit of the CSIM3n register is set to 1 in the continuous mode (TRMDn bit = 1 in the CSIM3n register), the INTCSI3n interrupt is not output at the end of data other than the last data set by the SFNn3 to SFNn0 bits of the SFN3n register, but a delay of half a clock can be inserted between each data transfer. Remark n = 0, 1 User's Manual U16031EJ4V1UD 569 CHAPTER 10 SERIAL INTERFACE FUNCTION (15) Enabling/disabling transfer wait In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), starting transfer can be delayed by one clock for each time 1-bit data transfer is started, depending on the setting (1) of the CSWEn bit of the CSIM3n register (CSWEn bit = 1 (transfer wait inserted)). The CSWEn bit is valid only in the master mode. In the slave mode (CKS3n2 to CKS3n0 bits = 111 in the CSIC3n register), setting the CSWEn bit to 1 is prohibited (even if set, transfer wait is not inserted). Figure 10-34. Enabling/Disabling Transfer Wait (a) CSITn bit = 0, CSWEn bit = 1, CKPn and DAPn bits = 00, CCLn3 to CCLn0 bits = 1000 (transfer data length: 8 bits) Wait SCKn (output) SIn (input) DI7 DI6 DI5 DI1 DI0 DI7 SOn (output) DO7 DO6 DO5 DO1 DO0 DO7 (b) CSITn bit = 1, CSWEn bit = 1, CKPn and DAPn bits = 00, CCLn3 to CCLn0 bits = 1000 (transfer data length: 8 bits) Delay Wait SCKn (output) SIn (input) DI7 DI6 DI5 DI1 DI0 DI7 SOn (output) DO7 DO6 DO5 DO1 DO0 DO7 INTCSI3n interrupt Delay Remark n = 0, 1 570 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (16) Output pins (a) SCKn pin The SCKn pin outputs a high level when both the CTXEn and CRXEn bits of the CSIM3n register are 0 (n = 0, 1). In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), this pin outputs the default level when the FPCLRn bit of the SFA3n register is set to 1. Table 10-8. Default Output Level of SCKn Pin CKPn Bit 0 CKS3n2 to CKS3n0 Bits 111 (slave mode) Other than 111 (master mode) 1 111 (slave mode) Other than 111 (master mode) Low level Default Output Level of SCKn Pin High level Note High level - (input) Note Default value after reset or value when CSICAEn bit = 0 in the CSIM3n register Remarks 1. The output of the SCKn pin changes if the CKPn bit is rewritten in the master mode. 2. n = 0, 1 (b) SOn pin The SOn pin outputs a low level when both the CTXEn and CRXEn bits of the CSIM3n register are 0 (n = 0, 1). This pin outputs a low level when the FPCLRn bit of the SFA3n register is 1 (the previous value is retained only in the slave mode (CKS3n2 to CKS3n0 bits = 111 in the CSIC3n register) and when the DAPn bit = 0 in the CSIC3n register). Table 10-9. Default Output Level of SOn Pin Default Output Level of SOn Pin Low level Note Note Default value after reset or value when CSICAEn bit = 0 in the CSIM3n register Remark n = 0, 1 (17) CSIBUFn overflow interrupt signal (INTCOVF3n) The INTCOVF3n interrupt is output when 16 data exist in the CSIBUFn register and when the 17th data is written (to the SFDB3n or SFDB3nL register) (the 17th data is not written but ignored). In the single mode (TRMDn bit = 0 in the CSIM3n register), 16 data exist in the CSIBUFn register when "write CSIBUFn pointer value = SIOn load CSIBUFn pointer value and SFFULn bit = 1 in the SFA3n register". When transfer is completed and the SIOn load CSIBUFn pointer is incremented, the CSIBUFn register has one vacancy (the CSIBUFn register has no vacancy even when transfer of one data has been completed in the continuous mode (TRMDn bit = 1 in the CSIM3n register)). User's Manual U16031EJ4V1UD 571 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Usage (1) Single mode (in master mode and transmission mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <7> Confirm that the SFFULn bit of the SFA3n register is 0, and then write transfer data to the SFDB3n register. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTCSI3n, it is not always necessary to confirm that the SFFULn bit is 0. <8> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit of the SFA3n register is 1, and disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Caution To execute further transfer, repeat <7> before <8>. (2) Single mode (in master mode and reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. <7> Confirm that the SFFULn bit of the SFA3n register is 0, and then write dummy transfer data to the SFDB3n register (reception start trigger). If it is clearly known that the SFFULn bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of INTCSI3n, it is not always necessary to confirm that the SFFULn bit is 0. <8> Confirm that the INTCSI3n interrupt has occurred, and then read the SIRB3n register. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1, and disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Cautions 1. To execute further transfer, repeat <7> and <8> before <9>. 2. The SOn pin outputs a low level but this is invalid. 572 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Single mode (in master mode and transmission/reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting the CTXEn and CRXEn bits to 1. <7> Confirm that the SFFULn bit of the SFA3n register is 0, and then write transfer data to the SFDB3n register. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTCSI3n, it is not always necessary to confirm that the SFFULn bit is 0. <8> Confirm that the INTCSI3n interrupt has occurred, and then read the SIRB3n register. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1, and disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Caution To execute further transfer, repeat <7> and <8> before <9>. (4) Single mode (in slave mode and transmission mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <7> Confirm that the SFFULn bit of the SFA3n register is 0, and then write transfer data to the SFDB3n register. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTCSI3n, it is not always necessary to confirm that the SFFULn bit is 0. <8> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1, and disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Caution To execute further transfer, repeat <7> before <8>. User's Manual U16031EJ4V1UD 573 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Single mode (in slave mode and reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. <7> Confirm that the SFFULn bit of the SFA3n register is 0, and then write dummy transfer data to the SFDB3n register (reception start trigger). If it is clearly known that the SFFULn bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of INTCSI3n, it is not always necessary to confirm that the SFFULn bit is 0. <8> Confirm that the INTCSI3n interrupt has occurred, and then read the SIRB3n register. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1, and disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Cautions 1. To execute further transfer, repeat <7> and <8> before <9>. 2. The SOn pin outputs a low level but this is invalid. (6) Single mode (in slave mode and transmission/reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting the CTXEn and CRXEn bits to 1. <7> Confirm that the SFFULn bit of the SFA3n register is 0, and then write transfer data to the SFDB3n register. If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTCSI3n, it is not always necessary to confirm that the SFFULn bit is 0. <8> Confirm that the INTCSI3n interrupt has occurred, and then read the SIRB3n register. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1, and disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Caution To execute further transfer, repeat <7> and <8> before <9>. 574 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Continuous mode (in master mode and transmission mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <7> Set the amount of data to be transmitted by using the SFNn3 to SFNn0 bits of the SFN3n register. <8> Write the amount of data to be transmitted to the SFDB3n register as transfer data. Writing data exceeding the set value of the SFN3n register is prohibited. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1. Then write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <10> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <11> Disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Caution To execute further transfer, repeat <7> to <10> before <11>. (8) Continuous mode (in master mode and reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. <7> Set the amount of data to be received by using the SFNn3 to SFNn0 bits of the SFN3n register. <8> Write dummy transfer data of the number of receive data to the SFDB3n register. The first dummy transfer data write is the trigger to start reception. Writing dummy data exceeding the set value of the SFN3n register is prohibited. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1. Then read the receive data from the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <10> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <11> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <12> Disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Cautions 1. To execute further transfer, repeat <7> to <11> before <12>. 2. The SOn pin outputs a low level. User's Manual U16031EJ4V1UD 575 CHAPTER 10 SERIAL INTERFACE FUNCTION (9) Continuous mode (in master mode and transmission/reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting both the CTXEn and CRXEn bits to 1. <7> Set the amount of data to be transmitted/received by using the SFNn3 to SFNn0 bits of the SFN3n register. <8> Write the amount of data to be transmitted to the SFDB3n register as transfer data. Writing data exceeding the set value of the SFN3n register is prohibited. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1. Then read the receive data from the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <10> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <11> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <12> Disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Caution To execute further transfer, repeat <7> to <11> before <12>. (10) Continuous mode (in slave mode and transmission mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission by setting the CTXEn bit to 1. <7> Set the amount of data to be transmitted by using the SFNn3 to SFNn0 bits of the SFN3n register. <8> Write the amount of data to be transmitted to the SFDB3n register as transfer data. Writing data exceeding the set value of the SFN3n register is prohibited. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1. Then write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <10> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <11> Disable transmission by clearing the CTXEn bit of the CSIM3n register to 0 (end of transmission). Caution To execute further transfer, repeat <7> to <10> before <11>. 576 User's Manual U16031EJ4V1UD CHAPTER 10 SERIAL INTERFACE FUNCTION (11) Continuous mode (in slave mode and reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1. <7> Set the amount of data to be received by using the SFNn3 to SFNn0 bits of the SFN3n register. <8> Write dummy transfer data of the number of receive data to the SFDB3n register. The first dummy transfer data write is the trigger to start reception. Writing dummy data exceeding the set value of the SFN3n register is prohibited. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1. Then read the receive data from the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <10> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <11> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <12> Disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception). Cautions 1. To execute further transfer, repeat <7> to <11> before <12>. 2. The SOn pin outputs a low level. (12) Continuous mode (in slave mode and transmission/reception mode) <1> Set the external pins related to the CSI3n function to control mode. <2> When the CSICAEn bit of the CSIM3n register is set to 1, supplying the operating clock is enabled. <3> Specify the transfer mode by setting the CSIC3n and CSIL3n registers. <4> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0. <5> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <6> Specify the transfer mode by using the TRMDn, DIRn, CSITn, and CSWEn bits of the CSIM3n register and, at the same time, enable transmission/reception by setting both the CTXEn and CRXEn bits to 1. <7> Set the number of data to be transmitted/received by using the SFNn3 to SFNn0 bits of the SFN3n register. <8> Write the amount of data to be transmitted to the SFDB3n register as transfer data. Writing data exceeding the set value of the SFN3n register is prohibited. <9> Confirm that the INTCSI3n interrupt has occurred and the SFEMPn bit is 1. Then read the receive data from the SIRB3n register (sequentially read the receive data stored in the CSIBUFn register). <10> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer. <11> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n register. <12> Disable transmission/reception by clearing the CTXEn and CRXEn bits of the CSIM3n register to 0 (end of transmission/reception). Caution To execute further transfer, repeat <7 to <11> before <12>. User's Manual U16031EJ4V1UD 577 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.7 Cautions Cautions concerning CSI3n are shown below (n = 0, 1). (1) Stopping CSI3n The CSI3n unit is reset and CSI3n is stopped when the CSICAEn bit of the CSIM3n register is cleared to 0. To operate CSI3n, first set the CSICAEn bit to 1. Usually, before clearing the CSICAEn bit to 0, clear both the CTXEn and CRXEn bits to 0 (after the end of transfer). (2) Enabling transfer Be sure to write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0 before enabling transfer by setting the CTXEn or CRXEn bit of the CSIM3n register to 1. If the CTXEn or CRXEn bit is set to 1 without clearing the pointers, and if the previously transferred data remains in the CSIBUFn register, transferring that data is immediately started. If transfer data is set to the CSIBUFn register before transfer is enabled, transfer is started as soon as the CTXEn or CRXEn bit is set to 1. (3) Caution on setting SFA3n register If the SFA3n register is read immediately after data has been written to the SFDB3n and SFDB3nL registers when the main clock (fX) is used at 84 MHz or lower, the SFFULn, SFEMPn, and SFPn3 to SFPn0 bits of the SFA3n register may not change their values in time. If the SFA3n register is read before the SFFULn bit is set to 1 and the 17th data is written, the CSIBUFn overflow interrupt (INTCOVF3n) occurs. (4) Caution on setting CSIM3n register Be sure to set the external pins related to the CSI3n function to the control mode before using CSI3n. Then set the CSICAEn bit to 1 before setting the other bits. (5) Maximum transfer rate in master mode Because the maximum transfer rate in the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register) is 5.5 Mbps, do not exceed this value. (6) Writing data to SFDB3n register in single mode Be sure to confirm that the SFFULn bit of the SFA3n register is 0 when writing data to the SFDB3n register. Even if data is written to this register when SFFULn bit is 1, the CSIBUFn overflow interrupt (INTCOVF3n) is issued, and the written data is ignored. (7) SFA3n register status in continuous mode The SFA3n register is in the same status when transfer data is written (before start of transfer) after the CSIBUFn pointer is cleared (FPCLRn bit = 1 in the SFA3n register) and when 16 data have been transferred (SFFULn bit = 0, SFEMPn bit = 1, SFPn3 to SFPn0 bits = 0000 in the SFA3n register). 578 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) The V850E/ME2 has an internal USB function controller (USBF) conforming to the Universal Serial Bus Specification. 11.1 Overview * Conforms to the Universal Serial Bus Specification. * Supports 12 Mbps (full-speed) transfer * Endpoint for transfer incorporated Endpoint Name Endpoint0 Read Endpoint0 Write Endpoint1 Endpoint2 Endpoint3 Endpoint4 Endpoint7 Endpoint8 64 64 64 x 2 64 x 2 64 x 2 64 x 2 8 8 FIFO Size (Bytes) Transfer Type Control transfer Control transfer Bulk 1 transfer (IN) Bulk 1 transfer (OUT) Bulk 2 transfer (IN) Bulk 2 transfer (OUT) Interrupt 1 transfer Interrupt 2 transfer Remark - - 2-buffer configuration 2-buffer configuration 2-buffer configuration 2-buffer configuration - - * Clock: Clock input from UCK pin (fUSB = 48 MHz) Caution When using the USB function, be sure to set (1) the UCKCNT bit of the UCKC register. If the registers related to the USB function while the UCKCNT bit is 0, 0 is read. User's Manual U16031EJ4V1UD 579 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.2 Configuration USB function 0 DMA channel select register (UF0CS) USB UFDRQn DMAAKn TCn Endpoint Endpoint0R Endpoint0W Endpoint1 Endpoint2 Endpoint3 Endpoint4 Endpoint7 Endpoint8 (64 bytes) (64 bytes) (64 bytes x 2) (64 bytes x 2) (64 bytes x 2) (64 bytes x 2) (64 bytes) (64 bytes) USBSP2B USBSP4B INTUSB0B INTUSB1B INTUSB2B Selector SIE I/O buffer UDM UDP INTRSUM fUSB (48 MHz) USB function 0 buffer control register (UF0BC) Remark n = 0 to 3 580 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.3 Requests 11.3.1 Automatic requests (1) Decode The following tables show the request formats and correspondence between requests and decoded values. Table 11-1. Request Format Offset 0 1 2 3 4 5 6 7 wLength wIndex Field Name bmRequestType bRequest wValue Lower side Higher side Lower side Higher side Lower side Higher side User's Manual U16031EJ4V1UD 581 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Table 11-2. Correspondence Between Requests and Decoded Values Offset bmRequestType bRequest Request GET_INTERFACE 0 81H 1 0AH 3 00H Decoded Value wValue 2 00H 5 00H wIndex 4 0nH wLength 7 00H 6 01H STALL STALL ACK NAK GET_CONFIGURATION 80H 08H 00H 00H 00H 00H 00H 01H ACK NAK GET_DESCRIPTOR Device GET_DESCRIPTOR Configuration GET_STATUS Device GET_STATUS Endpoint 0 GET_STATUS Endpoint X CLEAR_FEATURE DeviceNote 2 CLEAR_FEATURE Endpoint 0Note 2 CLEAR_FEATURE Endpoint XNote 2 SET_FEATURE DeviceNote 3 SET_FEATURE Endpoint 0Note 3 SET_FEATURE Endpoint XNote 3 SET_INTERFACE 01H 0BH 00H 0#H 00H 0?H 00H 00H STALL STALL 02H 03H 00H 00H 00H 02H 03H 00H 00H 00H 00H 80H $$H 00H 00H 00H 00H 00H 03H 00H 01H 00H 00H 00H 00H ACK NAK ACK NAK STALL ACK NAK ACK NAK STALL 02H 01H 00H 00H 00H 02H 01H 00H 00H 00H 00H 80H $$H 00H 00H 00H 00H 00H 01H 00H 01H 00H 00H 00H 00H ACK NAK ACK NAK STALL ACK NAK ACK NAK STALL 82H 00H 00H 00H 00H 82H 00H 00H 00H 00H 00H 80H $$H 00H 02H 00H 02H 80H 00H 00H 00H 00H 00H 00H 02H 80H 06H 02H 00H 00H 00H XXH XXHNote 1 80H 06H 01H 00H 00H 00H XXH XXHNote 1 ACK NAK ACK NAK ACK NAK ACK NAK STALL ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK STALL ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK SET_CONFIGURATIONNote 4 00H 09H 00H 00H 01H SET_ADDRESS 00H 05H XXH XXH 00H 00H 00H 00H 00H 00H 00H 00H ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK ACK NAK x x x x x x x x x Df Response Ad Cf Data Stage Remark : Data stage is provided x: Data stage is not provided Notes 1. If the wLength value is less than the prepared value, the wLength value is returned; if the wLength value is greater than the prepared value, the prepared value is returned. 2. The CLEAR_FEATURE request clears UF0 device status register L (UF0DSTL) and UF0 EPn status register L (UF0EnSL) (n = 0 to 4, 7, 8) when ACK is received in the status stage. 582 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Notes 3. The SET_FEATURE request sets the UF0 device status register L (UF0DSTL) and UF0 EPn status register L (UF0EnSL) (n = 0 to 4, 7, 8) when ACK is received in the status stage. If the E0HALT bit of the UF0E0SL register is set, a STALL response is made in the status stage or data stage of control transfer for a request other than the GET_STATUS Endpoint0 request, SET_FEATURE Endpoint0 request, and a request generated by the CPUDEC interrupt request, until the CLEAR_FEATURE Endpoint0 request is received. A STALL response to an unsupported request does not set the E0HALT bit of the UF0E0SL register to 1, and the STALL response is cleared as soon as the next SETUP token has been received. 4. If the wValue is not the default value, an automatic STALL response is made. Cautions 1. The sequence of control transfer defined by the Universal Serial Bus Specification is not satisfied under the following conditions. conditions. * If an IN/OUT token is suddenly received without a SETUP stage * If DATA PID1 is sent in the data phase of the SETUP stage * If a token of 128 addresses or more is received * If the request data transmitted in the SETUP stage is of less than 8 bytes 2. An ACK response is made even when the host transmits data other than a Null packet in the status stage. 3. If the wLength value is 00H during control transfer (read) of FW processing, a Null packet is automatically transmitted for control transfer (without data). automatically transmit a Null packet. Remarks 1. Df: Default state, Ad: Addressed state, Cf: Configured state 2. n = 0 to 4 It is determined by the setting of the UF0 active interface number register (UF0AIFN) whether a request with Interface number 1 to 4 is correctly responded to, depending on whether the Interface number of the target is valid or not. 3. $$: Valid endpoint number including transfer direction The valid endpoint is determined by the currently set Alternate Setting number (see 11.4.1 (36) UF0 active alternative setting register (UF0AAS), (38) UF0 endpoint 1 interface mapping register (UF0E1IM) to (43) UF0 endpoint 8 interface mapping register (UF0E8IM)). 4. ? and #: Value transmitted from host (information on Interface numbers 0 to 4) It is determined by the UF0 active interface number register (UF0AIFN) and UF0 active alternative setting register (UF0AAS) whether an Alternate Setting request corresponding to each Interface number is correctly responded to or not, depending on whether the Interface number and Alternate Setting of the target are valid or not. The FW request does not The operation is not guaranteed under these User's Manual U16031EJ4V1UD 583 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2) Processing The processing of an automatic request in the Default state, Addressed state, and Configured state is described below. Remark Default state: State in which an operation is performed with the Default address Addressed state: State after an address has been allocated Configured state: State after SET_CONFIGURATION wValue = 1 has been correctly received (a) CLEAR_FEATURE() request A STALL response is made in the status stage if the CLEAR_FEATURE() request cannot be cleared, if FEATURE does not exist, or if the target is an interface or an endpoint that does not exist. A STALL response is also made if the wLength value is other than 0. * Default state: The correct response is made when the CLEAR_FEATURE() request has been received only if the target is a device or a request for Endpoint0; otherwise a STALL response is made in the status stage. * Addressed state: The correct response is made when the CLEAR_FEATURE() request has been received only if the target is a device or a request for Endpoint0; otherwise a STALL response is made in the status stage. * Configured state: The correct response is made when the CLEAR_FEATURE() request has been received only if the target is a device or a request for an endpoint that exists; otherwise a STALL response is made in the status stage. When the CLEAR_FEATURE() request has been correctly processed, the corresponding bit of the UF0 CLR request register (UF0CLR) is set to 1, the EnHALT bit of the UF0 EPn status register L (UF0EnSL) is cleared to 0, and an interrupt is issued (n = 0 to 4, 7, 8). If the CLEAR_FEATURE() request is received when the subject is an endpoint, the toggle bit (that controls switching between DATA0 and DATA1) of the corresponding endpoint is always re-set to DATA0. (b) GET_CONFIGURATION() request A STALL response is made in the data stage if any of wValue, wIndex, or wLength is other than the values shown in Table 11-2. * Default state: The value stored in the UF0 configuration register (UF0CNF) is returned when the GET_CONFIGURATION() request has been received. * Addressed state: The * Configured state: The value value stored stored in in the the UF0CNF UF0CNF register register is is returned returned when when the the GET_CONFIGURATION() request has been received. GET_CONFIGURATION() request has been received. 584 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (c) GET_DESCRIPTOR() request If the subject descriptor has a length that is a multiple of wMaxPacketSize, a Null packet is returned to indicate the end of the data stage. If the length of the descriptor at this time is less than the wLength value, the entire descriptor is returned; if the length of the descriptor is greater than the wLength value, the descriptor up to the wLength value is returned. * Default state: The value stored in UF0 device descriptor register n (UF0DDn) and UF0 configuration/interface/endpoint descriptor register m (UF0CIEm) is returned (n = 0 to 17, m = 0 to 255) when the GET_DESCRIPTOR() request has been received. * Addressed state: The value stored in the UF0DDn register and UF0CIEm register is returned when the GET_DESCRIPTOR() request has been received. * Configured state: The value stored in the UF0DDn register and UF0CIEm register is returned when the GET_DESCRIPTOR() request has been received. A descriptor of up to 256 bytes can be stored in the UF0CIEm register. To return a descriptor of more than 256 bytes, set the CDCGDST bit of the UF0MODC register to 1 and process the GET_DESCRIPTOR() request by FW. Store the value of the total number of bytes of the descriptor set by the UF0CIEm register - 1 in the UF0 descriptor length register (UF0DSCL). The transfer data is controlled by the value of this data + 1 and wLength. (d) GET_INTERFACE() request If either of wValue and wLength is other than that shown in Table 11-2, or if wIndex is other than that set by the UF0 active interface number register (UF0AIFN), a STALL response is made in the data stage. * Default state: A STALL response is made in the data stage when the GET_INTERFACE() request has been received. * Addressed state: A STALL response is made in the data stage when the GET_INTERFACE() request has been received. * Configured state: The value stored in the UF0 interface n register (UF0IFn) corresponding to the wIndex value is returned (n = 0 to 4) when the GET_INTERFACE() request has been received. User's Manual U16031EJ4V1UD 585 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (e) GET_STATUS() request A STALL response is made in the data stage if any of wValue, wIndex, or wLength is other than the values shown in Table 11-2. A STALL response is also made in the data stage if the target is an interface or an endpoint that does not exist. * Default state: The value stored in the target status registerNote is returned only when the GET_STATUS() request has been received and when the request is for a device or Endpoint0; otherwise a STALL response is made in the data stage. * Addressed state: The value stored in the target status registerNote is returned only when the GET_STATUS() request has been received and when the request is for a device or Endpoint0; otherwise a STALL response is made in the data stage. * Configured state: The value stored in the target status registerNote is returned only when the GET_STATUS() request has been received and when the request is for a device or an endpoint that exists; otherwise a STALL response is made in the data stage. Note The target status register is as follows. * If the target is a device: UF0 device status register L (UF0DSTL) * If the target is endpoint 0: UF0 EP0 status register L (UF0E0SL) * If the target is endpoint n: UF0 EPn status register L (UF0EnSL) (n = 1 to 4, 7, 8) (f) SET_ADDRESS() request A STALL response is made in the status stage if either of wIndex or wLength is other than the values shown in Table 11-2. A STALL response is also made if the specified device address is greater than 127. * Default state: The device enters the Addressed state and changes the USB Address value to be input to SIE into a specified address value if the specified address is other than 0 when the SET_ADDRESS() request has been received. If the specified address is 0, the device remains in the Default state. * Addressed state: The device enters the Default state and returns the USB Address value to be input to SIE to the default address if the specified address is 0 when the SET_ADDRESS() request has been received. If the specified address is other than 0, the device remains in the Addressed state, and changes the USB Address value to be input to SIE into a specified new address value. * Configured state: The device remains in the Configured state and returns the USB Address value to be input to SIE to the default address if the specified address is 0 when the SET_ADDRESS() request has been received. In this case, the endpoints other than endpoint 0 remain valid, and control transfer (IN), control transfer (OUT), bulk transfer and interrupt transfer for an endpoint other than endpoint 0 are also acknowledged. If the specified address is other than 0, the device remains in the Configured state and changes the USB Address value to be input to SIE into a specified new address value. 586 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (g) SET_CONFIGURATION() request If any of wValue, wIndex, or wLength is other than the values shown in Table 11-2, a STALL response is made in the status stage. * Default state: The CONF bit of the UF0 mode status register (UF0MODS) and the UF0 configuration register (UF0CNF) are set to 1 if the specified configuration value is 1 when the SET_CONFIGURATION() request has been received. If the specified configuration value is 0, the CONF bit of the UF0MODS register and UF0CNF register are cleared to 0. In other words, the device skips the Addressed state and moves to the Configured state in which it responds to the Default address. * Addressed state: The CONF bit of the UF0MODS register and UF0CNF register are set to 1 and the device enters the Configured state if the specified configuration value is 1 when the SET_CONFIGURATION() request has been received. If the specified configuration value is 0, the device remains in the Addressed state. * Configured state: The CONF bit of the UF0MODS register and UF0CNF register are set to 1 and the device returns to the Addressed state if the specified configuration value is 0 when the SET_CONFIGURATION() request has been received. If the specified configuration value is 1, the device remains in the Configured state. If the SET_CONFIGURATION() request has been correctly processed, the target bit of the UF0 SET request register (UF0SET) is set to 1, and an interrupt is issued. All Halt Features are cleared after the SET_CONFIGURATION() request has been completed even if the specified configuration value is the same as the current configuration value. If the SET_CONFIGURATION() request has been correctly processed, the data toggle of all endpoints is always initialized to DATA0 again (it is defined that the default status, Alternative Setting 0, is set from when the SET_CONFIGURATION request is received to when the SET_INTERFACE request is received). (h) SET_FEATURE() request A STALL response is made in the status stage if the SET_FEATURE() request is for a Feature that cannot be set or does not exist, or if the target is an interface or an endpoint that does not exist. A STALL response is also made if the wLength value is other than 0. * Default state: The correct response is made when the SET_FEATURE() request has been received, only if the request is for a device or Endpoint0; otherwise a STALL response is made in the status stage. * Addressed state: The correct response is made when the SET_FEATURE() request has been received, only if the request is for a device or Endpoint0; otherwise a STALL response is made in the status stage. * Configured state: The correct response is made when the SET_FEATURE() request has been received, only if the request is for a device or an endpoint that exists; otherwise a STALL response is made in the status stage. When the SET_FEATURE() request has been correctly processed, the target bit of the UF0 SET request register (UF0SET) and the EnHALT bit of the UF0 EPn status register L (UF0EnSL) are set to 1, and an interrupt is issued (n = 0 to 4, 7, 8). User's Manual U16031EJ4V1UD 587 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (i) SET_INTERFACE() request If wLength is other than the values shown in Table 11-2, if wIndex is other than the value set to the UF0 active interface number register (UF0AIFN), or if wValue is other than the value set to the UF0 active alternative setting register (UF0AAS), a STALL response is made in the status stage. * Default state: A STALL response is made in the status stage when the SET_INTERFACE() request has been received. * Addressed state: A STALL response is made in the status stage when the SET_INTERFACE() request has been received. * Configured state: Null packet is transmitted in the status stage when the SET_INTERFACE() request has been received. When the SET_INTERFACE() request has been correctly processed, an interrupt is issued. All the Halt Features of the endpoint linked to the target Interface are cleared after the SET_INTERFACE() request has been cleared. The data toggle of all the endpoints related to the target Interface number is always initialized again to DATA0. When the currently selected Alternative Setting is to be changed by correctly processing the SET_INTERFACE() request, the FIFO of the endpoint that is affected is completely cleared, and all the related interrupt sources are also initialized. When the SET_INTERFACE() request has been completed, the FIFO of all the endpoints linked to the target Interface are cleared. At the same time, Halt Feature and Data PID are initialized, and the related UF0 INT status n register (UF0ISn) is cleared to 0 (n = 0 to 4). (Only Halt Feature and Data PID are cleared when the SET_CONFIGURATION request has been completed.) If the target Endpoint is not supported by the SET_INTERFACE() request during DMA transfer, the DMA request signal is immediately deasserted, and the FIFO of the Endpoint that has been linked when the SET_INTERFACE() request has been completed is completely cleared. As a result of this clearing of the FIFO, data transferred by DMA is not correctly processed. 11.3.2 Other requests (1) Response and processing The following table shows how other requests are responded to and processed. Table 11-3. Response and Processing of Other Requests Request GET_DESCRIPTOR String GET_STATUS Interface CLEAR_FEATURE Interface SET_FEATURE Interface all SET_DESCRIPTOR All other requests Response and Processing Generation of CPUDEC interrupt request Automatic STALL response Automatic STALL response Automatic STALL response Generation of CPUDEC interrupt request Generation of CPUDEC interrupt request 588 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.4 Register Configuration 11.4.1 Control registers (1) UF0 EP0NAK register (UF0E0N) This register controls NAK of Endpoint0 (except an automatically executed request). This register can be read or written in 8-bit units (however, bit 0 can only be read). It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set. If it is necessary to read the status correctly, therefore, separate a write signal that accesses the UF0FIC0 and UF0FIC1 registers from a read signal that accesses the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by at least four USB clocks. While NAK is being transmitted to Endpoint0 Read, Endpoint2, and Endpoint4, a write access to the EP0NKR bit is ignored. 7 UF0E0N 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFFE00H After reset 00H EP0NKR EP0NKW Bit position 1 Bit name EP0NKR Function This bit controls NAK to the OUT token to Endpoint0 (except an automatically executed request). It is automatically set to 1 by hardware when Endpoint0 has correctly received data. It is also cleared to 0 by hardware when the data of the UF0E0R register has been read by FW (counter value = 0). 1: Transmit NAK. 0: Do not transmit NAK (default value). Set this bit to 1 by FW when data should not be received from the USB bus for some reason even when USBF is ready for receiving data. In this case, USBF continues transmitting NAK until this bit is cleared to 0 by FW. This bit is also cleared to 0 as soon as the UF0E0R register has been cleared. 0 EP0NKW This bit indicates how NAK to the IN token to Endpoint0 is controlled (except an automatically executed request). This bit is automatically cleared to 0 by hardware when the data of Endpoint0 is transmitted and the host correctly receives the transmitted data. The data of the UF0E0W register is retained until this bit is cleared. Therefore, it is not necessary to rewrite this bit even in the case of a retransmission request that is made if the host could not receive data correctly. To send a short packet, be sure to set the E0DED bit of the UF0DEND register to 1. This bit is automatically set to 1 when the FIFO is full. As soon as the E0DED bit of the UF0DEND register is set to 1, the EP0NKW bit is automatically set to 1 at the same time. 1: Do not transmit NAK. 0: Transmit NAK (default value). If control transfer enters the status stage while ACK cannot be correctly received in the data stage, this bit is cleared to 0 as soon as the UF0E0W register is cleared. This bit is also cleared to 0 when UF0E0W is cleared by FW. User's Manual U16031EJ4V1UD 589 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Next, the procedure of a SETUP transaction that uses IN/OUT tokens is explained below. (a) When IN token is used (except a request automatically executed by hardware) FW should be used to clear the PROT bit of the UF0IS1 register to 0 after receiving the CPUDEC interrupt and before reading data from the UF0E0ST register. Next, perform processing in accordance with the request and, if it is necessary to return data by an IN token, write data to the UF0E0W register. Confirm that the PROT bit of the UF0IS1 register is 0 after writing has been completed, and set the E0DED bit of the UF0DEND register to 1. The hardware sends out data at the first IN token after the EP0NKW bit has been set to 1. If the PROT bit of the UF0IS1 register is 1, it indicates that a SETUP transaction has occurred again before completion of control transfer. In this case, clear the PROTC bit of the UF0IC1 register to 0 and clear the PROT bit of the UF0IS1 register to 0, and then read data from the UF0E0ST register again. A request received later can be read. (b) When OUT token is used (except a request automatically executed by hardware) FW should be used to clear the PROT bit of the UF0IS1 register after receiving the CPUDEC interrupt and before reading data from the UF0E0ST register. Confirm that the PROT bit of the UF0IS1 register is 0 before reading data from the UF0E0R register. If the PROT bit is 1, it means that invalid data is retained. Clear the FIFO by FW (the EP0NKR bit is automatically cleared to 0). If the PROT bit of the UF0IS1 register is 0, read the data of the UF0E0L register and read as many data from the UF0E0R register as set. When reading data from the UF0E0R register has been completed (when the counter of the UF0E0R register has been cleared to 0), the hardware automatically clears the EP0NKR bit to 0. 590 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0NAKALL register (UF0E0NA) This register controls NAK to all the requests of Endpoint0. It is also valid for automatically executed requests. This register can be read or written in 8-bit units. 7 UF0E0NA 0 6 0 5 0 4 0 3 0 2 0 1 0 0 EP0NKA Address FFFFFE01H After reset 00H Bit position 0 Bit name EP0NKA Function This bit controls NAK to a transaction other than a SETUP transaction to Endpoint0 (including an automatically executed request). This bit is manipulated by FW. 1: Transmit NAK. 0: Do not transmit NAK (default value). This register is used to prevent a conflict between a write access by FW and a read access from SIE when the data used for an automatically executed request is to be changed. It postpones reflecting a write access on this bit from FW while an access from SIE is being made. Before rewriting the request data register from FW, confirm that this bit has been correctly set to 1. Setting this bit to 1 is reflected only in the following cases. * Immediately after USBF has been reset and a SETUP token has never been received * Immediately after reception of Bus Reset and a SETUP token has never been received * PID of a SETUP token has been detected * The stage has been changed to the status stage Clearing this bit to 0 is reflected immediately, except while an IN token is being received and a NAK response is being made. Setting the EP0NKA bit to 1 is reflected in the above four cases during Endpoint0 transfer, but it is reflected immediately after data has been written to the bit while Endpoint0 is transferring no data. User's Manual U16031EJ4V1UD 591 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (3) UF0 EPNAK register (UF0EN) This register controls NAK of endpoints other than Endpoint0. This register can be read or written in 8-bit units (however, bits 5, 4, 1, and 0 can only be read). The BKO2NK bit can be written only when the BKO2NKM bit of the UF0ENM register is 1 and the BKO1NK bit can be written only when the BKO1NKM bit of the UF0ENM register is 1. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7, 8) and the current setting of the interface. It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set. If it is necessary to read the status correctly, therefore, separate a write signal that accesses the UF0FIC0 and UF0FIC1 registers from a read signal that accesses the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by at least four USB clocks. While NAK is being transmitted to Endpoint0 Read, Endpoint2, and Endpoint4, a write access to the BKO1NK and BKO2NK bits is ignored. Be sure to clear bits 7 and 6 to 0. If it is set to 1, the operation is not guaranteed. (1/4) 7 UF0EN 0 6 0 5 IT2NK 4 IT1NK 3 2 1 0 BKI1NK Address FFFFFE02H After reset 00H BKO2NK BKO1NK BKI2NK Bit position 5 Bit name IT2NK Function This bit controls NAK to Endpoint8 (interrupt 2 transfer). It is automatically set to 1 and transmission is started when the UF0INT2 register has become full as a result of writing data to it. To send a short packet that does not make the FIFO full, set the IT2DEND bit of the UF0DEND register to 1. As soon as the IT2DEND bit has been set to 1, this bit is automatically set to 1. 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is also cleared to 0 when the UF0INT2 register has been cleared. 4 IT1NK This bit controls NAK to Endpoint7 (interrupt 1 transfer). It is automatically set to 1 and transmission is started when the UF0INT1 register has become full as a result of writing data to it. To send a short packet that does not make the FIFO full, set the IT1DEND bit of the UF0DEND register to 1. As soon as the IT1DEND bit has been set to 1, this bit is automatically set to 1. 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is also cleared to 0 when the UF0INT1 register has been cleared. 592 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2/4) Bit position 3 Bit name BKO2NK Function This bit controls NAK to Endpoint4 (bulk 2 transfer (OUT)). 1: Transmit NAK. 0: Do not transmit NAK (default value). This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO2 register (64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a toggle operation is performed. The bank is changed (toggle operation) when the following conditions are satisfied. * Data correctly received is stored in the FIFO connected to the SIE side. * The value of the FIFO counter connected to the CPU side is 0 (completion of reading). FW should be used to read data of the UF0BO2L register when it has received the BLKO2DT interrupt request and read as many data from the UF0BO2 register as the value of that data. To not receive data from the USB bus for some reason even if USBF is ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting NAK until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO2 register has been cleared. 2 BKO1NK This bit controls NAK to Endpoint2 (bulk 1 transfer (OUT)). 1: Transmit NAK. 0: Do not transmit NAK (default value). This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO1 register (64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a toggle operation is performed. The bank is changed (toggle operation) when the following conditions are satisfied. * Data correctly received is stored in the FIFO connected to the SIE side. * The value of the FIFO counter connected to the CPU side is 0 (completion of reading). FW should be used to read data of the UF0BO1L register when it has received the BLKO1DT interrupt request and read as many data from the UF0BO1 register as the value of that data. To not receive data from the USB bus for some reason even if USBF is ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting NAK until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO1 register has been cleared. Cautions 1. If DMA is enabled while data is being read from the UF0BO2 register in the PIO mode, a DMA request is immediately issued. 2. If the last data of the FIFO on the CPU side is read in the DMA transfer mode, the DMA request signal becomes inactive. 3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes inactive. User's Manual U16031EJ4V1UD 593 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (3/4) Bit position 1 Bit name BKI2NK Function This bit controls NAK to Endpoint3 (bulk 2 transfer (IN)). 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI2 register (64-byte FIFO of bank configuration) cannot receive data. It is set to 1 when a toggle operation is performed (the data of the UF0BI2 register is retained until transmission has been correctly completed). The bank is changed (toggle operation) when the following conditions are satisfied. * Data is correctly written to the FIFO connected to the CPU bus side (writing has been completed and the FIFO is full or the UF0DEND register is set). * The value of the FIFO counter connected to the SIE side is 0. This bit is automatically set to 1 and data transmission is started when the FIFO on the CPU side becomes full and a FIFO toggle operation is performed as a result of writing data to the FIFO. However, if the FIFO on the CPU side becomes full as a result of writing data to it by DMA while the BKI2T bit of the UF0DEND register is cleared to 0, the toggle operation is not performed because the condition of the toggle operation is not satisfied until the BKI2DED bit of the UF0DEND register is set to 1. To send a short packet that does not make the FIFO on the CPU side full, set the BKI2DED bit to 1 after completing writing data. When the BKI2DED bit is set to 1, a toggle operation is performed and at the same time, this bit is automatically set to 1. This bit is also cleared to 0 as soon as the UF0BI2 register has been cleared. Cautions 1. If DMA is enabled while data is being written to the UF0BI2 register in the PIO mode, a DMA request is immediately issued. 2. If 64-byte data is written in the DMA transfer mode, the DMA request signal becomes inactive. If the BKI2NK bit is then set to 1, data is transmitted in synchronization with an IN token. The DMA request signal becomes active again as long as the DMA request is not masked as soon as the FIFO is toggled. If the BKI2NK bit is not set, data is not transmitted even if an IN token has been received. In this case, set the BKI2DED bit of the UF0DEND register to 1. 3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes inactive. At the same time, the DMA request is masked. If the BKI2NK bit is not set to 1, data is not transmitted even if an IN token is received. When the BKI2DED bit of the UF0DEND register is set to 1 by FW, data is transmitted in synchronization with the IN token. To execute DMA transfer again, unmask the DMA request. 594 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (4/4) Bit position 0 Bit name BKI1NK Function This bit controls NAK to Endpoint1 (bulk 1 transfer (IN)). 1: Do not transmit NAK. 0: Transmit NAK (default value). This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI1 register (64-byte FIFO of bank configuration) cannot receive data. It is set to 1 when a toggle operation is performed (the data of the UF0BI1 register is retained until transmission has been correctly completed). The bank is changed (toggle operation) when the following conditions are satisfied. * Data is correctly written to the FIFO connected to the CPU bus side (writing has been completed and the FIFO is full or the UF0DEND register is set). * The value of the FIFO counter connected to the SIE side is 0. This bit is automatically set to 1 and data transmission is started when the FIFO on the CPU side becomes full and a FIFO toggle operation is performed as a result of writing data to the FIFO. However, if the FIFO on the CPU side becomes full as a result of writing data to it by DMA while the BKI1T bit of the UF0DEND register is cleared to 0, the toggle operation is not performed because the condition of the toggle operation is not satisfied until the BKI1DED bit of the UF0DEND register is set to 1. To send a short packet that does not make the FIFO on the CPU side full, set the BKI1DED bit to 1 after completing writing data. When the BKI1DED bit is set to 1, a toggle operation is performed and at the same time, this bit is automatically set to 1. This bit is also cleared to 0 as soon as the UF0BI1 register has been cleared. Cautions 1. If DMA is enabled while data is being written to the UF0BI1 register in the PIO mode, a DMA request is immediately issued. 2. If 64-byte data is written in the DMA transfer mode, the DMA request signal becomes inactive. If the BKI1NK bit is then set to 1, data is transmitted in synchronization with an IN token. The DMA request signal becomes active again as long as the DMA request is not masked as soon as the FIFO is toggled. If the BKI1NK bit is not set, data is not transmitted even if an IN token has been received. In this case, set the BKI1DED bit of the UF0DEND register to 1. 3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes inactive. At the same time, the DMA request is masked. If the BKI1NK bit is not set to 1, data is not transmitted even if an IN token is received. When the BKI1DED bit of the UF0DEND register is set to 1 by FW, data is transmitted in synchronization with the IN token. To execute DMA transfer again, unmask the DMA request. User's Manual U16031EJ4V1UD 595 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (4) UF0 EPNAK mask register (UF0ENM) This register controls masking a write access to the UF0EN register. This register can be read or written in 8-bit units. Be sure to clear bits 7 to 4, 1, and 0. If it is set to 1, the operation is not guaranteed. 7 UF0ENM 0 6 0 5 0 4 0 3 2 1 0 0 0 Address FFFFFE03H After reset 00H BKO2NKM BKO1NKM Bit position 3 Bit name BKO2NKM Function This bit specifies whether a write access to bit 3 (BKO2NK) of the UF0EN register is masked or not. 1: Do not mask. 0: Mask (default value). 2 BKO1NKM This bit specifies whether a write access to bit 2 (BKO1NK) of the UF0EN register is masked or not. 1: Do not mask. 0: Mask (default value). 596 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (5) UF0 SNDSIE register (UF0SDS) This register performs manipulation such as no handshake. It can directly manipulate the pins of SIE. This register can be read or written in 8-bit units. Be sure to clear bit 2 to 0. If it is set to 1, the operation is not guaranteed. 7 UF0SDS 0 6 0 5 0 4 0 3 SNDSTL 2 0 1 0 0 RSUMIN Address FFFFFE04H After reset 00H Bit position 3 Bit name SNDSTL Function This bit makes Endpoint0 issue a STALL handshake. Setting this bit to 1 if a request for CPUDEC processing is not supported by the system results in a STALL handshake response. If an unsupported wValue is sent by the SET_CONFIGURATION or SET_INTERFACE request, the hardware sets this bit to 1. If a problem occurs in Endpoint0 due to overrun of an automatically executed request, this bit is also set to 1. However, the E0HALT bit of the UF0E0SL register is not set to 1. 1: Respond with STALL handshake. 0: Do not respond with STALL handshake (default value). This bit is cleared to 0 and the handshake response to the bus is other than STALL when the next SETUP token is received. To set the SNDSTL bit to 1 by FW, do not write data to the UF0E0W register. Depending on the timing of setting this bit, the STALL response is not made in time, and it may be made to the next transfer after a NAK response has been made. Setting this bit is valid only while an FW-executed request is under execution when this bit is set to 1. It is automatically cleared to 0 when the next SETUP token is received. Remark The SNDSTL bit is valid only for an FW-executed request. 0 RSUMIN This bit outputs the Resume signal onto the USB bus. Writing this bit is invalid unless the RMWK bit of the UF0DSTL register is set to 1. 1: Generate the Resume signal. 0: Do not generate the Resume signal (default value). While this bit is set to 1, the Resume signal continues to be generated. Clear this bit to 0 by FW after a specific time has elapsed. Because the signal is internally sampled at the clock, the operation is guaranteed only while CLK is supplied. Care must be exercised when CLK of the system is stopped. User's Manual U16031EJ4V1UD 597 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (6) UF0 CLR request register (UF0CLR) This register indicates the target of the received CLEAR_FEATURE request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7, 8) and the current setting of the interface. 7 UF0CLR 6 5 4 3 2 1 0 Address FFFFFE05H After reset 00H CLREP8 CLREP7 CLREP4 CLREP3 CLREP2 CLREP1 CLREP0 CLRDEV Bit position 7 to 1 Bit name CLREPn Function These bits indicate that a CLEAR_FEATURE Endpoint n request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) 0 CLRDEV This bit indicates that a CLEAR_FEATURE Device request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) Remark n = 0 to 4, 7, 8 598 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (7) UF0 SET request register (UF0SET) This register indicates the target of the automatically processed SET_XXXX (except SET_INTERFACE) request. This register is read-only, in 8-bit units. This register is meaningful only when an interrupt request is generated. Each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read. 7 UF0SET SETCON 6 0 5 0 4 0 3 0 2 SETEP 1 0 0 SETDEV Address FFFFFE06H After reset 00H Bit position 7 Bit name SETCON Function This bit indicates that a SET_CONFIGURATION request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) 2 SETEP This bit indicates that a SET_FEATURE Endpoint n request (n = 0 to 4, 7, 8) is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) 0 SETDEV This bit indicates that a SET_FEATURE Device request is received and automatically processed. 1: Automatically processed 0: Not automatically processed (default value) User's Manual U16031EJ4V1UD 599 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (8) UF0 EP status 0 register (UF0EPS0) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7, 8) and the current setting of the interface. It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been set. If it is necessary to read the status correctly, therefore, separate writing to the UF0FIC0 and UF0FIC1 registers from reading from the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by at least four USB clocks. (1/2) 7 UF0EPS0 IT2 6 IT1 5 4 3 BKIN2 2 BKIN1 1 EP0W 0 EP0R Address FFFFFE07H After reset 00H BKOUT2 BKOUT1 Bit position 7, 6 Bit name ITn Function These bits indicate that data is in the UF0INTn register (FIFO). By setting the ITnDED bit of the UF0DEND register to 1, the status in which data is in the UF0INTn register can be created even if data is not written to the register (Null data transmission). As soon as the ITnDED bit of the UF0DEND register is set to 1 even when the counter of the UF0INTn register is 0, this bit is set to 1 by hardware. It is cleared to 0 after correct transmission. 1: Data is in the register. 0: No data is in the register (default value). 5, 4 BKOUTn These bits indicate that data is in the UF0BOn register (FIFO) connected to the CPU side. When the FIFO configuring the UF0BOn register is toggled, this bit is automatically set to 1 by hardware. It is automatically cleared to 0 by hardware when reading the UF0BOn register (FIFO) connected to the CPU side has been completed (counter value = 0). It is not set to 1 when Null data is received (toggling the FIFO does not take place either). 1: Data is in the register. 0: No data is in the register (default value). 3, 2 BKINn These bits indicate that data is in the UF0BIn register (FIFO) connected to the CPU side. By setting the BKInDED bit of the UF0DEND register to 1, the status in which data is in the UF0BIn register can be created even if data is not written to the register (Null data transmission). As soon as the BKInDED bit of the UF0DEND register has been set to 1 while the counter of the UF0BIn register is 0, this bit is set to 1 by hardware. It is cleared to 0 when a toggle operation is performed. 1: Data is in the register. 0: No data is in the register (default value). Remark n = 1, 2 600 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 1 Bit name EP0W Function This bit indicates that data is in the UF0E0W register (FIFO). By setting the E0DED bit of the UF0DEND register to 1, the status in which data is in the UF0E0W register can be created even if data is not written to the register (Null data transmission). As soon as the E0DED bit of the UF0DEND register is set to 1 even when the counter of the UF0E0W register is 0, this bit is set to 1 by hardware. It is cleared to 0 after correct transmission. 1: Data is in the register. 0: No data is in the register (default value). 0 EP0R This bit indicates that data is in the UF0E0R register (FIFO). It is automatically cleared to 0 by hardware when reading the UF0E0R register (FIFO) has been completed (counter value = 0). It is not set to 1 if Null data is received. 1: Data is in the register. 0: No data is in the register (default value). User's Manual U16031EJ4V1UD 601 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (9) UF0 EP status 1 register (UF0EPS1) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. 7 UF0EPS1 RSUM 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFFE08H After reset 00H Bit position 7 Bit name RSUM Function This bit indicates that the USB bus is in the Resume status. This bit is meaningful only when an interrupt request is generated. 1: Suspend status 0: Resume status (default value) Because sampling is internally performed with the clock, the operation is guaranteed only when CLK is supplied. Care must be exercised when CLK of the system is stopped. The INTRSUM signal of SIE operates even when CLK is stopped. It can therefore be supported by making the interrupt control register (RSUMIC) valid or lowering the frequency of CLK to the USBF. This bit is automatically cleared to 0 when it is read. 602 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (10) UF0 EP status 2 register (UF0EPS2) This register indicates the USB bus status and the presence or absence of register data. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7, 8) and the current setting of the interface. 7 UF0EPS2 0 6 HALT8 5 HALT7 4 HALT4 3 HALT3 2 HALT2 1 HALT1 0 HALT0 Address FFFFFE09H After reset 00H Bit position 6 to 0 Bit name HALTn Function These bits indicate that Endpoint n is currently stalled. They are set to 1 when a stall condition, such as occurrence of an overrun and reception of an undefined request, is satisfied. These bits are automatically set to 1 by hardware. 1: Endpoint is stalled. 0: Endpoint is not stalled (default value). The SNDSTL bit is set to 1 as soon as the HALT0 bit has been set to 1 as a result of occurrence of an overrun or reception of an undefined request. If the next SETUP token is received in this status, the SNDSTL bit is cleared to 0 and, therefore, the HALT0 bit is also cleared to 0. If Endpoint0 is stalled by the SET_FEATURE Endpoint0 request, this bit is not cleared to 0 until the CLEAR_FEATURE Endpoint0 request is received or Halt Feature is cleared by FW. If the GET_STATUS Endpoint0, CLEAR_FEATURE Endpoint0, or SET_FEATURE Endpoint0 request is received, or if a request to be processed by FW is received due to the CPUDEC interrupt request, the HALT0 bit is masked and cleared to 0, until the next SETUP token is received. The HALTn bit is not cleared to 0 until Endpoint n receives the CLEAR_FEATURE Endpoint request, Halt Feature is cleared by the SET_INTERFACE or SET_CONFIGURATION request to the interface to which the endpoint is linked, or Halt Feature is cleared by FW. When the SET_INTERFACE or SET_CONFIGURATION request is correctly processed, the Halt Feature of all the target endpoints, except Endpoint0, is cleared after the request has been processed, even if the wValue is the same as the currently set value, and these bits are also cleared to 0. Halt Feature of Endpoint0 cannot be cleared if it is set because the STALL response is made in response to the SET_INTERFACE and SET_CONFIGURATION requests. Remark n = 0 to 4, 7, 8 User's Manual U16031EJ4V1UD 603 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (11) UF0 INT status 0 register (UF0IS0) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB0B) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC0 register. (1/2) 7 6 5 0 4 SHORT 3 DMAED 2 SETRQ 1 CLRRQ 0 EPHALT Address FFFFFE10H After reset 00H UF0IS0 BUSRST RSUSPD Bit position 7 Bit name BUSRST Function This bit indicates that Bus Reset has occurred. 1: Bus Reset has occurred (interrupt request is generated). 0: Not Bus Reset status (default value) 6 RSUSPD This bit indicates that the Resume or Suspend status has occurred. Reference bit 7 of the UF0EPS1 register by FW. 1: Resume or Suspend status has occurred (interrupt request is generated). 0: Resume or Suspend status has not occurred (default value). 4 SHORT This bit indicates that data is read from the FIFO of either the UF0BO1 or UF0BO2 register and that the USBSPnB signal (n = 2, 4) is active. It is valid only when the FIFO is full in the DMA mode. 1: USBSPnB signal is active (interrupt request is generated). 0: USBSPnB signal is not active (default value). Identify on which endpoint the operation is performed, by using the UF0DMS1 register. This bit is not automatically cleared to 0 even when the UF0DMS1 register is read by FW. 604 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 3 Bit name DMAED Function This bit indicates that the DMA end (TC) signal for Endpoint n (n = 1 to 4, 7, 8) is active. 1: DMA end signal for Endpoint n has been input (interrupt request is generated). 0: DMA end signal for Endpoint n has not been input (default value). When this bit is set to 1, the DMA request signal for Endpoint n becomes inactive. The DMA request signal for Endpoint n does not become active unless FW enables DMA transfer. Use the UF0DMS0 register to confirm on which endpoint the operation is actually performed. However, this bit is not automatically cleared to 0 even if the UF0DMS0 register is read by FW. 2 SETRQ This bit indicates that the SET_XXXX request to be automatically processed has been received and automatically processed (XXXX = CONFIGURATION or FEATURE). 1: SET_XXXX request to be automatically processed has been received (interrupt request is generated). 0: SET_XXXX request to be automatically processed has not been received (default value). This bit is set to 1 after completion of the status stage. Reference the UF0SET register to identify what is the target of the request. This bit is not automatically cleared to 0 even if the UF0SET register is read by FW. The EPHALT bit is also set to 1 when the SET_FEATURE Endpoint request has been received. 1 CLRRQ This bit indicates that the CLEAR_FEATURE request has been received and automatically processed. 1: CLEAR_FEATURE request has been received (interrupt request is generated). 0: CLEAR_FEATURE request has not been received (default value). This bit is set to 1 after completion of the status stage. Reference the UF0CLR register to identify what is the target of the request. This bit is not automatically cleared to 0 even if the UF0CLR register is read by FW. 0 EPHALT This bit indicates that an endpoint has stalled. 1: Endpoint has stalled (interrupt request is generated). 0: Endpoint has not stalled (default value). This bit is also set to 1 when an endpoint has stalled by setting FW. Identify the endpoint that has stalled, by referencing the UF0EPS2 register. This bit is not automatically cleared to 0 even when the CLEAR_FEATURE Endpoint, SET_INTERFACE, or SET_CONFIGURATION request is received. It is not automatically cleared to 0, either, if the next SETUP token is received in case of overrun of Endpoint0. Caution Even if Halt Feature of Endpoint0 is set and this interrupt request is generated, bit 0 of the UF0EPS2 register is masked and cleared to 0 between when a SET_FEATURE Endpoint0, CLEAR_FEATURE Endpoint0, or GET_STATUS Endpoint0 request, or FW-processed request is received and when a SETUP token other than the above is received. User's Manual U16031EJ4V1UD 605 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (12) UF0 INT status 1 register (UF0IS1) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB0B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB0B) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC1 register. However, the SUCES and STG bits of the UF0IS1 register are automatically cleared to 0 when the next SETUP token has been received. (1/2) 7 UF0IS1 0 6 E0IN 5 E0INDT 4 E0ODT 3 SUCES 2 STG 1 PROT 0 CPU DEC Address FFFFFE11H After reset 00H Bit position 6 Bit name E0IN Function This bit indicates that an IN token for Endpoint0 has been received and that the hardware has automatically transmitted NAK. 1: IN token is received and NAK is transmitted (interrupt request is generated). 0: IN token is not received (default value). 5 E0INDT This bit indicates that data has been correctly transmitted from the UF0E0W register. 1: Transmission from UF0E0W register is completed (interrupt request is generated). 0: Transmission from UF0E0W register is not completed (default value). Data is transmitted in synchronization with the IN token next to the one that set the EP0NKW bit of the UF0E0N register to 1. This bit is automatically set to 1 by hardware when the host correctly receives that data. It is also set to 1 even if the data is a Null packet. This bit is automatically cleared to 0 by hardware when the first write access is made to the UF0E0W register. 4 E0ODT This bit indicates that data has been correctly received in the UF0E0R register. 1: Data is in UF0E0R register (interrupt request is generated). 0: Data is not in UF0E0R register (default value). This bit is automatically set to 1 by hardware when data has been correctly received. At the same time, bit 0 of the UF0EPS0 register is also set to 1. If a Null packet has been received, this bit is not set to 1. It is automatically cleared to 0 by hardware when the FW reads the UF0E0R register and the value of the UF0E0L register becomes 0. 3 SUCES This bit indicates that either an FW-processed or hardware-processed request has been received and that the status stage has been correctly completed. 1: Control transfer has been correctly processed (interrupt request is generated). 0: Control transfer has not been processed correctly (default value). This bit is set to 1 upon completion of the status stage. It is automatically cleared to 0 by hardware when the next SETUP token is received. This bit is also set to 1 when data with Data PID of 0 (Null data) is received in the status stage of control transfer. 606 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 2 Bit name STG Function This bit is set to 1 when the stage of control transfer has changed to the status stage. It is valid for both FW-processed and hardware-processed requests. This bit is also set to 1 when the stage of control transfer (without data) has changed to the status stage. 1: Status stage (interrupt request is generated) 0: Not status stage (default value) This bit is automatically cleared to 0 by hardware when the next SETUP token is received. It is also set to 1 when the stage of control transfer has changed to the status stage while ACK cannot be correctly received in the data stage. In this case, the EP0NKW bit of the UF0E0N register is also cleared to 0 as soon as the UF0E0W register has been cleared, if the FW is processing control transfer (read). 1 PROT This bit indicates that a SETUP token has been received. It is valid for both FWprocessed and hardware-processed requests. 1: SETUP token is correctly received (interrupt request is generated). 0: SETUP token is not received (default value). This bit is set to 1 when data has been correctly received in the UF0E0ST register. Clear this bit to 0 by FW when the first read access is made to the UF0E0ST register. If it is not cleared to 0 by FW, reception of the next SETUP token cannot be correctly recognized. This bit is used to accurately recognize that a SETUP transaction has been executed again during control transfer. If the SETUP transaction is re-executed during control transfer and if a second request is executed by hardware, the CPUDEC bit is not set to 1, but the PROT bit can be used for recognition of the re-execution. 0 CPUDEC This bit indicates that the UF0E0ST register has a request that is to be decoded by FW. 1: Data is in UF0E0ST register (interrupt request is generated). 0: Data is not in UF0E0ST register (default value). This bit is automatically cleared to 0 by hardware when all the data of the UF0E0ST register is read. User's Manual U16031EJ4V1UD 607 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (13) UF0 INT status 2 register (UF0IS2) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB1B) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC2 register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7, 8) and the current setting of the interface. 7 UF0IS2 BKI2IN 6 BKI2DT 5 BKI1IN 4 BKI1DT 3 0 2 0 1 IT2DT 0 IT1DT Address FFFFFE12H After reset 00H Bit position 7, 5 Bit name BKInIN Function These bits indicate that an IN token has been received in the UF0BIn register (Endpoint m) and that NAK has been returned. 1: IN token is received and NAK is transmitted (interrupt request is generated). 0: IN token is not received (default value). 6, 4 BKInDT These bits indicate that the FIFO of the UF0BIn register (Endpoint m) has been toggled. This means that data can be written to Endpoint m. 1: FIFO has been toggled (interrupt request is generated). 0: FIFO has not been toggled (default value). The data written to Endpoint m is transmitted in synchronization with the IN token next to the one that set the BKInNK bit of the UF0EN register to 1. When the FIFO has been toggled and then data can be written from the CPU, this bit is automatically set to 1 by hardware. It is also set to 1 when the FIFO has been toggled, even if the data is a Null packet. This bit is automatically cleared to 0 by hardware when the first write access is made to the UF0BIn register. 1, 0 ITnDT These bits indicate that data has been correctly received from the UF0INTn register (Endpoint x). 1: Transmission is completed (interrupt request is generated). 0: Transmission is not completed (default value). Data is transmitted in synchronization with the IN token next to the one that set the ITnNK bit of the UF0EN register to 1. This bit is automatically set to 1 by hardware when the host has correctly received that data. It is automatically cleared to 0 by hardware when the first write access is made to the UF0INTn register. This bit is also set to 1 even when the data is a Null packet. Remark n = 1, 2 m = 1 and x = 7 where n = 1 m = 3 and x = 8 where n = 2 608 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (14) UF0 INT status 3 register (UF0IS3) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB1B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB1B) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC3 register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. (1/2) 7 UF0IS3 6 5 BKO2 NAK 4 3 2 1 BKO1 NAK 0 BKO1DT Address FFFFFE13H After reset 00H BKO2FL BKO2NL BKO2DT BKO1FL BKO1NL Bit position 7, 3 Bit name BKOnFL Function These bits indicate that data has been correctly received in the UF0BOn register (Endpoint m) and that both the FIFOs of the CPU and SIE hold the data. 1: Received data is in both the FIFOs of the UF0BOn register (interrupt request is generated). 0: Received data is not in the FIFO on the SIE side of the UF0BOn register (default value). If data is held in both the FIFOs of the CPU and SIE, these bits are automatically set to 1 by hardware. They are automatically cleared to 0 by hardware when the FIFO is toggled. 6, 2 BKOnNL These bits indicate that a Null packet (packet with a length of 0) has been received in the UF0BOn register (Endpoint m). 1: Null packet is received (interrupt request is generated). 0: Null packet is not received (default value). These bits are set to 1 immediately after reception of a Null packet when the FIFO is empty. They are set to 1 when the FIFO on the CPU side has been completely read if data is in that FIFO. 5, 1 BKOnNAK These bits indicate that an OUT token has been received to the UF0BOn register (Endpoint m) and that NAK has been returned. 1: OUT token is received and NAK is transmitted (interrupt request is generated). 0: OUT token is not received (default value). Remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 User's Manual U16031EJ4V1UD 609 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 4, 0 Bit name BKOnDT Function These bits indicate that data has been correctly received in the UF0BOn register (Endpoint m). 1: Reception has been completed correctly (interrupt request is generated). 0: Reception has not been completed (default value). These bits are automatically set to 1 by hardware when data has been correctly received and the FIFO has been toggled. At the same time, the corresponding bits of the UF0EPS0 register are also set to 1. They are not set to 1 when the data is a Null packet. These bits are automatically cleared to 0 by hardware when the value of the UF0BOnL register becomes 0 as a result of reading the UF0BOn register by FW. These bits are automatically cleared to 0 when all the contents of the FIFO on the CPU side have been read. However, the interrupt request is not cleared if data is in the FIFO on the SIE side at this time, and the INTUSB1B signal does not become inactive. The signal is kept active if data is successively received. Remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 610 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (15) UF0 INT status 4 register (UF0IS4) This register indicates the interrupt source. If the contents of this register are changed, the INTUSB2B signal becomes active. This register is read-only, in 8-bit units. If an interrupt request (INTUSB2B) is generated from USBF, the FW must read this register to identify the interrupt source. Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC4 register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7, 8) and the current setting of the interface. 7 UF0IS4 0 6 0 5 SETINT 4 0 3 0 2 0 1 0 0 0 Address FFFFFE14H After reset 00H Bit position 5 Bit name SETINT Function This bit indicates that the SET_INTERFACE request has been received and automatically processed. 1: The request has been automatically processed (interrupt request is generated). 0: The request has not been automatically processed (default value). The current setting of this bit can be identified by reading the UF0ASS or UF0IFn register (n = 0 to 4). User's Manual U16031EJ4V1UD 611 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (16) UF0 INT mask 0 register (UF0IM0) This register controls masking of the interrupt sources indicated by the UF0IS0 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSB0B) by writing 1 to the corresponding bit of this register. 7 UF0IM0 BUS RSTM 6 RSU SPDM 5 0 4 SHORTM 3 DMA EDM 2 SET RQM 1 CLR RQM 0 EP HALTM Address FFFFFE17H After reset 00H Bit position 7 Bit name BUSRSTM This bit masks the Bus Reset interrupt. 1: Mask 0: Do not mask (default value) Function 6 RSUSPDM This bit masks the Resume/Suspend interrupt. 1: Mask 0: Do not mask (default value) 4 SHORTM This bit masks the Short interrupt. 1: Mask 0: Do not mask (default value) 3 DMAEDM This bit masks the DMA_END interrupt. 1: Mask 0: Do not mask (default value) 2 SETRQM This bit masks the SET_RQ interrupt. 1: Mask 0: Do not mask (default value) 1 CLRRQM This bit masks the CLR_RQ interrupt. 1: Mask 0: Do not mask (default value) 0 EPHALTM This bit masks the EP_Halt interrupt. 1: Mask 0: Do not mask (default value) 612 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (17) UF0 INT mask 1 register (UF0IM1) This register controls masking of the interrupt sources indicated by the UF0IS1 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSB0B) by writing 1 to the corresponding bit of this register. 7 UF0IM1 0 6 E0INM 5 E0 INDTM 4 E0 ODTM 3 SUCESM 2 STGM 1 PROTM 0 CPU DECM Address FFFFFE18H After reset 00H Bit position 6 Bit name E0INM This bit masks the EP0IN interrupt. 1: Mask 0: Do not mask (default value) Function 5 E0INDTM This bit masks the EP0INDT interrupt. 1: Mask 0: Do not mask (default value) 4 E0ODTM This bit masks the EP0OUTDT interrupt. 1: Mask 0: Do not mask (default value) 3 SUCESM This bit masks the Success interrupt. 1: Mask 0: Do not mask (default value) 2 STGM This bit masks the Stg interrupt. 1: Mask 0: Do not mask (default value) 1 PROTM This bit masks the Protect interrupt. 1: Mask 0: Do not mask (default value) 0 CPUDECM This bit masks the CPUDEC interrupt. 1: Mask 0: Do not mask (default value) User's Manual U16031EJ4V1UD 613 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (18) UF0 INT mask 2 register (UF0IM2) This register controls masking of the interrupt sources indicated by the UF0IS2 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSB1B) by writing 1 to the corresponding bit of this register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7, 8) and the current setting of the interface. 7 UF0IM2 BKI2INM 6 BKI2 DTM 5 BKI1INM 4 BKI1 DTM 3 0 2 0 1 IT2DTM 0 IT1DTM Address FFFFFE19H After reset 00H Bit position 7, 5 Bit name BKInINM These bits mask the BLKInIN interrupt. 1: Mask 0: Do not mask (default value) Function 6, 4 BKInDTM These bits mask the BLKInDT interrupt. 1: Mask 0: Do not mask (default value) 1, 0 ITnDTM These bits mask the INTnDT interrupt. 1: Mask 0: Do not mask (default value) Remark n = 1, 2 614 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (19) UF0 INT mask 3 register (UF0IM3) This register controls masking of the interrupt sources indicated by the UF0IS3 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSB1B) by writing 1 to the corresponding bit of this register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. 7 UF0IM3 BKO2 FLM 6 BKO2 NLM 5 BKO2 NAKM 4 BKO2 DTM 3 BKO1 FLM 2 BKO1 NLM 1 BKO1 NAKM 0 BKO1 DTM Address FFFFFE1AH After reset 00H Bit position 7, 3 Bit name BKOnFLM Function These bits mask the BLKOnFL interrupt. 1: Mask 0: Do not mask (default value) 6, 2 BKOnNLM These bits mask the BLKOnNL interrupt. 1: Mask 0: Do not mask (default value) 5, 1 BKOnNAKM These bits mask the BLKOnNK interrupt. 1: Mask 0: Do not mask (default value) 4, 0 BKOnDTM These bits mask the BLKOnDT interrupt. 1: Mask 0: Do not mask (default value) Remark n = 1, 2 User's Manual U16031EJ4V1UD 615 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (20) UF0 INT mask 4 register (UF0IM4) This register controls masking of the interrupt sources indicated by the UF0IS4 register. This register can be read or written in 8-bit units. FW can mask occurrence of an interrupt request from USBF (INTUSB2B) by writing 1 to the corresponding bit of this register. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7, 8) and the current setting of the interface. 7 UF0IM4 0 6 0 5 SETINTM 4 0 3 0 2 0 1 0 0 0 Address FFFFFE1BH After reset 00H Bit position 5 Bit name SETINTM This bit masks the SET_INT interrupt. 1: Mask 0: Do not mask (default value) Function 616 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (21) UF0 INT clear 0 register (UF0IC0) This register controls clearing the interrupt sources indicated by the UF0IS0 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. 7 UF0IC0 BUS RSTC 6 RSU SPDC 5 1 4 SHORTC 3 DMA EDC 2 SET RQC 1 CLR RQC 0 EP HALTC Address FFFFFE1EH After reset FFH Bit position 7 Bit name BUSRSTC This bit clears the Bus Reset interrupt. 0: Clear Function 6 RSUSPDC This bit clears the Resume/Suspend interrupt. 0: Clear 4 SHORTC This bit clears the Short interrupt. 0: Clear 3 DMAEDC This bit clears the DMA_END interrupt. 0: Clear 2 SETRQC This bit clears the SET_RQ interrupt. 0: Clear 1 CLRRQC This bit clears the CLR_RQ interrupt. 0: Clear 0 EPHALTC This bit clears the EP_Halt interrupt. 0: Clear User's Manual U16031EJ4V1UD 617 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (22) UF0 INT clear 1 register (UF0IC1) This register controls clearing the interrupt sources indicated by the UF0IS1 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. 7 UF0IC1 1 6 E0INC 5 E0 INDTC 4 3 2 STGC 1 PROTC 0 CPU DECC Address FFFFFE1FH After reset FFH E0ODTC SUCESC Bit position 6 Bit name E0INC This bit clears the EP0IN interrupt. 0: Clear This bit clears the EP0INDT interrupt. 0: Clear Function 5 E0INDTC 4 E0ODTC This bit clears the EP0OUTDT interrupt. 0: Clear 3 SUCESC This bit clears the Success interrupt. 0: Clear 2 STGC This bit clears the Stg interrupt. 0: Clear 1 PROTC This bit clears the Protect interrupt. 0: Clear 0 CPUDECC This bit clears the CPUDEC interrupt. 0: Clear 618 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (23) UF0 INT clear 2 register (UF0IC2) This register controls clearing the interrupt sources indicated by the UF0IS2 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7, 8) and the current setting of the interface. 7 UF0IC2 BKI2INC 6 BKI2 DTC 5 BKI1INC 4 BKI1 DTC 3 1 2 1 1 IT2DTC 0 IT1DTC Address FFFFFE20H After reset FFH Bit position 7, 5 Bit name BKInINC These bits clear the BLKInIN interrupt. 0: Clear Function 6, 4 BKInDTC These bits clear the BLKInDT interrupt. 0: Clear These bits clear the INTnDT interrupt. 0: Clear 1, 0 ITnDTC Remark n = 1, 2 User's Manual U16031EJ4V1UD 619 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (24) UF0 INT clear 3 register (UF0IC3) This register controls clearing the interrupt sources indicated by the UF0IS3 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. 7 UF0IC3 BKO2 FLC 6 BKO2 NLC 5 BKO2 NAKC 4 BKO2 DTC 3 BKO1 FLC 2 BKO1 NLC 1 BKO1 NAKC 0 BKO1 DTC Address FFFFFE21H After reset FFH Bit position 7, 3 Bit name BKOnFLC These bits clear the BLKOnFL interrupt. 0: Clear Function 6, 2 BKOnNLC These bits clear the BLKOnNL interrupt. 0: Clear These bits clear the BLKOnNK interrupt. 0: Clear These bits clear the BLKOnDT interrupt. 0: Clear 5, 1 BKOnNAKC 4, 0 BKOnDTC Remark n = 1, 2 620 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (25) UF0 INT clear 4 register (UF0IC4) This register controls clearing the interrupt sources indicated by the UF0IS4 register. This register is write-only, in 8-bit units. If this register is read, the value FFH is read. FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of this register automatically sets the bit to 1. Writing 1 is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7, 8) and the current setting of the interface. 7 UF0IC4 1 6 1 5 SETINTC 4 1 3 1 2 1 1 1 0 1 Address FFFFFE22H After reset FFH Bit position 5 Bit name SETINTC This bit clears the SET_INT interrupt. 0: Clear Function User's Manual U16031EJ4V1UD 621 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (26) UF0 INT & DMARQ register (UF0IDR) This register selects reporting via an interrupt request or starting DMA. This register can be read or written in 8-bit units. If data exists in either the UF0BO1 or UF0BO1 register, or if data can be written to the UF0BI1 or UF0BI2 register, this register selects whether it is reported to the FW by an interrupt request, or whether starting DMA is requested. If starting DMA is requested, the DMA transfer mode can be selected according to the setting of bits 0 and 1. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface. Be sure to clear bits 3 and 2 to 0. If they are set to 1, the operation is not guaranteed. Caution If the target endpoint is not supported by the SET_INTERFACE request under DMA transfer, the DMA request signal becomes inactive immediately, and the corresponding bit is automatically cleared to 0 by hardware. (1/2) 7 UF0IDR DQBI2 MS 6 DQBI1 MS 5 DQBO2 MS 4 DQBO1 MS 3 0 2 0 1 MODE1 0 MODE0 Address FFFFFE26H After reset 00H Bit position 7, 6 Bit name DQBInMS Function These bits enable (mask) a write DMA transfer request (DMA request signal for Endpoint m) to the UF0BIn register. When these bits are set to 1, the DMA request signal for Endpoint m becomes active while writing data can be acknowledged. If the DMA end signal for Endpoint m is input (if the DMA controller issues TC), these bits are automatically cleared to 0 by hardware. To continue DMA transfer, re-set these bits to 1 by FW. 1: Enables active DMA request signal for Endpoint m (masks BKInDT interrupt). 0: Disables active DMA request signal for Endpoint m (default value). 5, 4 DQBOnMS These bits enable (mask) a read DMA transfer request (DMA request signal for Endpoint x) to the UF0BOn register. When these bits are set to 1, the DMA request signal for Endpoint x becomes active if the data to be read is prepared in the UF0BOn register. If the DMA end signal for Endpoint x is input (if the DMA controller issues TC), these bits are automatically cleared to 0 by hardware. They are also cleared to 0 when the USBSPxB signal is active. To continue DMA transfer, re-set these bits to 1 by FW. 1: Enables active DMA request signal for Endpoint x (masks BKOnDT interrupt). 0: Disables active DMA request signal for Endpoint x (default value). Remark n = 1, 2 m = 1 and x = 2 where n = 1 m = 3 and x = 4 where n = 2 622 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 1, 0 Bit name MODE1, MODE0 Function These bits select the DMA transfer mode. MODE1 1 MODE2 1 Mode Setting prohibited Demand mode Remark Operation cannot be guaranteed. 1 0 DMA request signal becomes active as long as there is data. It becomes inactive if there is no more data. DMA request signal becomes inactive each time DMA transfer has been executed. 0 X Single mode Remark X: Don't care User's Manual U16031EJ4V1UD 623 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (27) UF0 DMA status 0 register (UF0DMS0) This register indicates the DMA status of Endpoint1 to Endpoint4. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface. 7 UF0DMS0 0 6 0 5 DQE4 4 DQE3 3 DQE2 2 DQE1 1 0 0 0 Address FFFFFE27H After reset 00H Bit position 5 Bit name DQE4 Function This bit indicates that a DMA read request is being issued from Endpoint4 to memory. 1: DMA read request from Endpoint4 is being issued. 0: DMA read request from Endpoint4 is not being issued (default value). 4 DQE3 This bit indicates that a DMA write request is being issued from memory to Endpoint3. Note that, even if data is in Endpoint3 (when the FIFO is not full and after the BKI2DED bit has been set to 1), the DMA request signal becomes active immediately and DMA transfer is started when the DQBI2MS bit of the UF0IDR register is set to 1. 1: DMA write request for Endpoint3 is being issued. 0: DMA write request for Endpoint3 is not being issued (default value). 3 DQE2 This bit indicates that a DMA read request is being issued from Endpoint2 to memory. 1: DMA read request from Endpoint2 is being issued. 0: DMA read request from Endpoint2 is not being issued (default value). 2 DQE1 This bit indicates that a DMA write request is being issued from memory to Endpoint1. Note that, even if data is in Endpoint1 (when the FIFO is not full and after the BKI1DED bit has been set to 1), the DMA request signal becomes active immediately and DMA transfer is started when the DQBI1MS bit of the UF0IDR register is set to 1. 1: DMA write request for Endpoint1 is being issued. 0: DMA write request for Endpoint1 is not being issued (default value). 624 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (28) UF0 DMA status 1 register (UF0DMS1) This register indicates the DMA status of Endpoint1 to Endpoint4. This register is read-only, in 8-bit units. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4) and the current setting of the interface. Each bit is automatically cleared to 0 when this register is read. Even when this register is read, however, bits 4 and 3 of the UF0IS0 register are not cleared to 0. If the target endpoint is no longer supported by the SET_INTERFACE request, each bit is automatically cleared to 0 by hardware (however, the DMA_END interrupt request and Short interrupt request are not cleared). 7 UF0DMS1 DEDE4 6 DSPE4 5 DEDE3 4 DEDE2 3 DSPE2 2 DEDE1 1 0 0 0 Address FFFFFE28H After reset 00H Bit position 7, 5, 4, 2 Bit name DEDEn Function These bits indicate that the DMA end (TC) signal for Endpoint n becomes active and DMA is stopped while a DMA read request is being issued from Endpoint n to memory. 1: DMA end signal for Endpoint n is active. 0: DMA end signal for Endpoint n is inactive (default value). 6, 3 DSPEm These bits indicate that, although a DMA read request was being issued from Endpoint m to memory, DMA has been stopped because the received data is a short packet and there is no more data to be transferred. 1: USBSPmB signal is active. 0: USBSPmB signal is inactive (default value). Remark n = 1 to 4 m = 2, 4 User's Manual U16031EJ4V1UD 625 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (29) UF0 FIFO clear 0 register (UF0FIC0) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7, 8) and the current setting of the interface. 7 UF0FIC0 BKI2SC 6 BKI2CC 5 BKI1SC 4 BKI1CC 3 ITR2C 2 ITR1C 1 EP0WC 0 EP0RC Address FFFFFE30H After reset 00H Bit position 7, 5 Bit name BKInSC Function These bits clear only the FIFO on the SIE side of the UF0BIn register (reset the counter). 1: Clear Writing these bits is invalid while an IN token for Endpoint m is being processed with the BKInNK bit set to 1. The BKInNK bit is automatically cleared to 0 by clearing the FIFO. Make sure that the FIFO on the CPU side is empty when these bits are used. 6, 4 BKInCC These bits clear only the FIFO on the CPU side of the UF0BIn register (reset the counter). 1: Clear 3, 2 ITRnC These bits clear the UF0INTn register (reset the counter). 1: Clear Writing these bits is invalid while an IN token for Endpoint x is being processed with the ITnNK bit set to 1. The ITnNK bit is automatically cleared to 0 by clearing the FIFO. 1 EP0WC This bit clears the UF0E0W register (resets the counter). 1: Clear Writing this bit is invalid while an IN token for Endpoint0 is being processed with the EP0NKW bit set to 1. The EP0NKW bit is automatically cleared to 0 by clearing the FIFO. 0 EP0RC This bit clears the UF0E0R register (resets the counter). 1: Clear When the EP0NKR bit is set to 1 (except when it has been set by FW), the EP0NKR bit is automatically cleared to 0 by clearing the FIFO. Remark n = 1, 2 m = 1 and x = 7 where n = 1 m = 3 and x = 8 where n = 2 626 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (30) UF0 FIFO clear 1 register (UF0FIC1) This register clears each FIFO. This register is write-only, in 8-bit units. If this register is read, 00H is read. FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4) and the current setting of the interface. 7 UF0FIC1 0 6 0 5 0 4 0 3 BKO2C 2 BKO2CC 1 BKO1C 0 BKO1CC Address FFFFFE31H After reset 00H Bit position 3, 1 Bit name BKOnC Function These bits clear the FIFOs on both the SIE and CPU sides of the UF0BOn register (reset the counter). 1: Clear When the BKOnNK bit is set to 1 (except when it has been set by FW), the BKOnNK bit is automatically cleared to 0 by clearing the FIFO. 2, 0 BKOnCC These bits clear only the FIFO on the CPU side of the UF0BOn register (reset the counter). 1: Clear When the BKOnNK bit is set to 1 (except when it has been set by FW), the BKOnNK bit is automatically cleared to 0 by clearing the FIFO. Remark n = 1, 2 User's Manual U16031EJ4V1UD 627 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (31) UF0 data end register (UF0DEND) This register reports the end of writing to the transmission system. This register is write-only, in 8-bit units (however, bits 7 and 6 can be read and written). If this register is read, 00H is read. FW can start data transfer of the target endpoint by writing 1 to the corresponding bit of this register. The bit to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid. The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7, 8) and the current setting of the interface. (1/2) 7 UF0DEND BKI2T 6 BKI1T 5 0 4 3 2 1 0 Address FFFFFE35H After reset 00H IT2DEND IT1DEND BKI2DED BKI1DED E0DED Bit position 7, 6 Bit name BKInT Function These bits specify whether toggling the FIFO is automatically executed if the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA. 1: Automatically execute a toggle operation of the FIFO as soon as the FIFO has become full. 0: Do not automatically execute a toggle operation of the FIFO even if the FIFO becomes full (default value). 4, 3 ITnDEND Set these bits to 1 to transmit the data of the UF0INTn register. When these bits are set to 1, the ITnNK bit is set to 1 and data transfer is executed. 1: Transmit a short packet. 0: Do not transmit a short packet (default value). If the ITRnC bit of the UF0FIC0 register is set to 1 and then these bits are set to 1 (counter of UF0INTn register = 0 and the corresponding bit of the UF0EPS0 register = 1), a Null packet (with a data length of 0) is transmitted. If data exists in the UF0INTn register and if these bits are set to 1 (counter of UF0INTn register 0 and the corresponding bit of the UF0EPS0 register = 1), a short packet is transmitted. These bits are automatically controlled by hardware when the FIFO is full. Remark n = 1, 2 628 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2/2) Bit position 2, 1 Bit name BKInDED Function Set these bits to 1 when writing transmit data to the UF0BIn register has been completed. When these bits are set to 1, the FIFO is toggled as soon as possible, the BKInNK bit is set to 1, and data is transferred. 1: Transmit a short packet. 0: Do not transmit a short packet (default value). These bits control the FIFO on the CPU side. If the BKInCC bit of the UF0FIC0 register is set to 1 and then these bits are set to 1 (counter of UF0BIn register = 0), a Null packet (with a data length of 0) is transmitted. If data exists in the UF0BIn register and if these bits are set to 1 (counter of UF0BIn register 0), and if the FIFO is not full, a short packet is transmitted. If the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA, with the PIO or BKInT bit set to 1, the hardware starts data transmission even if these bits are not set to 1. If the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA, with the BKInT bit cleared to 0, be sure to set these bits to 1 (see 11.4.1 (3) UF0 EPNAK register (UF0EN)). 0 E0DED Set this bit to 1 to transmit data of the UF0E0W register. When this bit is set to 1, the EP0NKW bit is set to 1 and data is transferred. 1: Transmit a short packet. 0: Do not transmit a short packet (default value). If the EP0WC bit of the UF0FIC0 register is set to 1 and if this bit is set to 1 (counter of UF0E0W register = 0 and bit 1 of UF0EPS0 register = 1), a Null packet (with a data length of 0) is transmitted. If data exists in the UF0E0W register and if this bit is set to 1 (counter of UF0E0W register 0 and bit 1 of the UF0EPS0 register = 1), and if the FIFO is not full, a short packet is transmitted. Remark n = 1, 2 User's Manual U16031EJ4V1UD 629 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (32) UF0 GPR register (UF0GPR) This register controls USBF and the USB interface. This register is write-only, in 8-bit units. If this register is read, 00H is read. Be sure to clear bits 7 to 1 to 0. FW can reset the USBF by writing 1 to bit 0 of this register. This bit is automatically cleared to 0 after 1 has been written to it. Writing 0 to this bit is invalid. 7 UF0GPR 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MRST Address FFFFFE37H After reset 00H Bit position 0 Bit name MRST Set this bit to 1 to reset USBF. 1: Reset Function Actually, USBF is reset two USB clocks after this bit has been set to 1 by FW and the write signal has become inactive. Resetting USBF by the MRST bit while the system clock is operating has the same result as resetting by the RESET pin (hardware reset) (register value back to default value). However, the UF0CS and UF0BC registers are not reset by the MRST bit. 630 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (33) UF0 mode control register (UF0MODC) This register controls CPUDEC processing. This register can be read or written in 8-bit units. By setting each bit of this register, the setting of the UF0MODS register can be changed. The bit of this register is automatically cleared to 0 only at hardware reset and when the MRST bit of the UF0GRP register has been set to 1. Even if the bit of this register has automatically been set to 1 by hardware, the setting by FW takes precedence. Be sure to clear bits 7 and 5 to 2 to 0. If they are set to 1, the operation is not guaranteed. Caution This register is provided for debugging purposes. Usually, do not set this register except for verifying the operation or when a special mode is used. 7 UF0MODC 0 6 CDC GDST 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFFE3AH After reset 00H Bit position 6 Bit name CDCGDST Function Set this bit to 1 to switch the GET_DESCRIPTOR Configuration request to CPUDEC processing. By setting this bit to 1, the CDCGD bit of the UF0MODS register can be forcibly set to 1. 1: Forcibly change the GET_DESCRIPTOR Configuration request to CPUDEC processing (sets the CDCGD bit of the UF0MODS register to 1). 0: Automatically process the GET_DESCRIPTOR Configuration request (default value). User's Manual U16031EJ4V1UD 631 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (34) UF0 mode status register (UF0MODS) This register indicates the configuration status. This register is read-only, in 8-bit units. 7 UF0MODS 0 6 CDCGD 5 0 4 MPACK 3 DFLT 2 CONF 1 0 0 0 Address FFFFFE3CH After reset 00H Bit position 6 Bit name CDCGD Function This bit specifies whether CPUDEC processing is performed for the GET_DESCRIPTOR Configuration request. 1: Forcibly change the GET_DESCRIPTOR Configuration request to CPUDEC processing. 0: Automatically process the GET_DESCRIPTOR Configuration request (default value). 4 MPACK This bit indicates the transmit packet size of Endpoint0. 1: Transmit a packet of other than 8 bytes. 0: Transmit a packet of 8 bytes (default value). This bit is automatically set to 1 by hardware after the GET_DESCRIPTOR Device request has been processed (on normal completion of the status stage). It is not cleared to 0 until the USBF has been reset (it is not cleared to 0 by Bus Reset). If this bit is not set to 1, the hardware transfers only the automatically-executed request in 8-byte units. Therefore, even if data of more than 8 bytes is sent by the OUT token to be processed by FW before completion of the GET_DESCRIPTOR Device request, the data is correctly received. This bit is ignored if the size of Endpoint0 is 8 bytes. 3 DFLT This bit indicates the default status (DFLT bit = 1). 1: Enables response. 0: Disables response (always no response) (default value). This bit is automatically set to 1 by Bus Reset. The transaction for all the endpoints is not responded to until this bit is set to 1. 2 CONF This bit indicates whether the SET_CONFIGURATION request has been completed. 1: SET_CONFIGURATION request has been completed. 0: SET_CONFIGURATION request has not been completed (default value). This bit is set to 1 when Configuration value = 1 is received by the SET_CONFIGURATION request. Unless this bit is set to 1, access to an endpoint other than Endpoint0 is ignored. This bit is cleared to 0 when Configuration value = 0 is received by the SET_CONFIGURATION request. It is also cleared to 0 when Bus Reset is detected. 632 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (35) UF0 active interface number register (UF0AIFN) This register sets the valid Interface number that correctly responds to the GET/SET_INTERFACE request. Because Interface 0 is always valid, Interfaces 1 to 4 can be selected. This register can be read or written in 8-bit units. 7 UF0AIFN ADDIF 6 0 5 0 4 0 3 0 2 0 1 IFNO1 0 IFNO0 Address FFFFFE40H After reset 00H Bit position 7 Bit name ADDIF Function This bit allows use of Interfaces numbered other than 0. 1: Support up to the Interface number specified by the IFNO1 and IFNO0 bits. 0: Support only Interface 0 (default value). Setting bits 1 and 0 of this register is invalid when this bit is not set to 1. 1, 0 IFNO1, IFNO0 These bits specify the range of Interface numbers to be supported. IFNO1 1 1 0 0 IFNO0 1 0 1 0 0, 1, 2, 3, 4 0, 1, 2, 3 0, 1, 2 0, 1 Valid Interface No. User's Manual U16031EJ4V1UD 633 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (36) UF0 active alternative setting register (UF0AAS) This register specifies a link between the Interface number and Alternative Setting. This register can be read or written in 8-bit units. USBF of the V850E/ME2 can set a five-series Alternative Setting (Alternate Setting 0, 1, 2, 3, and 4 can be defined) and a two-series Alternative Setting (Alternative Setting 0 and 1 can be defined) for one Interface. 7 UF0AAS ALT2 6 IFAL21 5 IFAL20 4 ALT2EN 3 ALT5 2 IFAL51 1 IFAL50 0 ALT5EN Address FFFFFE41H After reset 00H Bit position 7, 3 Bit name ALTn Function These bits specify whether an n-series Alternative Setting is linked with Interface 0. When these bits are set to 1, the setting of the IFALn1 and IFALn0 bits is invalid. 1: Link n-series Alternative Setting with Interface 0. 0: Do not link n-series Alternative Setting with Interface 0 (default value). 6, 5, 2, 1 IFALn1, IFALn0 These bits specify the Interface number to be linked with the n-series Alternative Setting. If the linked Interface number is outside the range specified by the UF0AIFN register, the n-series Alternative Setting is invalid (ALTnEN bit = 0). IFALn1 1 1 0 0 IFALn0 1 0 1 0 Interface number to be linked Links Interface 4. Links Interface 3. Links Interface 2. Links Interface 1. Do not link a five-series Alternative Setting and a two-series Alternative Setting with the same Interface number. 4, 0 ALTnEN These bits validate the n-series Alternative Setting. Unless these bits are set to 1, the setting of the ALTn, IFALn1, and IFALn0 bits is invalid. 1: Validate the n-series Alternative Setting. 0: Do not validate the n-series Alternative Setting (default value). Remark n = 2, 5 For example, when the UF0AIFN register is set to 82H and the UF0AAS register is set to 15H, Interfaces 0, 1, 2, and 3 are valid. Interfaces 0 and 2 support only Alternative Setting 0. Interface 1 supports Alternative Setting 0 and 1, and Interface 3 supports Alternative Setting 0, 1, 2, 3, and 4. With this setting, requests GET_INTERFACE wIndex = 0/1/2/3, SET_INTERFACE wValue = 0 & wIndex = 0/2, SET_INTERFACE wValue = 0/1 & wIndex = 1, and SET_INTERFACE wValue = 0/1/2/3/4 & wIndex = 3 are automatically responded to, and a STALL response is made to the other GET/SET_INTERFACE requests. 634 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (37) UF0 alternative setting status register (UF0ASS) This register indicates the current status of the Alternative Setting. This register is read-only, in 8-bit units. Check this register when the SET_INT interrupt request has been issued. The value received by the SET_INTERFACE request is reflected on the UF0IFn register (n = 0 to 4) as well as on this register. 7 UF0ASS 0 6 0 5 0 4 0 3 AL5ST3 2 AL5ST2 1 AL5ST1 0 AL2ST Address FFFFFE42H After reset 00H Bit position 3 to 1 Bit name AL5ST3 to AL5ST1 Function These bits indicate the current status of the five-series Alternative Setting. AL5ST3 1 0 0 0 0 AL5ST2 0 1 1 0 0 AL5ST1 0 1 0 1 0 Selected Alternative Setting number Alternative Setting 4 Alternative Setting 3 Alternative Setting 2 Alternative Setting 1 Alternative Setting 0 0 AL2ST This bit indicates the current status of the two-series Alternative Setting (selected Alternative Setting number). 1: Alternative Setting 1 0: Alternative Setting 0 User's Manual U16031EJ4V1UD 635 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (38) UF0 endpoint 1 interface mapping register (UF0E1IM) This register specifies for which Interface and Alternative Setting Endpoint1 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint1 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint1 request and the IN transaction to Endpoint1 are responded to, and whether the related bits are valid or invalid. 7 UF0E1IM E1EN2 6 E1EN1 5 E1EN0 4 E12AL1 3 E15AL4 2 E15AL3 1 E15AL2 0 E15AL1 Address FFFFFE43H After reset 00H Bit position 7 to 5 Bit name E1EN2 to E1EN0 Function These bits set a link between the Interface of Endpoint1 and the two-/five-series Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E1EN2 1 1 1 1 0 0 0 0 E1EN1 1 1 0 0 1 1 0 0 E1EN0 1 0 1 0 1 0 1 0 Linked with Interface 4 and Alternative Setting 0 Linked with Interface 3 and Alternative Setting 0 Linked with Interface 2 and Alternative Setting 0 Linked with Interface 1 and Alternative Setting 0 Linked with Interface 0 and Alternative Setting 0 Not linked with Interface (default value) Link status Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E12AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint1 is valid. 4 E12AL1 This bit validates Endpoint1 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E15AL4 to E15AL1 bits are 0000. 3 to 0 E15ALn These bits validate Endpoint1 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 636 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (39) UF0 endpoint 2 interface mapping register (UF0E2IM) This register specifies for which Interface and Alternative Setting Endpoint2 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint2 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint2 request and the OUT transaction to Endpoint2 are responded to, and whether the related bits are valid or invalid. 7 UF0E2IM E2EN2 6 E2EN1 5 E2EN0 4 E22AL1 3 E25AL4 2 E25AL3 1 E25AL2 0 E25AL1 Address FFFFFE44H After reset 00H Bit position 7 to 5 Bit name E2EN2 to E2EN0 Function These bits set a link between the Interface of Endpoint2 and the two-/five-series Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E2EN2 1 1 1 1 0 0 0 0 E2EN1 1 1 0 0 1 1 0 0 E2EN0 1 0 1 0 1 0 1 0 Linked with Interface 4 and Alternative Setting 0 Linked with Interface 3 and Alternative Setting 0 Linked with Interface 2 and Alternative Setting 0 Linked with Interface 1 and Alternative Setting 0 Linked with Interface 0 and Alternative Setting 0 Not linked with Interface (default value) Link status Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E22AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint2 is valid. 4 E22AL1 This bit validates Endpoint2 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E25AL4 to E25AL1 bits are 0000. 3 to 0 E25ALn These bits validate Endpoint2 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 User's Manual U16031EJ4V1UD 637 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (40) UF0 endpoint 3 interface mapping register (UF0E3IM) This register specifies for which Interface and Alternative Setting Endpoint3 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint3 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint3 request and the IN transaction to Endpoint3 are responded to, and whether the related bits are valid or invalid. 7 UF0E3IM E3EN2 6 E3EN1 5 E3EN0 4 E32AL1 3 E35AL4 2 E35AL3 1 E35AL2 0 E35AL1 Address FFFFFE45H After reset 00H Bit position 7 to 5 Bit name E3EN2 to E3EN0 Function These bits set a link between the Interface of Endpoint3 and the two-/five-series Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E3EN2 1 1 1 1 0 0 0 0 E3EN1 1 1 0 0 1 1 0 0 E3EN0 1 0 1 0 1 0 1 0 Linked with Interface 4 and Alternative Setting 0 Linked with Interface 3 and Alternative Setting 0 Linked with Interface 2 and Alternative Setting 0 Linked with Interface 1 and Alternative Setting 0 Linked with Interface 0 and Alternative Setting 0 Not linked with Interface (default value) Link status Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E32AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint3 is valid. 4 E32AL1 This bit validates Endpoint3 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E35AL4 to E35AL1 bits are 0000. 3 to 0 E35ALn These bits validate Endpoint3 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 638 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (41) UF0 endpoint 4 interface mapping register (UF0E4IM) This register specifies for which Interface and Alternative Setting Endpoint4 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint4 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint4 request and the OUT transaction to Endpoint4 are responded to, and whether the related bits are valid or invalid. 7 UF0E4IM E4EN2 6 E4EN1 5 E4EN0 4 E42AL1 3 E45AL4 2 E45AL3 1 E45AL2 0 E45AL1 Address FFFFFE46H After reset 00H Bit position 7 to 5 Bit name E4EN2 to E4EN0 Function These bits set a link between the Interface of Endpoint4 and the two-/five-series Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E4EN2 1 1 1 1 0 0 0 0 E4EN1 1 1 0 0 1 1 0 0 E4EN0 1 0 1 0 1 0 1 0 Linked with Interface 4 and Alternative Setting 0 Linked with Interface 3 and Alternative Setting 0 Linked with Interface 2 and Alternative Setting 0 Linked with Interface 1 and Alternative Setting 0 Linked with Interface 0 and Alternative Setting 0 Not linked with Interface (default value) Link status Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E42AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint4 is valid. 4 E42AL1 This bit validates Endpoint4 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E45AL4 to E45AL1 bits are 0000. 3 to 0 E45ALn These bits validate Endpoint4 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 User's Manual U16031EJ4V1UD 639 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (42) UF0 endpoint 7 interface mapping register (UF0E7IM) This register specifies for which Interface and Alternative Setting Endpoint7 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint7 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint7 request and the IN transaction to Endpoint7 are responded to, and whether the related bits are valid or invalid. 7 UF0E7IM E7EN2 6 E7EN1 5 E7EN0 4 E72AL1 3 E75AL4 2 E75AL3 1 E75AL2 0 E75AL1 Address FFFFFE49H After reset 00H Bit position 7 to 5 Bit name E7EN2 to E7EN0 Function These bits set a link between the Interface of Endpoint7 and the two-/five-series Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E7EN2 1 1 1 1 0 0 0 0 E7EN1 1 1 0 0 1 1 0 0 E7EN0 1 0 1 0 1 0 1 0 Linked with Interface 4 and Alternative Setting 0 Linked with Interface 3 and Alternative Setting 0 Linked with Interface 2 and Alternative Setting 0 Linked with Interface 1 and Alternative Setting 0 Linked with Interface 0 and Alternative Setting 0 Not linked with Interface (default value) Link status Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E72AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint7 is valid. 4 E72AL1 This bit validates Endpoint7 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E75AL4 to E75AL1 bits are 0000. 3 to 0 E75ALn These bits validate Endpoint7 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 640 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (43) UF0 endpoint 8 interface mapping register (UF0E8IM) This register specifies for which Interface and Alternative Setting Endpoint8 is valid. This register can be read or written in 8-bit units. The setting of this register and the Alternative Setting selected by the SET_INTERFACE request indicate whether Endpoint8 is currently valid, and the hardware determines how the GET_STATUS/CLEAR_FEATURE/SET_FEATURE Endpoint8 request and the IN transaction to Endpoint8 are responded to, and whether the related bits are valid or invalid. 7 UF0E8IM E8EN2 6 E8EN1 5 E8EN0 4 E82AL1 3 E85AL4 2 E85AL3 1 E85AL2 0 E85AL1 Address FFFFFE4AH After reset 00H Bit position 7 to 5 Bit name E8EN2 to E8EN0 Function These bits set a link between the Interface of Endpoint8 and the two-/five-series Alternative Setting. The endpoint is linked with Alternative Setting 0. The endpoint linked with Alternative Setting 0 cannot be excluded from Alternative Setting 1 to 4. E8EN2 1 1 1 1 0 0 0 0 E8EN1 1 1 0 0 1 1 0 0 E8EN0 1 0 1 0 1 0 1 0 Linked with Interface 4 and Alternative Setting 0 Linked with Interface 3 and Alternative Setting 0 Linked with Interface 2 and Alternative Setting 0 Linked with Interface 1 and Alternative Setting 0 Linked with Interface 0 and Alternative Setting 0 Not linked with Interface (default value) Link status Not linked with Interface When these bits are set to 110 or 111, they are invalid even if the E82AL1 bit is cleared to 0. If the endpoint is linked, setting of the CONF bit of the UF0MODS register to 1 indicates that Endpoint8 is valid. 4 E82AL1 This bit validates Endpoint8 when the two-series Alternative Setting and the Alternative Setting of the linked Interface are set to 1. 1: Validate the endpoint when Alternative Setting 1 is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting 1 is set with CONF bit = 1 (default value). This bit is valid when the E85AL4 to E85AL1 bits are 0000. 3 to 0 E85ALn These bits validate Endpoint8 when the five-series Alternative Setting and the Alternative Setting of the linked Interface are set to n. 1: Validate the endpoint when Alternative Setting n is set with CONF bit = 1. 0: Do not validate the endpoint even when Alternative Setting n is set with CONF bit = 1 (default value). Remark n = 1 to 4 User's Manual U16031EJ4V1UD 641 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.4.2 Data hold registers (1) UF0 EP0 read register (UF0E0R) The UF0E0R register is a 64-byte FIFO that stores the OUT data sent from the host in the data stage of control transfer to/from Endpoint0. This register is read-only, in 8-bit units. A write access to this register is ignored. The hardware automatically transfers data to the UF0E0R register when it has received the data from the host. When the data has been correctly received, the E0ODT bit of the UF0IS1 register is set to 1. The UF0E0L register holds the quantity of the received data, and an interrupt request (INTUSB0B) is issued. The UF0E0L register always updates the length of the received data while it is receiving data. If the final transfer is correct reception, the interrupt request is generated. If the reception is abnormal, the UF0E0L register is cleared to 0 and the interrupt request is not generated. The data held by the UF0E0R register must be read by FW up to the value of the amount of data read by the UF0E0L register. Check that all data has been read by using the EP0R bit of the UF0EPS0 register (EP0R = 0 when all data has been read). If the value of the UF0E0L register is 0, the EP0NKR bit of the UF0E0N register is cleared to 0, and the UF0E0R register is ready for reception. The UF0E0R register is cleared when the next SETUP token has been received. Caution Read all the data stored. Clear the FIFO to discard some data. 7 UF0E0R E0R7 6 E0R6 5 E0R5 4 E0R4 3 E0R3 2 E0R2 1 E0R1 0 E0R0 Address FFFFFE80H After reset Undefined Bit position 7 to 0 Bit name E0R7 to E0R0 Function These bits store the OUT data sent from the host in the data stage of control transfer to/from Endpoint0. The operation of the UF0E0R register is illustrated below. 642 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-1. Operation of UF0E0R Register Normal completion of reception Status of UF0E0R register FIFO hardAbnormal ware reception clear Normal completion of reception EP0NKR bit of UF0E0N register EP0R bit of UF0EPS0 register Hardware clear E0ODT bit of UF0IS1 register Reading FIFO starts Hardware clear Reading FIFO completed (2) UF0 EP0 length register (UF0E0L) The UF0E0L register stores the data length held by the UF0E0R register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0E0L register always updates the length of the received data while it is receiving data. If the final transfer is abnormal reception, the UF0E0L register is cleared to 0 and the interrupt request is not generated. The interrupt request is generated only when the reception is normal, and the FW can read as many data from the UF0E0R register as the value read from the UF0E0L register. The value of the UF0E0L register is decremented each time the UF0E0R register has been read. 7 UF0E0L E0L7 6 E0L6 5 E0L5 4 E0L4 3 E0L3 2 E0L2 1 E0L1 0 E0L0 Address FFFFFE81H After reset 00H Bit position 7 to 0 Bit name E0L7 to E0L0 Function These bits store the data length held by the UF0E0R register. User's Manual U16031EJ4V1UD 643 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP0 setup register (UF0E0ST) The UF0E0ST register holds the SETUP data sent from the host. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0E0ST register always writes data when a SETUP transaction has been received. The hardware sets the PROT bit of the UF0IS1 register when it has correctly received the SETUP transaction. It sets the CPUDEC bit of the UF0IS1 register in the case of an FW-processed request. Then an interrupt request (INTUSB0B) is issued. In the case of an FW-processed request, be sure to read the request in 8-byte units. If it is not read in 8-byte units, the subsequent requests cannot be correctly decoded. The read counter of the UF0E0ST register is not cleared even when Bus Reset is received. Always read this counter in 8-byte units regardless of whether Bus Reset is received or not. Because the UF0E0ST register always enables writing, the hardware overwrites data to this register even if a SETUP transaction is received while the data of the register is being read. Even if the SETUP transaction cannot be correctly received, the CPUDEC interrupt request and Protect interrupt request are not generated, but the previous data is discarded. If a SETUP token of less than 8 bytes is received, however, the received SETUP token is discarded, and the previously received SETUP data is retained. If the SETUP token is received more than once when control transfer is executed once, be sure to check the PROT bit of the UF0IS1 register under the conditions below. If PROT bit = 1, read the UF0E0ST register again because the SETUP transaction has been received more than once. <1> If a request is decoded by FW and the UF0E0R register is read or the UF0E0W register is written <2> When preparing for a STALL response for the request to which the decode result does not correspond Caution Be sure to read all the stored data. The UF0E0ST register is always updated by the request in the SETUP transaction. 7 UF0E0ST E0S7 6 E0S6 5 E0S5 4 E0S4 3 E0S3 2 E0S2 1 E0S1 0 E0S0 Address FFFFFE82H After reset 00H Bit position 7 to 0 Bit name E0S7 to E0S0 Function These bits hold the SETUP data sent from the host. The operation of the UF0E0ST register is illustrated below. 644 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-2. Operation of UF0E0ST Register (a) Normal Completion of normal reception of SETUP token Status of UF0E0ST register Completion of normal reception of SETUP token FW processing Hardware processing CPUDEC bit of UF0IS1 register PROT bit of UF0IS1 register INT clear (FW clear) Hardware clear INT clear (FW clear) Completion of decoding request Completion of reading FIFO Completion Completion of decoding of reading request FIFO (b) When SETUP transaction is received more than once Completion Start of of normal reception reception of second of second SETUP token SETUP token Completion of normal reception of SETUP token Status of UF0E0ST register Hardware clear on completion of reading 8 bytes CPUDEC bit of UF0IS1 register PROT bit of UF0IS1 register Completion of decoding request Hardware clear INT clear (FW clear) INT clear (FW clear) Completion of decoding request Completion of reading FIFO User's Manual U16031EJ4V1UD 645 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP0 write register (UF0E0W) The UF0E0W register is a 64-byte FIFO that stores the IN data (passes it to SIE) sent to the host in the data stage to Endpoint0. This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with an IN token only when the EP0NKW bit of the UF0E0N register is set to 1 (when NAK is not transmitted). When data is transmitted and when the host correctly receives the data, the EP0NKW bit of the UF0E0N register is automatically cleared to 0 by hardware. A short packet is transmitted when data is written to the UF0E0W register and the E0DED bit of the UF0DEND register is set to 1 (EP0W bit of the UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0E0W register is cleared and the E0DED bit of the UF0DEND register is set to 1 (EP0W bit of the UF0EPS0 register = 1 (data exists)). The UF0E0W register is cleared to 0 when the next SETUP token is received while transmission has not been completed yet. If the stage of control transfer (read) changes to the status stage while ACK has not been correctly received in the data stage, the UF0E0W register is automatically cleared to 0. At the same time, it is also cleared to 0 if the EP0NKW bit of the UF0E0N register is 1. If the UF0E0W register is read while no data is in it, 00H is read. 7 UF0E0W E0W7 6 E0W6 5 E0W5 4 E0W4 3 E0W3 2 E0W2 1 E0W1 0 E0W0 Address FFFFFE83H After reset Undefined Bit position 7 to 0 Bit name E0W7 to E0W0 Function These bits store the IN data sent to the host in the data stage to Endpoint0. The operation of the UF0E0W register is illustrated below. 646 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-3. Operation of UF0E0W Register (a) 16-byte transmission Transmission completed ACK reception ReTranstransmission mission completed ACK starts Transcannot be ACK mission received reception starts Transmission starts Status of UF0E0W register 16-byte transfer 16-byte transfer Re-transfer EP0NKW bit of UF0EN register EP0W bit of UF0EPS0 register FIFO full FIFO full INT clear (FW clear) E0INDT bit of UF0IS1 register Writing Writing FIFO FIFO starts completed Hardware clear Writing Writing FIFO FIFO starts completed Counter reloaded (b) When Null packet or short packet is transmitted Transmission completed ACK reception Transmission completed ACK reception Transmission starts Status of UF0E0W register Transmission starts Transfer of Null packet Short packet transfer E0DED bit of UF0DEND register is set. EP0NKW bit of UF0EN register EP0W bit of UF0EPS0 register E0DED bit of UF0DEND register is set. INT clear (FW clear) E0INDT bit of UF0IS1 register FIFO FW clear Hardware clear Writing Writing FIFO FIFO starts completed User's Manual U16031EJ4V1UD 647 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (5) UF0 bulk out 1 register (UF0BO1) The UF0BO1 register is a 64-byte x 2 FIFO that stores data for Endpoint2. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when data is in the FIFO on the SIE side and when no data is in the FIFO on the CPU side (counter value = 0). This register is read-only, in 8-bit units. A write access to this register is ignored. When the hardware receives data for Endpoint2 from the host, it automatically transfers the data to the UF0BO1 register. When the register correctly receives the data, a FIFO toggle operation occurs. As a result, the BKO1DT bit of the UF0IS3 register is set to 1, the quantity of the received data is held by the UF0BO1L register, and an interrupt request or DMA request is issued to the CPU. Whether the interrupt request or DMA request is issued can be selected by using the DQBO1MS bit of the UF0IDR register. Read the data held by the UF0BO1 register by FW, up to the value of the amount of data read by the UF0BO1L register. When the correct received data is held by the FIFO connected to the SIE side and the value of the UF0BO1L register reaches 0, the toggle operation of the FIFO occurs, and the BKO1NK bit of the UF0EN register is automatically cleared to 0. If data greater than the value of the UF0BO1L register is read and if the FIFO toggle condition is satisfied, the toggle operation of the FIFO occurs. As a result, the next packet may be read by mistake. Note that, if the toggle condition is not satisfied, the first data is repeatedly read. If overrun data is received while data is held by the FIFO connected to the CPU side, Endpoint2 stalls, and the FIFO on the CPU side is cleared. When the UF0BO1 register is read while no data is in it, an undefined value is read. Caution Be sure to read all the data stored in this register. 7 UF0BO1 BKO17 6 BKO16 5 BKO15 4 BKO14 3 BKO13 2 BKO12 1 BKO11 0 BKO10 Address FFFFFE84H After reset Undefined Bit position 7 to 0 Bit name BKO17 to BKO10 These bits store data for Endpoint2. Function The operation of the UF0BO1 register is illustrated below. 648 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-4. Operation of UF0BO1 Register (1/2) (a) Operation example 1 Reception completed Status of UF0BO1 register SIE side FIFO toggle Transmission starts Transmission FIFO toggle completed ACK transmission ACK transmission FIFO_0 FIFO_1 CPU side Reading FIFO starts Reading FIFO completed 64-byte transfer BKO1NK bit of UF0EN register BKO1FL bit of UF0IS3 register Reading FIFO starts FIFO_1 FIFO_0 FIFO_0 FIFO_1 Reading FIFO completed 64-byte transfer Transfer of data less than 64 bytes BKOUT1 bit of UF0EPS0 register BKO1DT bit of UF0IS3 register FW clear User's Manual U16031EJ4V1UD 649 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-4. Operation of UF0BO1 Register (2/2) (b) Operation example 2 Transmission Null starts reception Status of completed UF0BO1 register SIE side Reception completed FIFO toggle Transmission Null starts reception completed Reception completed FIFO toggle ACK transmission ACK transmission FIFO_0 FIFO_1 CPU side Reading FIFO starts 0-byte transfer BKO1NL bit of UF0IS3 register BKOUT1 bit of UF0EPS0 register 64-byte transfer FW clear 0-byte transfer FIFO_1 FIFO_0 FIFO_0 FIFO_1 Reading FIFO completed Transfer of data less than 64 bytes 64-byte transfer BKO1DT bit of UF0IS3 register FW clear 650 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (6) UF0 bulk out 1 length register (UF0BO1L) The UF0BO1L register stores the length of the data held by the UF0BO1 register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0BO1L register always updates the received data length while it is receiving data. If the final transfer is abnormal reception, the UF0BO1L register is cleared to 00H, and an interrupt request is not generated. Only if the reception is normal, the interrupt request is generated, and FW can read as much data from the UF0BO1 register as the value read from the UF0BO1L register. The value of the UF0BO1L register is decremented each time the UF0BO1 register has been read. 7 UF0BO1L BKO1L7 6 BKO1L6 5 BKO1L5 4 BKO1L4 3 BKO1L3 2 BKO1L2 1 BKO1L1 0 BKO1L0 Address FFFFFE85H After reset 00H Bit position 7 to 0 Bit name BKO1L7 to BKO1L0 Function These bits store the length of the data held by the UF0BO1 register. User's Manual U16031EJ4V1UD 651 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (7) UF0 bulk out 2 register (UF0BO2) The UF0BO2 register is a 64-byte x 2 FIFO that stores data for Endpoint4. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when data is in the FIFO on the SIE side and when no data is in the FIFO on the CPU side (counter value = 0). This register is read-only, in 8-bit units. A write access to this register is ignored. When the hardware receives data for Endpoint4 from the host, it automatically transfers the data to the UF0BO2 register. When the register correctly receives the data, a FIFO toggle operation occurs. As a result, the BKO2DT bit of the UF0IS3 register is set to 1, the quantity of the received data is held by the UF0BO2L register, and an interrupt request or DMA request is issued to the CPU. Whether the interrupt request or DMA request is issued can be selected by using the DQBO2MS bit of the UF0IDR register. Read the data held by the UF0BO2 register by FW, up to the value of the amount of data read by the UF0BO2L register. When the correct received data is held by the FIFO connected to the SIE side and the value of the UF0BO2L register reaches 0, the toggle operation of the FIFO occurs, and the BKO2NK bit of the UF0EN register is automatically cleared to 0. If data greater than the value of the UF0BO2L register is read and if the FIFO toggle condition is satisfied, the toggle operation of the FIFO occurs. As a result, the next packet may be read by mistake. Note that, if the toggle condition is not satisfied, the first data is repeatedly read. If overrun data is received while data is held by the FIFO connected to the CPU side, Endpoint4 stalls, and the FIFO on the CPU side is cleared. When the UF0BO2 register is read while no data is in it, an undefined value is read. Caution Be sure to read all the data stored in this register. 7 UF0BO2 BKO27 6 BKO26 5 BKO25 4 BKO24 3 BKO23 2 BKO22 1 BKO21 0 BKO20 Address FFFFFE86H After reset Undefined Bit position 7 to 0 Bit name BKO27 to BKO20 These bits store data for Endpoint4. Function The operation of the UF0BO2 register is illustrated below. 652 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-5. Operation of UF0BO2 Register (1/2) (a) Operation example 1 Reception completed Status of UF0BO2 register SIE side Reception completed FIFO toggle ACK Transmission transmission starts FIFO toggle ACK transmission FIFO_0 FIFO_1 CPU side Reading FIFO starts Reading FIFO completed 64-byte transfer BKO2NK bit of UF0EN register BKO2FL bit of UF0IS3 register Reading FIFO starts FIFO_1 FIFO_0 FIFO_0 FIFO_1 Reading FIFO completed 64-byte transfer Transfer of data less than 64 bytes BKOUT2 bit of UF0EPS0 register BKO2DT bit of UF0IS3 register FW clear User's Manual U16031EJ4V1UD 653 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-5. Operation of UF0BO2 Register (2/2) (b) Operation example 2 Null reception completed Status of UF0BO2 register SIE side Transmission starts Reception completed Null reception completed FIFO toggle Transmission starts ACK transmission Reception completed FIFO toggle ACK transmission FIFO_0 FIFO_1 CPU side Reading FIFO starts 0-byte transfer BKO2NL bit of UF0IS3 register BKOUT2 bit of UF0EPS0 register 64-byte transfer FW clear 0-byte transfer FIFO_1 FIFO_0 FIFO_0 FIFO_1 Reading FIFO completed Transfer of data less than 64 bytes 64-byte transfer BKO2DT bit of UF0IS3 register FW clear 654 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (8) UF0 bulk out 2 length register (UF0BO2L) The UF0BO2L register stores the length of the data held by the UF0BO2 register. This register is read-only, in 8-bit units. A write access to this register is ignored. The UF0BO2L register always updates the received data length while it is receiving data. If the final transfer is abnormal reception, the UF0BO2L register is cleared to 00H, and an interrupt request is not generated. Only if the reception is normal, the interrupt request is generated, and FW can read as much data from the UF0BO2 register as the value read from the UF0BO2L register. The value of the UF0BO2L register is decremented each time the UF0BO2 register has been read. 7 UF0BO2L BKO2L7 6 BKO2L6 5 BKO2L5 4 BKO2L4 3 BKO2L3 2 BKO2L2 1 BKO2L1 0 BKO2L0 Address FFFFFE87H After reset 00H Bit position 7 to 0 Bit name BKO2L7 to BKO2L0 Function These bits store the length of the data held by the UF0BO2 register. (9) UF0 bulk in 1 register (UF0BI1) The UF0BI1 register is a 64-byte x 2 FIFO that stores data for Endpoint1. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when no data is in the FIFO on the SIE side (counter value = 0) and when the FIFO on the CPU side is correctly written (FIFO full or BKI1DED bit = 1). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint1 only when the BKI1NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). The address at which data is to be written or read is managed by the hardware. Therefore, FW can transmit data to the host only by writing the data to the UF0BI1 register sequentially. A short packet is transmitted when data is written to the UF0BI1 register and the BKI1DED bit of the UF0DEND register is set to 1 (BKIN1 bit of UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0BI1 register is cleared and the BKI1DED bit of the UF0DEND register is set to 1 (BKIN1 bit of the UF0EPS0 register = 1 (data exists)). An interrupt request or DMA request can be selected by using the DQBI1MS bit of the UF0IDR register. 7 UF0BI1 BKI17 6 BKI16 5 BKI15 4 BKI14 3 BKI13 2 BKI12 1 BKI11 0 BKI10 Address FFFFFE88H After reset Undefined Bit position 7 to 0 Bit name BKI17 to BKI10 These bits store data for Endpoint1. Function The operation of the UF0BI1 register is illustrated below. User's Manual U16031EJ4V1UD 655 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-6. Operation of UF0BI1 Register (1/3) (a) Operation example 1 Transmission FIFO toggle completed ACK Transmission reception starts Transmission completed ACK reception FIFO toggle Status of UF0BO1 register SIE side FIFO_0 FIFO_1 FIFO_1 FIFO_0 FIFO_0 FIFO_1 CPU side Writing Writing FIFO FIFO starts completed Writing FIFO starts Writing FIFO completed 64-byte transfer 64-byte transfer 64-byte transfer BKI1DED bit of UF0DEND register is set or hardware set BKI1NK bit of UF0EN register BKI1DED bit of UF0DEND register is set or hardware set BKI1DT bit of UF0IS2 register INT clear (FW clear) Hardware clear 656 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-6. Operation of UF0BI1 Register (2/3) (b) Operation example 2 ACK reception FIFO toggle Status of UF0BO1 register SIE side Transmission completed Transmission starts ACK cannot be received Transmission completed Retransmission starts ACK reception FIFO_0 FIFO_1 CPU side Writing Writing FIFO FIFO starts completed 64-byte transfer BKI1NK bit of UF0EN register Writing FIFO starts 64-byte transfer FIFO_1 FIFO_0 Writing FIFO completed Re-transfer BKI1DT bit of UF0IS2 register INT clear (FW clear) Hardware clear User's Manual U16031EJ4V1UD 657 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-6. Operation of UF0BI1 Register (3/3) (c) Operation example 3 Transmission completed Status of UF0BO1 register SIE side Transmission completed ACK reception FIFO toggle ACK reception Transmission starts FIFO toggle FIFO_0 FIFO_1 FIFO_1 FIFO_0 FIFO_0 FIFO_1 CPU side FIFO clear Writing FIFO starts Writing FIFO completed 64-byte transfer Transfer of Null packet Short packet transfer BKI1DED bit of UF0DEND register is set. BKI1NK bit of UF0EN register BKI1DED bit of UF0DEND register is set. BKI1DT bit of UF0IS2 register INT clear (FW clear) Hardware clear 658 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (10) UF0 bulk in 2 register (UF0BI2) The UF0BI2 register is a 64-byte x 2 FIFO that stores data for Endpoint3. This register consists of two banks of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU sides. The toggle operation takes place when no data is in the FIFO on the SIE side (counter value = 0) and when the FIFO on the CPU side is correctly written (FIFO full or BKI2DED bit = 1). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint3 only when the BKI2NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). The address at which data is to be written or read is managed by the hardware. Therefore, FW can transmit data to the host only by writing the data to the UF0BI2 register sequentially. A short packet is transmitted when data is written to the UF0BI2 register and the BKI2DED bit of the UF0DEND register is set to 1 (BKIN2 bit of UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0BI2 register is cleared and the BKI2DED bit of the UF0DEND register is set to 1 (BKIN2 bit of the UF0EPS0 register = 1 (data exists)). An interrupt request or DMA request can be selected by using the DQBI2MS bit of the UF0IDR register. 7 UF0BI2 BKI27 6 BKI26 5 BKI25 4 BKI24 3 BKI23 2 BKI22 1 BKI21 0 BKI20 Address FFFFFE89H After reset Undefined Bit position 7 to 0 Bit name BKI27 to BKI20 These bits store data for Endpoint3. Function The operation of the UF0BI2 register is illustrated below. User's Manual U16031EJ4V1UD 659 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-7. Operation of UF0BI2 Register (1/3) (a) Operation example 1 Transmission FIFO toggle completed ACK Transmission reception starts Transmission completed ACK reception FIFO toggle Status of UF0BI2 register SIE side FIFO_0 FIFO_1 CPU side Writing Writing FIFO FIFO starts completed 64-byte transfer BKI2NK bit of UF0EN register Writing FIFO starts FIFO_1 FIFO_0 FIFO_0 FIFO_1 Writing FIFO completed 64-byte transfer BKI2DED bit of UF0DEND register is set or hardware set. 64-byte transfer BKI2DED bit of UF0DEND register is set or hardware set. Hardware clear BKI2DT bit of UF0IS2 register INT clear (FW clear) 660 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-7. Operation of UF0BI2 Register (2/3) (b) Operation example 2 ACK cannot be received Transmission completed Status of UF0BI2 register SIE side Transmission FIFO toggle completed ACK Transmission reception starts ACK Re- reception transmission starts FIFO_0 FIFO_1 CPU side Writing Writing FIFO FIFO starts completed 64-byte transfer BKI2NK bit of UF0EN register Writing FIFO starts FIFO_1 FIFO_0 Writing FIFO completed Re-transfer 64-byte transfer BKI2DT bit of UF0IS2 register INT clear (FW clear) Hardware clear User's Manual U16031EJ4V1UD 661 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-7. Operation of UF0BI2 Register (3/3) (c) Operation example 3 Transmission Transmission FIFO toggle completed completed ACK Transmission ACK reception starts reception FIFO toggle Status of UF0BI2 register SIE side FIFO_0 FIFO_1 CPU side FIFO clear Writing FIFO starts FIFO_1 FIFO_0 FIFO_0 FIFO_1 Writing FIFO completed Short packet transfer BKI2DED bit of UF0DEND register is set. 64-byte transfer BKI2NK bit of UF0EN register Transfer of Null packet BKI2DED bit of UF0DEND register is set. Hardware clear BKI2DT bit of UF0IS2 register INT clear (FW clear) 662 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (11) UF0 interrupt 1 register (UF0INT1) The UF0INT1 register is an 8-byte FIFO that stores data for Endpoint7 (to be passed to SIE). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint7 only when the IT1NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). When the data is transmitted and the host correctly receives it, the IT1NK bit of the UF0EN register is automatically cleared to 0 by hardware. A short packet is transmitted when data is written to the UF0INT1 register and the IT1DEND bit of the UF0DEND register is set to 1 (IT1 bit of the UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0INT1 register is cleared and the IT1DEND bit of the UF0DEND register is set to 1 (IT1 bit of the UF0EPS0 register = 1 (data exists)). 7 UF0INT1 IT17 6 IT16 5 IT15 4 IT14 3 IT13 2 IT12 1 IT11 0 IT10 Address FFFFFE8AH After reset Undefined Bit position 7 to 0 Bit name IT17 to IT10 These bits store data for Endpoint7. Function The operation of the UF0INT1 register is illustrated below. User's Manual U16031EJ4V1UD 663 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-8. Operation of UF0INT1 Register (a) 8-byte transfer Transmission completed Transmission ACK starts reception Status of UF0INT1 register Transmission Re-transmission completed starts Transmission ACK cannot ACK be received starts reception 8-byte transfer 8-byte transfer Re-transfer IT1NK bit of UF0EN register IT1 bit of UF0EPS0 register FIFO full FIFO full INT clear (FW clear) IT1DT bit of UF0IS2 register Writing Writing FIFO FIFO starts completed Hardware clear Writing Writing FIFO FIFO starts completed Counter reloaded (b) When Null packet or short packet is transmitted Transmission completed Transmission ACK starts reception Status of UF0INT1 register Transmission completed Transmission ACK starts reception Transfer of Null packet Short packet transfer IT1DEND bit of UF0DEND register is set. IT1NK bit of UF0EN register IT1 bit of UF0EPS0 register IT1DEND bit of UF0DEND register is set. INT clear (FW clear) IT1DT bit of UF0IS2 register FIFO FW clear Hardware clear Writing Writing FIFO FIFO starts completed 664 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (12) UF0 interrupt 2 register (UF0INT2) The UF0INT2 register is an 8-byte FIFO that stores data for Endpoint8 (to be passed to SIE). This register is write-only, in 8-bit units. When this register is read, 00H is read. The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint8 only when the IT2NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). When the data is transmitted and the host correctly receives it, the IT2NK bit of the UF0EN register is automatically cleared to 0 by hardware. A short packet is transmitted when data is written to the UF0INT2 register and the IT2DEND bit of the UF0DEND register is set to 1 (IT2 bit of the UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0INT2 register is cleared and the IT2DEND bit of the UF0DEND register is set to 1 (IT2 bit of the UF0EPS0 register = 1 (data exists)). 7 UF0INT2 IT27 6 IT26 5 IT25 4 IT24 3 IT23 2 IT22 1 IT21 0 IT20 Address FFFFFE8BH After reset Undefined Bit position 7 to 0 Bit name IT27 to IT20 These bits store data for Endpoint8. Function The operation of the UF0INT2 register is illustrated below. User's Manual U16031EJ4V1UD 665 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-9. Operation of UF0INT2 Register (a) 8-byte transfer Retransmission starts ACK reception Transmission completed Transmission starts Status of UF0INT2 register ACK reception Transmission completed Transmission starts ACK cannot be received 8-byte transfer 8-byte transfer Re-transfer IT2NK bit of UF0EN register IT2 bit of UF0EPS0 register FIFO full FIFO full INT clear (FW clear) IT2DT bit of UF0IS2 register Writing Writing FIFO FIFO starts completed Hardware clear Writing Writing FIFO FIFO starts completed Counter reloaded (b) When Null packet or short packet is transmitted Transmission completed Transmission ACK starts reception Status of UF0INT2 register Transmission completed Transmission ACK starts reception Transfer of Null packet Short packet transfer IT1DEND bit of UF0DEND register is set. IT2NK bit of UF0EN register IT2 bit of UF0EPS0 register IT1DEND bit of UF0DEND register is set. INT clear (FW clear) IT2DT bit of UF0IS2 register FIFO FW clear Hardware clear Writing Writing FIFO FIFO starts completed 666 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.4.3 Request data register area (1) UF0 device status register L (UF0DSTL) This register stores the value that is to be returned in response to the GET_STATUS Device request. This register can be read or written in 8-bit units. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Device request. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0DSTL 0 6 0 5 0 4 0 3 0 2 0 1 RMWK 0 SFPW Address FFFFFEA2H After reset 00H Bit position 1 Bit name RMWK Function This bit specifies whether the remote wakeup function of the device is used. 1: Enabled 0: Disabled If the device supports a remote wakeup function, this bit is set to 1 by hardware when the SET_FEATURE Device request has been received, and is cleared to 0 by hardware when the CLEAR_FEATURE Device request has been received. If the device does not support a remote wakeup function, make sure that the SET_FEATURE Device request is not issued from the host. 0 SFPW This bit indicates whether the device is self-powered or bus-powered. 1: Self-powered 0: Bus-powered User's Manual U16031EJ4V1UD 667 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2) UF0 EP0 status register L (UF0E0SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint0 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in USBF, the E0HALT bit is set to 1 by FW. A write access to this register is ignored while a USB-side access to Endpoint0 is being received. When the E0HALT bit is set to 1 by FW, it is not reflected until the next SETUP token is received if the control transfer immediately before is for the SET_FEATURE Endpoint0, CLEAR_FEATURE Endpoint0, GET_STATUS Endpoint0 request, or an FW-processed request. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint0 request. If Endpoint0 has stalled, the UF0E0W and UF0E0R registers are cleared, and the EP0NKW and EP0NKR bits of the UF0E0N register are cleared to 0. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0E0SL 0 6 0 5 0 4 0 3 0 2 0 1 0 0 E0HALT Address FFFFFEA6H After reset 00H Bit position 0 Bit name E0HALT Function This bit indicates the status of Endpoint0. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint0 request has been received, and cleared to 0 by hardware when the CLEAR_FEATURE Endpoint0 request has been received. DATA PID is initialized to DATA0. 668 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (3) UF0 EP1 status register L (UF0E1SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint1 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint1, the E1HALT bit is set to 1. A write access to this register is ignored while a USB-side access to Endpoint1 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint1 request. If Endpoint1 has stalled, the UF0BI1 register is cleared and the BKI1NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint1, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0E1SL 0 6 0 5 0 4 0 3 0 2 0 1 0 0 E1HALT Address FFFFFEA8H After reset 00H Bit position 0 Bit name E1HALT Function This bit indicates the status of Endpoint1. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint1 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint1 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint1 is linked has correctly been received. DATA PID is initialized to DATA0. User's Manual U16031EJ4V1UD 669 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (4) UF0 EP2 status register L (UF0E2SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint2 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint2, the E2HALT bit is set to 1. A write access to this register is ignored while a USB-side access to Endpoint2 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint2 request. If Endpoint2 has stalled, the UF0BO1 register is cleared and the BKO1NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint2, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0E2SL 0 6 0 5 0 4 0 3 0 2 0 1 0 0 E2HALT Address FFFFFEAAH After reset 00H Bit position 0 Bit name E2HALT Function This bit indicates the status of Endpoint2. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint2 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint2 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint2 is linked has correctly been received. DATA PID is initialized to DATA0. 670 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (5) UF0 EP3 status register L (UF0E3SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint3 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint3, the E3HALT bit is set to 1. A write access to this register is ignored while a USB-side access to Endpoint3 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint3 request. If Endpoint3 has stalled, the UF0BI2 register is cleared and the BKI2NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint3, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0E3SL 0 6 0 5 0 4 0 3 0 2 0 1 0 0 E3HALT Address FFFFFEACH After reset 00H Bit position 0 Bit name E3HALT Function This bit indicates the status of Endpoint3. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint3 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint3 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint3 is linked has correctly been received. DATA PID is initialized to DATA0. User's Manual U16031EJ4V1UD 671 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (6) UF0 EP4 status register L (UF0E4SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint4 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint4, the E4HALT bit is set to 1. A write access to this register is ignored while a USB-side access to Endpoint4 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint4 request. If Endpoint4 has stalled, the UF0BO2 register is cleared and the BKO2NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint4, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0E4SL 0 6 0 5 0 4 0 3 0 2 0 1 0 0 E4HALT Address FFFFFEAEH After reset 00H Bit position 0 Bit name E4HALT Function This bit indicates the status of Endpoint4. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint4 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint4 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint4 is linked has correctly been received. DATA PID is initialized to DATA0. 672 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (7) UF0 EP7 status register L (UF0E7SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint7 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint7, the E7HALT bit is set to 1. A write access to this register is ignored while a USB-side access to Endpoint7 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint7 request. If Endpoint7 has stalled, the UF0INT1 register is cleared and the IT1NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint7, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0E7SL 0 6 0 5 0 4 0 3 0 2 0 1 0 0 E7HALT Address FFFFFEB4H After reset 00H Bit position 0 Bit name E7HALT Function This bit indicates the status of Endpoint7. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint7 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint7 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint7 is linked has correctly been received. DATA PID is initialized to DATA0. User's Manual U16031EJ4V1UD 673 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (8) UF0 EP8 status register L (UF0E8SL) This register stores the value that is to be returned in response to the GET_STATUS Endpoint8 request. This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when the EP0NKA bit is set to 1. If an error occurs in Endpoint8, the E8HALT bit is set to 1. A write access to this register is ignored while a USB-side access to Endpoint8 is being received. The hardware automatically transmits the contents of this register to the host when it has received the GET_STATUS Endpoint8 request. If Endpoint8 has stalled, the UF0INT2 register is cleared and the IT2NK bit is cleared to 0. Because writing this register is always masked when transfer to Endpoint8, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0E8SL 0 6 0 5 0 4 0 3 0 2 0 1 0 0 E8HALT Address FFFFFEB6H After reset 00H Bit position 0 Bit name E8HALT Function This bit indicates the status of Endpoint8. 1: Stalled 0: Not stalled This bit is set to 1 by hardware when the SET_FEATURE Endpoint8 request has been received. It is cleared to 0 by hardware when the CLEAR_FEATURE Endpoint8 request, SET_CONFIGURATION request, or the SET_INTERFACE request for the Interface to which Endpoint8 is linked has correctly been received. DATA PID is initialized to DATA0. 674 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (9) UF0 address register (UF0ADRS) This register stores the device address. This register is read-only, in 8-bit units. The device address sent by the SET_ADDRESS request is analyzed and the resultant value is automatically written to this register. If the SET_ADDRESS request is processed by FW, the value of this register is reflected as the device address when the SUCCESS signal is received in the status stage. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0ADRS 0 6 ADRS6 5 ADRS5 4 ADRS4 3 ADRS3 2 ADRS2 1 ADRS1 0 ADRS0 Address FFFFFEC0H After reset 00H Bit position 6 to 0 Bit name ADRS6 to ADRS0 Function These bits hold the device address of SIE. User's Manual U16031EJ4V1UD 675 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (10) UF0 configuration register (UF0CNF) This register stores the value that is to be returned in response to the GET_CONFIGURATION request. This register is read-only, in 8-bit units. When the SET_CONFIGURATION request is received, its wValue is automatically written to this register. To change the value of this register by FW after a value other than 00H has been written to the register, write 00H once and then write the desired value. When a change of the value of this register from 00H to other than 00H is detected, the CONF bits are set to 1. If the SET_CONFIGURATION request is processed by FW, the status of this register is immediately reflected on the UF0MODS register as soon as data has been written to this register (CONF bits = 1 before completion of the status stage). Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0CNF 0 6 0 5 0 4 0 3 0 2 0 1 CONF1 0 CONF0 Address FFFFFEC1H After reset 00H Bit position 1, 0 Bit name CONF1, CONF0 Function These bits hold the data to be returned in response to the GET_CONFIGURATION request. 676 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (11) UF0 interface 0 register (UF0IF0) This register stores the value that is to be returned in response to the GET_INTERFACE wIndex = 0 request. This register is read-only, in 8-bit units. When the SET_INTERFACE request is received, its wValue is automatically written to this register. If the SET_INTERFACE request is processed by FW, wIndex and wValue are decoded, and the setting of endpoint is automatically changed. At this time, the status bit of the target endpoint and DPID are automatically cleared to 0, depending on the setting. The FIFO is not cleared automatically. Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0IF0 0 6 0 5 0 4 0 3 0 2 IF02 1 IF01 0 IF00 Address FFFFFEC2H After reset 00H Bit position 2 to 0 Bit name IF02 to IF00 Function These bits hold the data to be returned in response to GET_INTERFACE wIndex = 0 request. User's Manual U16031EJ4V1UD 677 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (12) UF0 interface 1 to 4 registers (UF0IF1 to UF0IF4) These registers store the value that is to be returned in response to the GET_INTERFACE wIndex = n request (n = 1 to 4). These registers are read-only, in 8-bit units. When the SET_INTERFACE request is received, its wValue is automatically written to these registers. These registers are invalidated according to the setting of the UF0AIFN and UF0AAS registers. If the SET_INTERFACE request is processed by FW, wIndex and wValue are decoded, and the setting of endpoint is automatically changed. At this time, the status bit of the target endpoint and DPID are automatically cleared to 0, depending on the setting. The FIFO is not cleared automatically. Caution To rewrite these registers, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0IF1 0 6 0 5 0 4 0 3 0 2 IF12 1 IF11 0 IF10 Address FFFFFEC3H After reset 00H UF0IF2 0 0 0 0 0 IF22 IF21 IF20 FFFFFEC4H 00H UF0IF3 0 0 0 0 0 IF32 IF31 IF30 FFFFFEC5H 00H UF0IF4 0 0 0 0 0 IF42 IF41 IF40 FFFFFEC6H 00H Bit position 2 to 0 Bit name IFn2 to IFn0 Function These bits hold the data to be returned in response to GET_INTERFACE wIndex = n request. Remark n = 1 to 4 678 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (13) UF0 descriptor length register (UF0DSCL) This register stores the length of the value that is to be returned in response to the GET_DESCRIPTOR Configuration request. The value of this register is the number of bytes of all the descriptors set by the UF0CIEn register minus 1 (n = 0 to 255). The total descriptor length that is to be returned in response to the GET_DESCRIPTOR Configuration request is determined according to the value of this register. This register can be read or written in 8-bit units. However, data can be written to this register only when the EP0NKA bit is set to 1. Processing of wLength is automatically controlled. If this register is set to 00H, it means that the descriptor to be returned is 1 byte long. If the register is set to FFH, a descriptor length of 256 bytes is returned. When a descriptor exceeding 256 bytes in length is used, set the CDCGDST bit of the UF0MODC register to 1 and process the GET_DESCRIPTOR request by FW (at this time, the CDCGD bit of the UF0MODS register is also set to 1). Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 7 UF0DSCL DPL7 6 DPL6 5 DPL5 4 DPL4 3 DPL3 2 DPL2 1 DPL1 0 DPL0 Address FFFFFED0H After reset 00H Bit position 7 to 0 Bit name DPL7 to DPL0 Function These bits set the value of the number of bytes of all the descriptors to be returned in response to the GET_DESCRIPTOR Configuration request minus 1. User's Manual U16031EJ4V1UD 679 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (14) UF0 device descriptor registers 0 to 17 (UF0DD0 to UF0DD17) These registers store the value to be returned in response to the GET_DESCRIPTOR Device request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1. Cautions 1. To rewrite these registers, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 2. Use the value defined by USB Specification Ver. 2.0 and the latest Class Specification as the set value. 7 UF0DDn (n = 0 to 17) 6 5 4 3 2 1 0 Address After reset See Table 11-4. Undefined Table 11-4. Mapping and Data of UF0 Device Descriptor Registers Symbol UF0DD0 UF0DD1 UF0DD2 UF0DD3 UF0DD4 UF0DD5 UF0DD6 UF0DD7 UF0DD8 UF0DD9 UF0DD10 UF0DD11 UF0DD12 UF0DD13 UF0DD14 UF0DD15 UF0DD16 UF0DD17 Address FFFFFED1H FFFFFED2H FFFFFED3H FFFFFED4H FFFFFED5H FFFFFED6H FFFFFED7H FFFFFED8H FFFFFED9H FFFFFEDAH FFFFFEDBH FFFFFEDCH FFFFFEDDH FFFFFEDEH FFFFFEDFH FFFFFEE0H FFFFFEE1H FFFFFEE2H iManufacturer iProduct lSerialNumber BNumConfigurations bcdDevice idProduct bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor Field Name bLength bDescriptorType bcdUSB Size of this descriptor Device descriptor type Value below decimal point of Rev. number of USB specification Value above decimal point of Rev. number of USB specification Class code Subclass code Protocol code Maximum packet size of Endpoint0 Lower value of vendor ID Higher value of vendor ID Lower value of product ID Higher value of product ID Lower value of device release number Higher value of device release number Index of string descriptor describing manufacturer Index of string descriptor describing product Index of string descriptor describing device serial number Number of settable configurations Contents 680 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (15) UF0 configuration/interface/endpoint descriptor registers 0 to 255 (UF0CIE0 to UF0CIE255) These registers store the value to be returned in response to the GET_DESCRIPTOR Configuration request. These registers can be read or written in 8-bit units. However, data can be written to these registers only when the EP0NKA bit is set to 1. Descriptor information of up to 256 bytes can be stored in these registers. Store each descriptor in the order of Configuration, Interface, and Endpoint (see Table 11-5). If there are two or more Interfaces, repeatedly store the data following the Interface descriptor. Table 11-5. Mapping of UF0CIEn Register Address FFFFFEE3H FFFFFEECH FFFFFEF5H FFFFFEFCH FFFFFF03H : FFFFFFxxH FFFFFFxxH+9 FFFFFFxxH+16 FFFFFFxxH+23 : Descriptor Stored Configuration descriptor (9 bytes) Interface descriptor (9 bytes) Endpoint1 descriptor (7 bytes) Endpoint2 descriptor (7 bytes) Endpoint3 descriptor (7 bytes) : Interface descriptor (9 bytes) Endpoint1 descriptor (7 bytes) Endpoint2 descriptor (7 bytes) Endpoint3 descriptor (7 bytes) : The range of the valid data that can be set to these registers varies according to the setting of the UF0DSCL register. In addition to the descriptors listed in Table 11-6, descriptors peculiar to classes and vendors can also be stored. If all the values are fixed, they can be stored in ROM. Cautions 1. To rewrite these registers, set the EP0NKA bit to 1 before reading the register contents, and rewrite the register contents after confirming that the bit has been set, in order to prevent conflict between a read access and a write access. 2. Use the value defined by USB Specification Ver. 2.0 and the latest Class Specification as the set value. 7 UF0CIEn (n = 0 to 255) 6 5 4 3 2 1 0 Address FFFFFEE3H to FFFFFFE2H After reset Undefined User's Manual U16031EJ4V1UD 681 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Table 11-6. Data of UF0CIEn Register (a) Configuration descriptor (9 bytes) Offset 0 1 2 Field Name bLength bDescriptorType wTotalLength Size of this descriptor Descriptor type Lower value of the total number of bytes of Configuration, all Interface, and all Endpoint descriptors 3 Higher value of the total number of bytes of Configuration, all Interface, and all Endpoint descriptors 4 5 6 7 8 bNumInterface bConfigurationValue iConfiguration bmAttributes MaxPower Number of Interfaces Value to select this Configuration Index of string descriptor describing this Configuration Features of this Configuration (self-powered, without remote wakeup) Maximum power consumption of this Configuration (unit: mA) Contents (b) Interface descriptor (9 bytes) Offset 0 1 2 3 4 5 6 7 8 Field Name bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol Interface Size of this descriptor Descriptor type Value of this Interface Value to select alternative setting of Interface Number of usable Endpoints Class code Subclass code Protocol code Index of string descriptor describing this Interface Contents (c) Endpoint descriptor (7 bytes) Offset 0 1 2 3 4 5 6 bInterval Field Name bLength bDescriptorType bEndpointAddress bmAttributes wMaxPaketSize Size of this descriptor Descriptor type Address/transfer direction of this Endpoint Transfer type Lower value of maximum number of transfer data Higher value of maximum number of transfer data Transfer interval Contents 682 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.4.4 Peripheral control registers (1) USB function 0 DMA channel select register (UF0CS) This register allocates each DMA service of the USB function to a DMA channel. This register can be read or written in 16-bit units. To allocate the service of a USB function to a DMA channel by using this register, set this register in advance, set the DTFRn register (n = 0 to 3) of the DMA controller to 7FH, and enable USB_DMA in advance. Caution Setting the same DMA service to different DMA channels and setting different DMA services to the same DMA channel are prohibited. 15 UF0CS 0 14 13 12 11 0 10 9 8 7 0 6 5 4 3 0 2 UFD C02 1 0 Address FFFFFDF0H, FFFFFDF1H After reset 0000H UFD UFD UFD C32 C31 C30 UFD UFD UFD C22 C21 C20 UFD UFD UFD C12 C11 C10 UFD UFD C01 C00 Bit position 14 to 12, 10 to 8, 6 to 4, 2 to 0 Bit name UFDCn2 to UFDCn0 Function These bits set the DMA service of a USB function to be allocated to DMA channel n. UFDCn2 1 1 1 1 0 UFDCn1 1 1 0 0 X UFDCn0 1 0 1 0 X EP4_DMA EP3_DMA EP2_DMA EP1_DMA No allocation (DMA not used) Service to be allocated Remark X: Don't care Remark n = 0 to 3 User's Manual U16031EJ4V1UD 683 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (2) USB function 0 buffer control register (UF0BC) This register performs enable control and floating control on the input buffer of the USB function. This register can be read or written in 8-bit or 1-bit units. 7 UF0BC 0 6 0 5 0 4 0 3 0 2 0 1 UBFIEN 0 UBFIOR Address FFFFFDF2H After reset 00H Bit position 1 Bit name UBFIEN This bit controls use of the USB buffer. 1: Buffer valid 0: Buffer invalid Function Caution Clear this bit to 0 when the USB is not used. If this bit is set to 1, a current of 3 mA (TYP.) constantly flows, regardless of whether the USB is used or not. 0 UBFIOR This bit controls use of floating measures of the USB buffer. 1: Disables floating measures 0: Enables floating measures This bit prevents erroneous recognition of Bus Reset, Suspend, and Resume due to an undefined value when a cable is not connected (when data input is floated). When this bit is set to 1, control the processing for floating by the VBUS signal (which recognizes cable connection). 684 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) The following flowcharts illustrate the program execution when the host is disconnected and then reconnected, and the program execution when power is supplied. Figure 11-10. Flowchart of Program When Host Is Disconnected and Then Reconnected START Checks status of pin interrupt detecting host connection status Host disconnected? Yes Masks INTUSBnB and INTRSUM interrupts No Disables USE bus, enables measures against floating Checks status of pin interrupt detecting host connection status Host connected? Yes Unmasks USB-related interrupts and discards interrupts No Initialization processing of register area Automatic device setup by Plug&Play END Remark n = 0 to 2 User's Manual U16031EJ4V1UD 685 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-11. Flowchart of Program When Power Is Supplied START Masks INTUSBnB and INTRSUM interrupts Starts USBF clock supply Initializes register area, enables measures against floating Checks status of pin interrupt detecting host connection status Host connected? Yes Unmasks USB-related interrupts and discards interrupts No Enables USE bus, disables measures against floating Automatic device setup by Plug&Play END Remark n = 0 to 2 686 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.5 STALL Handshake or No Handshake Errors of USBF are defined to be handled as follows. Transfer Type Transaction Target Packet Token Error Type Function Response No response No response None None Processing Control transfer/ bulk transfer/ interrupt transfer IN/OUT/SETUP Endpoint not supported Endpoint transfer direction mismatch CRC error Bit stuffing error No response No response No response No response No response None None None None None Control transfer/ bulk transfer OUT/SETUP Data Timeout PID check error Unsupported PID (other than Data PID) CRC error Bit stuffing error No response No response ACK No response Note 1 Discard received data Discard received data Discard received data Discard received data OUT Control transfer (SETUP stage) Control transfer (data stage) OUT SETUP Data Data Data PID mismatch Overrun Data Overrun No response Set SNDSTL bit of UF0SDS register to 1 and discard received data Control transfer (status stage) OUT Data Overrun ACK or no response Note 2 Set SNDSTL bit of UF0SDS register to 1 and discard received data Set EnHALT bit of UF0EnSL register (n = 0 to 4, 7, 8) to 1 Bulk transfer OUT Data Overrun No response Note 1 Control transfer/ bulk transfer/ interrupt transfer IN Handshake PID check error - - - Hold transferred data and re-transfer data Note 3 Unsupported PID (other than ACK PID) Timeout Hold transferred data and re-transfer data Note 3 Hold transferred data and re-transfer data Note 3 Notes 1. A STALL response is made to re-transfer by the host. 2. An ACK response is made if the transfer data is of less than MaxPacketSize and the data received in the status stage is discarded. If MaxPacketSize is exceeded, no response is made, the SNDSTL bit of the UF0SDS register is set to 1, and the received data is discarded. 3. If an OUT transaction indicating a change from the data stage to the status stage is received during control transfer, an error is not handled and it is assumed that reception has been correctly completed. Cautions 1. It is judged by the Alternative Setting number currently set whether the target Endpoint is valid or invalid. 2. For the response to the request included in control transfer to/from Endpoint0, see 11.3 Requests. User's Manual U16031EJ4V1UD 687 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.6 Register Values in Specific Status Table 11-7. Register Values in Specific Status (1/2) Register Name UF0E0N register UF0E0NA register UF0EN register UF0ENM register UF0SDS register UF0CLR register UF0SET register UF0EPS0 register UF0EPS1 register UF0EPS2 register UF0IS0 register UF0IS1 register UF0IS2 register UF0IS3 register UF0IS4 register UF0IM0 register UF0IM1 register UF0IM2 register UF0IM3 register UF0IM4 register UF0IC0 register UF0IC1 register UF0IC2 register UF0IC3 register UF0IC4 register UF0IDR register UF0DMS0 register UF0DMS1 register UF0FIC0 register UF0FIC1 register UF0DEND register UF0GPR register UF0MODC register UF0MODS register UF0AIFN register UF0AAS register UF0ASS register UF0E1IM register UF0E2IM register 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H After CPU Reset (RESET) After Bus Reset Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. Bit 2 (CONF): Cleared (0), Other bits: Value is held. Value is held. Value is held. 00H Value is held. Value is held. 688 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Table 11-7. Register Values in Specific Status (2/2) Register Name UF0E3IM register UF0E4IM register UF0E7IM register UF0E8IM register UF0E0R register UF0E0L register UF0E0ST register UF0E0W register UF0BO1 register UF0BO1L register UF0BO2 register UF0BO2L register UF0BI1 register UF0BI2 register UF0INT1 register UF0INT2 register UF0DSTL register UF0E0SL register UF0E1SL register UF0E2SL register UF0E3SL register UF0E4SL register UF0E7SL register UF0E8SL register UF0ADRS register UF0CNF register UF0IF0 register UF0IF1 register UF0IF2 register UF0IF3 register UF0IF4 register UF0DSCL register UF0DDn register (n = 0 to 17) UF0CIEn register (n = 0 to 255) 00H 00H 00H 00H Undefined 00H 00H Undefined Note 1 Note 1 After CPU Reset (RESET) After Bus Reset Value is held. Value is held. Value is held. Value is held. Value is held. Value is held. 00H Value is held. Value is held. Value is held. Undefined 00H Undefined 00H Undefined Undefined Note 1 Note 1 Value is held. Value is held. Note 1 Value is held. Value is held. Value is held. Value is held. 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Value is held. Note 2 Note 2 Note 1 Undefined Undefined 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Note 2 Note 2 Notes 1. This register can be cleared to 0 by the RESET signal because its write pointer, counter, and read pointer are cleared to 0 when the RESET signal becomes active, in the same manner as clearing by the UF0FICn register, as the register is controlled by FIFO. 2. This register cannot be cleared to 0. Because data can be written to it by FW, however, any value can be written to the register (before doing so, however, be sure to set the EP0NKA bit of the UF0E0NA register to 1). User's Manual U16031EJ4V1UD 689 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7 FW Processing The following FW processing is performed. * Setting processing on device side for the SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and CLEAR_FEATURE requests during enumeration processing * Analysis and processing of XXXXStandard, XXXXClass, and XXXXVendor requests not subject to automatic processing * Reading data following bulk-transferred OUT token from receive buffer * Writing data to be returned in response to bulk-transferred IN token * Writing data to be returned in response to interrupt-transferred token The following table lists the requests supported by FW. 690 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Table 11-8. FW-Supported Standard Requests Request Reception Side CLEAR_FEATURE Interface Processing/ Frequency Automatic STALL response It is considered that this request does not come to Interface because there is no function selector value, though it is reserved for bmRequestType. When this request is received, the hardware makes an automatic STALL response. SET_FEATURE Interface Automatic STALL response It is considered that this request does not come to Interface because there is no function selector value, though it is reserved for bmRequestType. When this request is received, the hardware makes an automatic STALL response. GET_DESCRIPTOR String FW Returns the string descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and writes the data to be returned to the host, to the UF0E0W register. SET_DESCRIPTOR Device FW Rewrites the device descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and the writes the data for the next control transfer (OUT) to the UF0DDn register (n = 0 to 17). SET_DESCRIPTOR Configuration FW Rewrites the configuration descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and the writes the data for the next control transfer (OUT) to the UF0CIEn register (n = 0 to 255). SET_DESCRIPTOR String FW Rewrites the string descriptor. When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and loads the data for the next control transfer (OUT). Other NA FW When this request is received by the SETUP token, the hardware generates the CPUDEC interrupt request for FW. FW decodes the contents of the request from the CPUDEC interrupt request, and performs the necessary processing. Explanation User's Manual U16031EJ4V1UD 691 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.1 Initialization processing Initialization processing is executed in the following two ways. * Initialization of request data register area * Setting of interrupt When the request data register area is initialized, data for the GET_XXXX request to which a value is to be automatically returned is written and an endpoint is allocated to an interface. In the interrupt settings, the interrupt sources that do not have to be checked can be masked by using the UF0IMn register (n = 0 to 4). The following flowcharts illustrate the above processing. Figure 11-12. Initializing Request Data Register Area START UF0E0NA register = 01H EP0NKA = 1? (UF0E0NA) Yes Initialization of request data register area No : See Figure 11-13 Initialization of Request Data Register Area. UF0MODC register = 40H or 00H If the total number of bytes of the UF0CIEn register exceeds 256, set the UF0MODC register to 40H. No data has to be written to the UF0CIEn register. Setting of interface and endpoint : See Figure 11-14 Setting of Interface and Endpoint. UF0E0NA register = 00H Cancels NAK response to Endpoint0. END Remark n = 0 to 255 692 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-13. Initialization of Request Data Register Area UF0DSTL register = 0XH The value of 0XH depends on the power supply method. * SFPW = 1: Self-powered * SFPW = 0: Bus-powered n = 0 to 4, 7, or 8. Setting is unnecessary if the target endpoint is not used. UF0EnSL register = 00H Setting of UF0DSCL register Input the total number of bytes of the UF0CIEa register. Inputting UF0DDm register Inputting UF0CIEa register If the total number of bytes of the UF0CIEa register exceeds 256, set the UF0MODC register to 40H. No data has to be written to the UF0CIEa register. Remark m = 0 to 17 a = 0 to 255 Figure 11-14. Setting of Interface and Endpoint Setting of UF0AIFN register ADDIF, IFNO1, IFNO2 = 000: Interface number 0 is valid. ADDIF, IFNO1, IFNO2 = 100: Interface numbers 0 and 1 are valid. ADDIF, IFNO1, IFNO2 = 101: Interface numbers 0 to 2 are valid. ADDIF, IFNO1, IFNO2 = 110: Interface numbers 0 to 3 are valid. ADDIF, IFNO1, IFNO2 = 111: Interface numbers 0 to 4 are valid. Set Interface number(s) and a link with the 5- or 2-series Alternative Setting. Setting of UF0AAS register Setting of UF0EnIM register Set a link between the target Interface of endpoint n and Alternative Setting. Set 00H if the target endpoint is not used. Remark n = 1 to 4, 7, 8 User's Manual U16031EJ4V1UD 693 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-15. Setting of Interrupt START Setting of UF0IMn register Mask the interrupt source to avoid issuance of an unnecessary interrupt request (INTUSBmB). END Remark n = 0 to 4 m = 0 where n = 0, 1 m = 1 where n = 2, 3 m = 2 where n = 4 694 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.2 Interrupt servicing The following flowchart illustrates how an interrupt is serviced. Figure 11-16. Interrupt Servicing START INTUSBaB active (a = 0 to 2) No INTUSB2B = 0? Yes Masking ID bit No INTUSB0B = 0? Yes (n = 0, 1) (m = 2, 3) Reading UF0ISm register Reading UF0IS4 register Reading UF0ISn register SETINTC of UF0IC4 register = 0 Target bit of UF0ICn register = 0 Target bit of UF0ICm register = 0 Servicing interrupt END Remark : Processing by hardware The following bits of the UF0ISn register are automatically cleared by hardware when a given condition is satisfied (n = 1 to 4). * E0INDT, E0ODT, SUCES, STG, and CPUDEC bits of UF0IS1 register * BKI2DT, BKI1DT, IT2DT, and IT1DT bits of UF0IS2 register * BKO2FL, BKO2DT, BKO1FL, and BKO1DT bits of UF0IS3 register Because clearing an interrupt source by the UF0ICn register is given a lower priority than setting an interrupt source by hardware, the interrupt source may not be cleared depending on the timing (n = 0 to 4). User's Manual U16031EJ4V1UD 695 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.3 USB main processing USB main processing involves processing USB transactions. The types of transactions to be processed are as follows. * Fully automatically processed request for control transfer * Automatically processed requests for control transfer (SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, CLEAR_FEATURE) * CPUDEC request for control transfer * Processing for bulk transfer (IN) * Processing for bulk transfer (OUT) * Processing for interrupt transfer (IN) Processing for endpoint n involves writing or reading for data transfer. The flowchart shown below is for PIO. (1) Fully automatically processed request for control transfer Because the fully automatically processed request for control transfer is executed by hardware, it cannot be referenced by FW. Therefore, FW does not have to perform any special processing for this request. (2) Automatically processed requests for control transfer (SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, CLEAR_FEATURE) Processing to write a register for automatically processed requests for control transfer, such as SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and CLEAR_FEATURE requests, is automatically executed by hardware, but an interrupt request is issued for recognition on the device side. This processing may be ignored if there is no special processing to be executed. The flowcharts are shown below. 696 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-17. Automatically Processed Requests for Control Transfer START Receiving SETUP token Decoding request CLEAR_FEATURE? No Yes CLEAR_FEATURE processing Yes : See Figure 11-18 CLEAR_FEATURE Processing. SET_FEATURE processing Yes : See Figure 11-19 SET_FEATURE Processing. SET_CONFIGURATION processing Yes : See Figure 11-20 SET_CONFIGURATION Processing. SET_INTERFACE processing No : See Figure 11-21 SET_INTERFACE Processing. SET_FEATURE? No SET_CONFIGURATION? No SET_INTERFACE? No Other automatically processed request? Yes Automatic processing CPUDEC processing END END INTUSB0B/INTUSB2B active INTUSB2B = 1? Yes Reading UF0IS4 register No (n = 0, 1) Reading UF0ISn register SETINT = 1? (UF0IS4) Yes No CLRRQ = 1? (UF0IS0) No Yes Illegal processing SETRQ = 1? (UF0IS0) Yes Illegal processing No FW processing for SET_INTERFACE Reading UF0SET register Reading UF0CLR register SETINTC = 0 (UF0IC4) FW processing for each request FW processing for each request END END END Remark : Processing by hardware User's Manual U16031EJ4V1UD 697 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-18. CLEAR_FEATURE Processing UF0CLR register = 0XH Set the corresponding bit for the value of 0XH. The EPHALT bit of the UF0IS0 register is cleared to 0 only when all Halt Features are cleared. CLRRQ = 1 (UF0IS0) Clearing UF0DSTL register Clearing UF0EnSL register HALTn = 0 (UF0EPS2) Remarks 1. n = 0 to 4, 7, 8 2. : Processing by hardware 698 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-19. SET_FEATURE Processing UF0SET register = 0XH Set the corresponding bit for the value of 0XH. The EPHALT bit of the UF0IS0 register is not set to 1 by setting the UF0DSTL register. SETRQ = 1 (UF0IS0) Setting UF0DSTL register Setting UF0EnSL register HALTn = 1 (UF0EPS2) EPHALT = 1 (UF0IS0) Remarks 1. n = 0 to 4, 7, 8 2. : Processing by hardware User's Manual U16031EJ4V1UD 699 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-20. SET_CONFIGURATION Processing SETCON = 1 (UF0SET) SETRQ = 1 (UF0IS0) CONF = 1 (UF0MODS) Setting UF0CNF register Remark : Processing by hardware Figure 11-21. SET_INTERFACE Processing SETINT = 1 (UF0IS4) Setting UF0ASS register Setting UF0IFn register Remarks 1. n = 0 to 4 2. : Processing by hardware 700 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (3) CPUDEC request for control transfer The CPUDEC request can be classified into three types of processing: control transfer (write), control transfer (read), and control transfer (without data). Control transfer (write) indicates a request that uses the OUT transaction in the data stage (e.g., SET_DESCRIPTOR), and control transfer (read) indicates a request that uses the IN transaction in the data stage (e.g., GET_DESCRIPTOR). Control transfer (without data) indicates a request that has no data stage (e.g., SET_CONFIGURATION). The flowcharts are shown below. Figure 11-22. CPUDEC Request for Control Transfer (1/12) (a) Token phase (1/2) START INTUSB0B active G E Reading UF0ISn register CPUDEC = 1? (UF0IS1) Yes PROTC = 0 (UF0IC1) No Appropriate interrupt servicing STGM = 0 (UF0IM1) CPUDECM = 1 (UF0IM1) Reading UF0E0ST register x 8 times CPUDEC = 0 (UF0IS1) Decoding FW request A Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 701 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (2/12) (a) Token phase (2/2) A It is judged whether the request decoded by the device is supported. Request that uses control transfer (IN), such as GET_DESCRIPTOR String Supported request? Yes No Reading UF0ISn register Yes Control transfer (read)? No B Yes C PROT = 1? (UF0IS1) No SNDSTL = 1 (UF0SDS) In the case of an unsupported request for control transfer (write), clear the FIFO because data may be written to the FIFO as a result of OUT transfer before the STALL response is made. Yes E Request that uses control transfer (OUT), such as SET_DESCRIPTOR String Control transfer (write)? No D EP0RC = 1 (UF0FIC0) STGM = 1 (UF0IM1) CPUDECM = 0 (UF0IM1) STALL handshake response SETUP token received? Yes SNDSTL = 0 (UF0SDS) No END Remarks 1. n = 0, 1 2. : Processing by hardware 702 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (3/12) (b) Control transfer (read) (1/4) B IN token received? Yes Transmitting NAK No E0IN = 1 (UF0IS1) INTUSB0B active Reading UF0ISn register E0IN = 1? (UF0IS1) Yes E0INM = 1 (UF0IM1) No Illegal processing I Writing UF0E0W register If return data greater than the FIFO size exists, it is divided into FIFO size units and sequentially written, starting from the lowest data byte. F Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 703 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (4/12) (b) Control transfer (read) (2/4) F No FIFO full? Yes E0DED = 1 (UF0DEND) EP0NKW = 1 (UF0E0N) PROT = 1? (UF0IS1) No Yes EP0WC = 1 (UF0FIC0) G No IN token received? Yes Transmitting data of UF0E0W register No ACK received? Yes H Remark : Processing by hardware 704 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (5/12) (b) Control transfer (read) (3/4) H E0INDT = 1 (UF0IS1) EP0NKW = 0 (UF0E0N) INTUSB0B active Reading UF0ISn register E0INDT = 1? (UF0IS1) Yes No Illegal processing No transmit data? Yes E0INDTC = 0 (UF0IC1) No I Data of Null packet received? Yes STG = 1 (UF0IS1) No J Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 705 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (6/12) (b) Control transfer (read) (4/4) J INTUSB0B active Reading UF0ISn register STG = 1? (UF0IS1) Yes STGM = 1 (UF0IM1) No Illegal processing Transmitting ACK SUCES = 1 (UF0IS1) INTUSB0B active Reading UF0ISn register SUCES = 1? (UF0IS1) Yes SUCESC = 0 (UF0IC1) E0INC = 0 (UF0IC1) No Illegal processing CPUDECM = 0 (UF0IM1) E0INM = 0 (UF0IM1) END Remarks 1. n = 0, 1 2. : Processing by hardware 706 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (7/12) (c) Control transfer (write) (1/4) C OUT token received? Yes Writing UF0E0R register No Normal reception? Yes E0ODT = 1 (UF0IS1) EP0R = 1 (UF0EPS0) EP0NKR = 1 (UF0E0N) No Clearing UF0E0R register INTUSB0B active Reading UF0ISn register PROT = 1? (UF0IS1) No Yes EP0RC = 1 (UF0FIC0) K G Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 707 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (8/12) (c) Control transfer (write) (2/4) K E0ODT = 1? (UF0IS1) Yes Updating data length of UF0E0L register No Illegal processing Reading UF0E0R register UF0E0L register data is read up to the value read by the UF0E0R register. Data length other than 0? No E0ODT = 0 (UF0IS1) EP0R = 0 (UF0EPS0) EP0NKR = 0 (UF0E0N) Yes Data length = Data length - 1 Updating data length of UF0E0L register OUT token received? No Yes C IN token received? Yes L No Remark : Processing by hardware 708 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (9/12) (c) Control transfer (write) (3/4) L STG = 1 (UF0IS1) E0IN = 1 (UF0IS1) INTUSB0B active Reading UF0ISn register PROT = 1? (UF0IS1) No Yes Clearing read data G STG = 1? (UF0IS1) Yes Request processing No Illegal processing EP0WC = 1 (UF0FIC0) E0DED = 1 (UF0DEND) M Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 709 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (10/12) (c) Control transfer (write) (4/4) M STGM = 1 (UF0IM1) E0INM = 1 (UF0IM1) IN token received? Yes Transmitting data of Null packet No ACK received? Yes SUCES = 1 (UF0IS1) E0INDT = 1 (UF0IS1) No INTUSB0B active Reading UF0ISn register SUCES = 1? (UF0IS1) Yes SUCESC = 0 (UF0IC1) E0INDTC = 0 (UF0IC1) No Illegal processing CPUDECM = 0 (UF0IM1) END Remarks 1. n = 0, 1 2. : Processing by hardware 710 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (11/12) (d) Control transfer (without data stage) (1/2) D IN token of status phase IN token received? Yes E0IN = 1 (UF0IS1) STG = 1 (UF0IS1) No INTUSB0B active Reading UF0ISn register PROT = 1? (UF0IS1) No Yes Request processing aborted G STG = 1? (UF0IS1) Yes EP0WC = 1 (UF0FIC0) No Illegal processing E0DED = 1 (UF0DEND) N Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 711 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-22. CPUDEC Request for Control Transfer (12/12) (d) Control transfer (without data stage) (2/2) N E0INM = 1 (UF0IM1) STGM = 1 (UF0IM1) IN token received? Yes Transmitting data of Null packet No ACK received? Yes SUCES = 1 (UF0IS1) E0INDT = 1 (UF0IS1) No INTUSB0B active Reading UF0ISn register SUCES = 1? (UF0IS1) Yes SUCESC = 0 (UF0IC1) E0INC = 0 (UF0IC1) E0INDTC = 0 (UF0IC1) No Illegal processing Request processing E0INM = 1 (UF0IM1) CPUDECM = 0 (UF0IM1) END Remarks 1. n = 0, 1 2. : Processing by hardware 712 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (4) Processing for bulk transfer (IN) Bulk transfer (IN) is allocated to Endpoint1 and Endpoint3. The flowchart shown below illustrates how Endpoint1 is controlled. Endpoint3 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint3, therefore, read the bit names of Endpoint1 in the flowchart as those of Endpoint3. User's Manual U16031EJ4V1UD 713 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-23. Processing for Bulk Transfer (IN) (Endpoint1) START IN token received? Yes BKI1IN = 1 (UF0IS2) No Returning NAK INTUSB1B active Reading UF0ISn register BKI1IN = 1? (UF0IS2) Yes BKI1INM = 1 (UF0IM2) No Illegal processing Writing UF0BI1 register If return data greater than the FIFO size exists, it is divided into FIFO size units and sequentially written, starting from the lowest data byte. Yes FIFO full? No Yes Data error? No BKI1DED = 1 (UF0DEND) BKI1CC = 1 (UF0FIC0) BKI1NK = 1 (UF0EN) BKI1DT = 1 (UF0IS2) The timing of the bit value varies depending on the situation on the SIE side. Parallel processing by hardware : See Figure 11-24 Parallel Processing by Hardware. INTUSB1B active END Reading UF0ISn register BKI1DT = 1? (UF0IS2) Yes No transmit data? Yes BKI1INC = 0 (UF0IC2) BKI1DTC = 0 (UF0IC2) No Illegal processing No END Remarks 1. n = 2, 3 2. : Processing by hardware 714 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-24. Parallel Processing by Hardware IN token received? No Yes Transmitting data of UF0BI1 register ACK received? No Yes BKI1NK = 0 (UF0EN) No transmit data? No Yes Remark : Processing by hardware User's Manual U16031EJ4V1UD 715 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (5) Processing for bulk transfer (OUT) Bulk transfer (OUT) is allocated to Endpoint2 and Endpoint4. The flowchart shown below illustrates how Endpoint2 is controlled. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. 716 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-25. Normal Processing for Bulk Transfer (OUT) (Endpoint2) START OUT token received? Yes Writing UF0BO1 register No No Normal reception? Yes BKO1DT = 1 (UF0IS3) BKOUT1 = 1 (UF0EPS0) Clearing UF0BO1 register INTUSB1B active Reading UF0ISn register BKO1DT = 1? (UF0IS3) Yes Updating data length of UF0BO1L register No Illegal processing Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? No BKO1DT = 0 (UF0IS3) BKOUT1 = 0 (UF0EPS0) Yes Data length = Data length - 1 Updating data length of UF0BO1 register Data length = 0? Yes No Illegal processing Yes OUT token received? No END Remarks 1. n = 2, 3 2. : Processing by hardware User's Manual U16031EJ4V1UD 717 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) During bulk transfer (OUT), more data may be transmitted from the host than expected by the system. Endpoint2 and Endpoint4 for bulk transfer (OUT) of the V850E/ME2 consist of two 64-byte buffers so that NAK responses are suppressed as much as possible and data can be read from the CPU side even while the bus side is being accessed as the transfer rate of the USB bus increases. Consequently, if the host sends more data than expected by the system, up to 128 bytes of extra data may be automatically received in the worst case. In this case, change the control flow from that of the normal processing of Endpoint2 and Endpoint4 to the flow illustrated below when the quantity of data expected by the system has decreased to two packets. This flowchart illustrates how Endpoint2 is controlled. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. 718 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-26. Processing If More Data Than Expected by System Is Transmitted (Endpoint2) (1/2) START OUT token received? No Yes Writing UF0BO1 register Normal reception? No Yes Clearing UF0BO1 register BKO1DT = 1 (UF0IS3) BKOUT1 = 1 (UF0EPS0) INTUSB1B active OUT token received? No Yes Writing UF0BO1 register Normal reception? No Yes Clearing UF0BO1 register BKO1FL = 1 (UF0IS3) BKO1NK = 1 (UF0EN) Reading UF0ISn register BKO1FL = 1? (UF0IS3) No Yes BKO1NKM = 1 (UF0ENM) Illegal processing BKO1NK = 1 (UF0EN) Updating data length of UF0BO1L register I Remarks 1. n = 2, 3 2. : Processing by hardware User's Manual U16031EJ4V1UD 719 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-26. Processing If More Data Than Expected by System Is Transmitted (Endpoint2) (2/2) I Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? Yes No Data length = Data length - 1 BKO1FL = 0 (UF0IS3) Updating data length of UF0BO1L register Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? Yes No Data length = Data length - 1 BKO1DT= 0 (UF0IS3) BKOUT1 = 0 (UF0EPS0) OUT token received? No Yes Next system sequence? BKO1NAK = 1 (UF0IS3) No Yes BKO1NKM = 0 (UF0ENM) NAK response INTUSB1B active BKO1NK = 0 (UF0EN) BKO1NAK = 1? (UF0IS3) No Expected system sequence processing Yes Illegal processing END Expected processing such as Endpoint STALL BKO1NKM = 0 (UF0ENM) BKO1NK = 0 (UF0EN) BKO1NAKC = 0 (UF0IC3) END Remark : Processing by hardware 720 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) (6) Processing for interrupt transfer (IN) Interrupt transfer (IN) is allocated to Endpoint7 and Endpoint8. The flowchart shown below illustrates how Endpoint7 is controlled. Endpoint8 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint8, therefore, read the bit names of Endpoint7 in the flowchart as those of Endpoint8. User's Manual U16031EJ4V1UD 721 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-27. Processing for Interrupt Transfer (IN) (Endpoint7) START Reading UF0EPS0 register IT1 = 0? (UF0EPS0) No Yes Writing UF0INT1 register FIFO full? Yes No Data error? Yes No IT1DEND = 1 (UF0DEND) ITR1C = 1 (UF0FIC0) IT1NK = 1 (UF0EN) IN token received? No Yes Transmitting data of UF0INT1 register ACK received? No Yes IT1DT = 1 (UF0IS2) IT1 = 0 (UF0EPS0) IT1NK = 0 (UF0EN) INTUSB1B active Reading UF0ISn register IT1DT = 1? (UF0IS2) No Yes No Illegal processing No transmit data? Yes IT1DTC = 0 (UF0IC2) END Remarks 1. n = 2, 3 2. : Processing by hardware 722 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.4 Suspend/Resume processing How Suspend/Resume processing is performed differs depending on the configuration of the system. example is given below. Figure 11-28. Example of Suspend/Resume Processing (1/3) One (a) Example of Suspend processing START Suspend detected? No Yes RSUSPD = 1 (UF0IS0) RSUM = 1 (UF0EPS1) INTUSB0B active Reading UF0ISn register RSUSPD = 1? (UF0IS0) No Yes Reading UF0EPS1 register Illegal processing RSUM = 1? (UF0EPS1) No Yes FW Suspend processing Illegal processing RSUSPDC = 0 (UF0IC0) END Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 723 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-28. Example of Suspend/Resume Processing (2/3) (b) Example of Resume processing START Resume detected? No Yes RSUSPD = 1 (UF0IS0) RSUM = 0 (UF0EPS1) INTUSB0B active Reading UF0ISn register RSUSPD = 1? (UF0IS0) No Yes Reading UF0EPS1 register Illegal processing RSUM = 0? (UF0EPS1) No Yes FW Resume processing Illegal processing RSUSPDC = 0 (UF0IC0) END Remarks 1. n = 0, 1 2. : Processing by hardware 724 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-28. Example of Suspend/Resume Processing (3/3) (c) Example of Resume processing (when supply of USB clock to USBF is stopped) START Resume detected? No Yes INTRSUM active Executing interrupt servicing Supplying USB clock FW Resume processing END Remark : Processing by hardware User's Manual U16031EJ4V1UD 725 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.5 Processing after power application The processing to be performed after power application differs depending on the configuration of the system. One example is given below. Figure 11-29. Example of Processing After Power Application/Power Failure (1/3) (a) Processing after power application (1/2) START START Pull-up processing of D+ inactiveNote 1 Initialization of request data register area Initialization of request data register area : See Figure 11-13 Initialization of Request Data Register Area. : See Figure 11-13 Initialization of Request Data Register Area. Controlling portNote 2 Controlling portNote 2 Pull-up processing of D+ activeNote 1 Connection Resume detected? No Yes BUSRST = 1 (UF0IS0) DFLT = 1 (UF0MODS) (a) Notes 1. Use one general-purpose port pin for the signal that controls switching of the pull-up resistor of the USB bus. 2. The input mode or control mode of the general-purpose port pin allocated in Note 1 may be selected as the default value. Note the active level of pull-up processing of D+ on power application. Remark : Processing by hardware 726 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-29. Example of Processing After Power Application/Power Failure (2/3) (a) Processing after power application (2/2) (a) Receiving GET_DESCRIPTOR Device request MPACK = 1 (UF0MODS) Receiving SET_ADDRESS request Setting UF0ADRS register Receiving SET_CONFIGURATION 1 request SETCON = 1 (UF0SET) SETRQ = 1 (UF0IS0) CONF = 1 (UF0MODS) UF0CNF register = 03H Valid endpoint = DATA0 Receiving SET_INTERFACE request SETINT = 1 (UF0IS4) Setting of UF0ASS register Setting of UF0IFm register Valid endpoint = DATA0 Processing continues Remarks 1. m = 0 to 4 2. : Processing by hardware User's Manual U16031EJ4V1UD 727 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-29. Example of Processing After Power Application/Power Failure (3/3) (b) Processing on power failure START Power failure INTPxx activeNote? Yes Interrupt servicing No Processing such as clearing FIFO or MRST = 1 (UF0GPR) END Note INTPxx means an external interrupt pin of the V850E/ME2 (INTP10, INTP11, INTP21 to INTP25, INTP50 to INTP52, INTP65 to INTP67, INTPD0 to INTPD15, INTPL0, INTPL1, INTPC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, and INTPC31). Allocate one external interrupt pin to the following applications. * Detecting disconnection of the connector in the case of self-powered mode (SFPW bit of UF0DSTL register = 1). In this case, monitor the VDD line of the USB connector, and input the result to the external interrupt pin at the edge. For the noise elimination time, see Table 14-1 Noise Elimination Time of Interrupt Input Pins and Table 14-3 Noise Elimination Time of Timer C and Timer ENC1 Input Pins. * Detecting turning off power from a HUB chip when the device is mounted on the same board as a HUB. Remark : Processing by hardware 728 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.6 Receiving data for bulk transfer (OUT) in DMA mode Bulk transfer (OUT) is allocated to Endpoint2 and Endpoint4. The flowchart shown below illustrates how Endpoint2 is controlled when DMA is used. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. The control flowchart shown below illustrates how remaining data is read by the CPU. If data for bulk transfer (OUT) has been correctly received by setting the DQBO1MS bit of the UF0IDR register to 1, the DMA request signal for Endpoint2, instead of an interrupt request (INTUSB1B), becomes active. This DMA request signal for Endpoint2 operates according to the setting of the MODEn bit of the UF0IDR register (n = 0, 1). If all the data stored in the UF0BO1 register has been read by DMA, the DMA request signal for Endpoint2 becomes inactive. In this status, if data for the next bulk transfer (OUT) has been correctly received, the DMA request signal for Endpoint2 becomes active again. If the data for bulk transfer (OUT) that has been received is equal to or less than the FIFO size, a Short interrupt request is issued and the USBSP2B signal becomes active, as soon as reading the data by DMA is completed. As a result, the DQBO1MS bit of the UF0IDR register is cleared to 0, and the DMA request signal for Endpoint2 becomes inactive. To read data by DMA again, set the DQBO1MS bit to 1 again. If DMA is completed by the DMA end signal for Endpoint2, the DQBO1MS bit of the UF0IDR register is cleared to 0, and the DMA request signal for Endpoint2 becomes inactive. At the same time, the DMA_END interrupt request is issued. If data remains in the UF0BO1 register at this time, DMA can be started again by setting the DQBO1MS bit of the UF0IDR register again. However, the data for bulk transfer (OUT) is always equal to or less than the FIFO size. Consequently, a Short interrupt request is issued, the USBSP2B signal becomes active, the DQBO1MS bit is cleared, and the DMA request signal for Endpoint2 becomes inactive, as soon as the data is read by DMA. Cautions 1. The DMA request signal for Endpoint n (n = 2, 4) becomes active in the demand mode (MODE1 and MODE0 bits of the UF0IDR register = 10), as long as there is data to be transferred. 2. The DMA request signal for Endpoint n (n = 2, 4) becomes active in the single mode (MODE1 and MODE0 bits of the UF0IDR register = 0X (X: don't care)) if there is data to be transferred, but this signal becomes inactive each time one byte has been transferred. This operation is repeated until there is no more data to be transferred. User's Manual U16031EJ4V1UD 729 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-30. DMA Processing by Bulk Transfer (OUT) (1/3) START (4) (3) MODE1, MODE0 = 10: Demand mode MODE1, MODE0 = 0X: Single mode (X = Don't care) Setting of MODEx (UF0IDR) DQBO1MS = 1 (UF0IDR) OUT token received? No Yes Writing UF0BO1 register Normal reception? No Yes BKO1DT = 1 (UF0IS3) BKOUT1 = 1 (UF0EPS0) DQE2 = 1 (UF0DMS0) Clearing UF0BO1 register DMA request for Endpoint2 active Reading all data in UF0BO1 register by DMA TC signal received? Yes (1) No UF0BO1 register data is read up to the value read by the UF0BO1L register. How many times is data length? No Yes BKO1DT = 0 (UF0IS3) BKOUT1 = 0 (UF0EPS0) DQE2 = 0 (UF0DMS0) MaxPacket? Yes No (2) Remark : Processing by hardware 730 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-30. DMA Processing by Bulk Transfer (OUT) (2/3) (2) DEDE2 = 1 (UF0DMS1) SHORT = 1 (UF0IS0) DQBO1MS = 0 (UF0IDR) INTUSB0B active DMA request for Endpoint2 inactive Reading UF0ISn register SHORT = 1? (UF0IS0) No Yes Reading UF0DMSn register Illegal processing DSPE2 = 1? (UF0DMS1) No Yes SHORTC = 0 (UF0IC0) Illegal processing Correct processing (3) Remarks 1. n = 0, 1 2. : Processing by hardware User's Manual U16031EJ4V1UD 731 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-30. DMA Processing by Bulk Transfer (OUT) (3/3) (1) DQE2 = 0 (UF0DMS0) DEDE2 = 1 (UF0DMS1) DMAED = 1 (UF0IS0) DQBO1MS = 0 (UF0IDR) INTUSB0B active DMA request for Endpoint2 inactive Reading UF0ISn register DMAED = 1? (UF0IS0) Yes Reading UF0DMSn register No Illegal processing DEDE2 = 1? (UF0DMS1) Yes Reading UF0ISm register No Illegal processing BKO1DT = 1? (UF0IS3) Yes Updating data length of UF0BO1L register No Reading UF0BO1 register UF0BO1 register data is read up to the value read by the UF0BO1L register. Data length other than 0? No Yes Data length = Data length - 1 BKO1DT = 0 (UF0IS3) BKOUT1 = 0 (UF0EPS0) DMAEDC = 0 (UF0IC0) (4) Remarks 1. n = 0, 1 m = 2, 3 2. : Processing by hardware 732 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.7 Transmitting data for bulk transfer (IN) in DMA mode Bulk transfer (IN) is allocated to Endpoint1 and Endpoint3. The flowchart shown below illustrates how Endpoint1 is controlled when DMA is used. Endpoint3 can also be controlled in the same sequence. To use this flowchart as the control flow of Endpoint3, therefore, read the bit names of Endpoint1 in the flowchart as those of Endpoint3. If data for bulk transfer (IN) can be written by setting the DQBI1MS bit of the UF0IDR register to 1, the DMA request signal for Endpoint1, instead of an interrupt request (INTUSB1B), becomes active. This DMA request signal for Endpoint1 operates according to the setting of the MODEn bit of the UF0IDR register (n = 0, 1). If all the data that can be written to the UF0BI1 register has been written by DMA, the DMA request signal for Endpoint1 becomes inactive. In this status, the toggle operation of the FIFO takes place and, if data for bulk transfer (IN) can be written, the DMA request signal for Endpoint1 becomes active again. The automatic toggle operation of the FIFO is not executed even if the FIFO has become full as a result of DMA transfer, unless the BKI1T bit of the UF0DEND register is set to 1. Therefore, be sure to set the BKI1DED bit of the UF0DEND register to 1 to transfer data. If DMA is completed by the DMA end signal for Endpoint1, the DQBI1MS bit of the UF0IDR register is cleared to 0, and the DMA request signal for Endpoint1 becomes inactive. At the same time, the DMA_END interrupt request is issued. To transmit a short packet at this time when the FIFO is not full, set the BKI1DED bit of the UF0DEND register to 1. Cautions 1. The DMA request signal for Endpoint n (n = 1, 3) becomes active in the demand mode (MODE1 and MODE0 bits of the UF0IDR register = 10), as long as data can be transferred. 2. The DMA request signal for Endpoint n (n = 1, 3) becomes active in the single mode (MODE1 and MODE0 bits of the UF0IDR register = 0X (X: don't care)) if data can be transferred, but this signal becomes inactive each time one byte has been transferred. This operation is repeated until there is no more data to be transferred. User's Manual U16031EJ4V1UD 733 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-31. DMA Processing by Bulk Transfer (IN) (1/4) START (5) Setting of MODEx (UF0IDR) DQBI1MS = 1 (UF0IDR) MODE1, MODE0 = 10: Demand mode MODE1, MODE0 = 0X: Single mode (X = Don't care) (3) FIFO on CPU side full? Yes No DQE1 = 1 (UF0DMS0) DMA request for Endpoint1 active If return data greater than the FIFO size exists, it is divided into FIFO size units, and sequentially written, starting from the lowest data byte. Writing UF0BI1 register by DMA TC signal received? Yes (1) No FIFO full? No Yes BKI1T = 1? (UF0DEND) No Yes (2) Remark : Processing by hardware 734 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-31. DMA Processing by Bulk Transfer (IN) (2/4) (2) BKI1NK = 1 (UF0EN)Note BKI1DT = 1 (UF0IS2)Note DQE1 = 0 (UF0DMS0) DMA request for Endpoint1 inactive (3) Parallel processing by hardware : See Figure 11-24 Parallel Processing by Hardware. END Note The timing of the bit value changes depending on the status on the SIE side. Remark : Processing by hardware User's Manual U16031EJ4V1UD 735 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-31. DMA Processing by Bulk Transfer (IN) (3/4) (1) FIFO full? No Yes BKI1T = 1? (UF0DEND) No Yes BKI1NK = 1 (UF0EN)Note BKI1DT = 1 (UF0IS2)Note DQE1 = 0 (UF0DMS0) DEDE1 = 1 (UF0DMS1) DMAED = 1 (UF0IS0) DQBI1MS = 0 (UF0IDR) DQE1 = 0 (UF0DMS0) DEDE1 = 1 (UF0DMS1) DMAED = 1 (UF0IS0) DQBI1MS = 0 (UF0IDR) INTUSB0B active DMA request for Endpoint1 inactive Reading UF0ISn register DMAED = 1? (UF0IS0) No Yes Reading UF0DMSn register Illegal processing DEDE1 = 1? (UF0DMS1) No Yes Illegal processing (4) Note The timing of the bit value changes depending on the status on the SIE side. Remarks 1. n = 0, 1 2. : Processing by hardware 736 User's Manual U16031EJ4V1UD CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Figure 11-31. DMA Processing by Bulk Transfer (IN) (4/4) (4) FIFO full? No Yes BKI1T = 1? (UF0DEND) No Yes Data error? Yes DMAEDC = 0 (UF0IC0) No (5) Parallel processing by hardware : See Figure 11-24 Parallel Processing by Hardware. BKI1DED = 1 (UF0DEND) BKI1CC = 1 (UF0FIC0) BKI1NK = 1 (UF0EN)Note BKI1DT = 1 (UF0IS2)Note DMAEDC = 0 (UF0IC0) END (5) Note The timing of the bit value changes depending on the status on the SIE side. Remark : Processing by hardware User's Manual U16031EJ4V1UD 737 CHAPTER 11 USB FUNCTION CONTROLLER (USBF) 11.7.8 USB connection example Figure 11-32. USB Connection Example UVDD UVDD V850E/ME2 P50 IC2 IC1 INTP51 UDP UDM 1.5 k 5 % VBUS 24 5 % 24 5 % D+ D- USB connector (1) Pull-up control of D+ To prohibit connection report (D+ pull-up) to the USB host/HUB (such as while higher priority processing or initialization processing is under execution), the system must control pulling up of D+ via a general-purpose port. As shown in the circuit example in Figure 11-32, control the pull-up control signal of D+ and VBUS input signal by using a general-purpose port and USB cable VBUS (AND circuit). In Figure 11-32, pulling up D+ is prohibited when the general-purpose port is high level (secure the high level of the general-purpose port pin by pulling it up because the port pin is in the input mode by default). Use an IC to which power can be applied when the system power supply is off as IC2 shown in Figure 11-32. (2) Detecting USB cable connection/disconnection The USB function controller (USBF) requires a VBUS input signal that recognizes connection and disconnection, because the state of USBF is managed by hardware. Voltage (5 V) is applied from the USB host/HUB as the VBUS input signal if the USB cable VBUS is connected to the USB host/HUB when power to the USBF is turned off. Therefore, use an IC to which power can be applied when the system power supply is off as IC1 shown in Figure 11-32. When disconnecting the USB cable in the circuit example in Figure 11-32, a signal input to INTP51 may be unstable while the VBUS voltage is dropping. Therefore, it is recommended to use a Schmitt buffer for IC1. 738 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER 12.1 Features * Analog input: 8 channels * 10-bit A/D converter * On-chip A/D conversion result register (ADCR0 to ADCR7) 10 bits x 8 * A/D conversion trigger mode A/D trigger mode Timer trigger mode External trigger mode * Successive approximation method User's Manual U16031EJ4V1UD 739 CHAPTER 12 A/D CONVERTER 12.2 Configuration The A/D converter of the V850E/ME2 adopts the successive approximation method, and uses A/D converter mode registers 0, 1, 2 (ADM0, ADM1, ADM2), and the A/D conversion result register (ADCR0 to ADCR7) to perform A/D conversion operations. (1) Input circuit The input circuit selects the analog input (ANI0 to ANI7) according to the mode set by the ADM0, ADM1, and ADM2 registers. (2) C-Array Holds the charge of the differential voltage between the voltage input from the analog input pins (ANI0 to ANI7) and the reference voltage (1/2 AVDD), and redistributes the sampled charges. (3) C-Dummy This block holds the reference voltage (1/2 AVDD) and assigns the reference of the comparator input. (4) Voltage comparator The voltage comparator compares the C-Array comparison potential with the C-Dummy reference potential. (5) A/D conversion result register n (ADCRn), A/D conversion result register nH (ADCRnH) ADCRn is a 10-bit register that holds A/D conversion results. Each time A/D conversion is completed, the conversion results are loaded from the successive approximation register (SAR). RESET input makes this register undefined. (6) ANI0 to ANI7 pins These are 8-channel analog input pins for the A/D converter. They input the analog signals to be A/D converted. Caution Make sure that the voltages input to ANI0 to ANI7 do not exceed the rated values. If a voltage higher than AVDD or lower than AVSS (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined, and the conversion values of the other channels may also be affected. (7) AVREFM and AVREFP pins This is the pin for inputting the reference voltage of the A/D converter. It converts signals input to the ANI0 to ANI7 pins to digital signals based on the voltage applied between AVREFM and AVREFP. (8) AVSS pin This is the ground pin of the A/D converter. Always use this pin at the same potential as that of the EVSS pin even when the A/D converter is not used. (9) AVDD pin This is the analog power supply pin of the A/D converter. Always use this pin at the same potential as that of the EVDD pin even when the A/D converter is not used. 740 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER Figure 12-1. Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input circuit Comparator C-Dummy C-Array AVREFM AVREFP AVDD AVSS fX/8 ADTRG INTCCC40 INTCCC41 INTCCC50 INTCCC51 Edge detection Trigger selector ADTRG Controller TTRG Successive approximation register (SAR) A/D conversion result register (ADCRn, ADCRnH) INTAD Remarks 1. fX: Main clock 2. n = 0 to 7 Cautions 1. If there is noise at the analog input pins (ANI0 to ANI7) or at the reference voltage input pin (AVREFP, AVREFM), that noise may generate an illegal conversion result. Software processing will be needed to avoid a negative effect on the system from this illegal conversion result. An example of this software processing is shown below. * Take the average result of a number of A/D conversions and use that as the A/D conversion result. * Execute a number of A/D conversions consecutively and use those results, omitting any exceptional results that may have been obtained. 2. Do not apply a voltage outside the AVREFM to AVREFP range to the pins that are used as A/D converter input pins. User's Manual U16031EJ4V1UD 741 CHAPTER 12 A/D CONVERTER 12.3 Control Registers (1) A/D converter mode register 0 (ADM0) The ADM0 register is an 8-bit register that specifies the operation mode, and executes conversion operations. This register can be read or written in 8-bit or 1-bit units. However, bit 6 can only be read. Writing this bit is ignored. Cautions 1. When the ADCE bit is 1 in the timer trigger mode and external trigger mode, the trigger signal standby state is set. To clear the ADCE bit, write 0 or reset. In the A/D trigger mode, the conversion trigger is set by writing 1 to the ADCE bit. After the operation, when the mode is changed to the timer trigger mode or external trigger mode without clearing the ADCE bit, the trigger input standby state is set immediately after changing the register. 2. Changing the setting of the BS and MS bits is prohibited while A/D conversion is enabled (ADCE bit = 1). 3. When data is written to the ADM0 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning. <7> <6> 5 BS 4 MS 3 0 2 0 1 0 0 0 Address FFFFF200H After reset 00H ADM0 ADCE ADCS Bit position 7 Bit name ADCE Function Enables or disables A/D conversion operation. 0: Disabled 1: Enabled 6 ADCS Indicates the status of A/D converter. This bit is read only. 0: Stopped 1: Operating 5 BS Specifies buffer mode in the select mode. 0: 1-buffer mode 1: 4-buffer mode 4 MS Specifies operation mode of A/D converter. 0: Scan mode 1: Select mode 742 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER (2) A/D converter mode register 1 (ADM1) The ADM1 register is an 8-bit register that specifies the conversion operation time and trigger mode. This register can be read or written in 8-bit or 1-bit units. Cautions 1. Changing the setting of the EGA1, EGA0, and FR3 to FR0 bits is prohibited while A/D conversion is enabled (ADCE bit = 1 in the ADM0 register). 2. When data is written to the ADM1 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning. 7 ADM1 EGA1 6 EGA0 5 TRG1 4 TRG0 3 FR3 2 FR2 1 FR1 0 FR0 Address FFFFF201H After reset 00H Bit position 7, 6 Bit name EGA1, EGA0 Specify valid edge of ADTRG. EGA1 0 0 1 1 EGA0 0 1 0 1 Function ADTRG valid edge specification No edge detected (does not operate as external trigger) Falling edge detected Rising edge detected Both edges detected 5, 4 TRG1, TRG0 Specify the trigger mode. TRG1 0 0 1 1 TRG0 0 1 0 1 A/D trigger mode Timer trigger mode External trigger mode Setting prohibited Trigger mode Remark Sets A/D conversion operation time by using bits FR3 to FR0. For details, see Table 12-1. User's Manual U16031EJ4V1UD 743 CHAPTER 12 A/D CONVERTER Table 12-1. Setting of A/D Conversion Operation Time FR3 FR2 FR1 FR0 Number of Conversion Clocks 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128 256 384 512 640 768 896 1,024 1,152 1,280 1,408 1,536 1,664 1,792 1,920 2,048 Setting prohibited Setting prohibited 2.56 s 3.42 s 4.27 s 5.12 s 5.98 s 6.83 s 7.68 s 8.54 s 9.39 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 2.89 s 3.85 s 4.82 s 5.78 s 6.74 s 7.70 s 8.67 s 9.63 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 2.56 s 3.84 s 5.12 s 6.40 s 7.68 s 8.96 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 3.20 s 4.80 s 6.40 s 8.00 s 9.60 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 64/fX 128/fX 160/fX 160/fX 160/fX 160/fX 160/fX 160/fX 160/fX 160/fX 160/fX - - - - - fX = 150 MHz Conversion Operation TimeNote 1 fX = 133 MHz fX = 100 MHz fX = 80 MHz A/D Stabilization TimeNote 2 Notes 1. 2. Set the conversion operation time in the range of 2 to 10 s (target value). After the ADCE bit is set to "1" from "0" to secure the stabilization time of the A/D converter, conversion is started after the A/D stabilization time has elapsed only before the first A/D conversion is executed. Cautions 1. Do not change the set value of the A/D conversion time (FR3 to FR0 bits) during an A/D conversion operation (ADCE bit = 1). To change the value, clear the ADCE bit to 0. 2. When the trigger mode (TRG1 and TGR0 bits) is changed midway, A/D conversion can be started immediately without having to secure the A/D stabilization time by re-setting the ADCE bit to "1". Remark fX: Main clock 744 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER (3) A/D converter mode register 2 (ADM2) The ADM2 register is an 8-bit register that specifies the analog input pin of the A/D converter. This register can be read or written in 8-bit or 1-bit units. Cautions 1. If a channel for which no analog input pin exists is specified, the result of A/D conversion is undefined. 2. Changing the setting of the ANIS2 to ANIS0 bits is prohibited while A/D conversion is enabled (ADCE bit = 1 in the ADM0 register). 3. When data is written to the ADM2 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning. 7 ADM2 0 6 0 5 0 4 0 3 0 2 ANIS2 1 ANIS1 0 Address FFFFF202H After reset 00H ANIS0 Bit position 2 to 0 Bit name ANIS2 to ANIS0 Function Specify the analog input pin for A/D conversion. ANIS2 ANIS1 ANIS0 Specification of pin for A/D conversion Select mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI0 ANI0, ANI1 ANI0 to ANI2 ANI0 to ANI3 ANI0 to ANI4 ANI0 to ANI5 ANI0 to ANI6 ANI0 to ANI7 Scan mode User's Manual U16031EJ4V1UD 745 CHAPTER 12 A/D CONVERTER (4) ADC trigger select register (ADTS) This is an 8-bit register that specifies the timer trigger signal in the timer trigger mode. This register can be read or written in 8-bit units. Be sure to clear bits 7 to 4 to 0. If they are set to 1, the operation is not guaranteed. Caution Stop the A/D conversion operation (by clearing the ADCE bit of the ADM0 register to 0) before changing the setting of the ADTS register. The operation is not guaranteed if the setting of the ADTS register is changed while A/D conversion is enabled (ADCE bit = 1). 7 ADTS 0 6 0 5 0 4 0 <3> TMS3 <2> TMS2 <1> TMS1 <0> Address FFFFF220H After reset 00H TMS0 Bit position 3 Bit name TMS3 Function Controls connection of a timer trigger signal (INTCCC51). 0: Timer trigger of ADC is invalid. 1: Timer trigger of ADC is valid. 2 TMS2 Controls connection of a timer trigger signal (INTCCC50). 0: Timer trigger of ADC is invalid. 1: Timer trigger of ADC is valid. 1 TMS1 Controls connection of a timer trigger signal (INTCCC41). 0: Timer trigger of ADC is invalid. 1: Timer trigger of ADC is valid. 0 TMS0 Controls connection of a timer trigger signal (INTCCC40). 0: Timer trigger of ADC is invalid. 1: Timer trigger of ADC is valid. 746 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER (5) A/D conversion result registers 0 to 7, 0H to 7H (ADCR0 to ADCR7, ADCR0H to ADCR7H) The ADCRn register is a 10-bit register holding the A/D conversion results. There are eight 10-bit registers. These registers are read-only, in 16-bit or 8-bit units. During 16-bit access, the ADCRn register is specified, and during higher 8-bit access, the ADCRnH register is specified (n = 0 to 7). When reading the 10-bit data of the A/D conversion results from the ADCRn register, only the higher 10 bits are valid and the lower 6 bits are always read as 0. 15 14 13 12 11 10 9 8 7 6 5 0 4 0 3 0 2 0 1 0 0 0 Address After reset ADCRn ADn9 ADn8 ADn7 ADn6 ADn5 ADn4 ADn3 ADn2 ADn1 ADn0 FFFFF210H to Undefined FFFFF21EH 7 6 5 4 3 2 1 0 Address After reset ADCRnH ADn9 ADn8 ADn7 ADn6 ADn5 ADn4 ADn3 ADn2 FFFFF211H to Undefined FFFFF21FH Remark n = 0 to 7 The correspondence between each analog input pin and the ADCRn register is shown below. Analog Input Pin ADCRn Register Select 1 Buffer Mode/ Scan Mode ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADCR0, ADCR0H ADCR1, ADCR1H ADCR2, ADCR2H ADCR3, ADCR3H ADCR4, ADCR4H ADCR5, ADCR5H ADCR6, ADCR6H ADCR7, ADCR7H ADCR4 to ADCR7, ADCR4H to ADCR7H ADCR0 to ADCR3, ADCR0H to ADCR3H Select 4 Buffer Mode User's Manual U16031EJ4V1UD 747 CHAPTER 12 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (of the A/D conversion result register n (ADCRn)) is as follows: SAR = INT ( VIN AVREF x 1,024 + 0.5) ADCRNote = SAR x 64 or, (SAR - 0.5) x AVREF 1,024 VIN < (SAR + 0.5) x AVREF 1,024 INT( ): Function that returns the integer of the value in ( ) VIN: Analog input voltage AVREF: AVREFM, AVREFP pin voltage ADCR: Value of A/D conversion result register n (ADCRn) Note The lower 6 bits of the ADCRn registers are fixed to 0. Figure 12-2 shows the relationship between the analog input voltage and the A/D conversion results. Figure 12-2. Relationship Between Analog Input Voltage and A/D Conversion Results SAR ADCRn 1,023 FFC0H 1,022 FF80H A/D conversion results (ADCRn) 1,021 FF40H 3 00C0H 2 0080H 1 0040H 0 0000H 1 3 2 5 3 1 2,048 1,024 2,048 1,024 2,048 1,024 2,043 1,022 2,045 1,023 2,047 2,048 1,024 2,048 1,024 2,048 1 Input voltage/AVREFP, AVREFM Remark n = 0 to 7 748 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER 12.4 Operation 12.4.1 Basic operation A/D conversion is executed by the following procedure. (1) The selection of the analog input and specification of the operation mode, trigger mode, etc. should be specified using the ADMn registerNote 1 (n = 0 to 2). When the ADCE bit of the ADM0 register is set to 1, A/D conversion starts in the A/D trigger mode. In the timer trigger mode and external trigger mode, the trigger standby stateNote 2 is set. (2) When A/D conversion is started, the C array voltage on the analog input side and the C array voltage on the reference side are compared by the comparator. (3) When the comparison of the 10 bits ends, the conversion results are stored in the ADCRn register. When A/D conversion has been performed the specified number of times, the A/D conversion end interrupt (INTAD) is generated (n = 0 to 7). Notes 1. If the setting of the ADMn register (n = 0 to 2) is changed during A/D conversion, the operation immediately before is stopped, and the result of the conversion is not stored in the ADCRn register (n = 0 to 7). The A/D conversion operation is then initialized, and conversion is executed from the beginning again. 2. During the timer trigger mode and external trigger mode, if the ADCE bit of the ADM0 register is set to 1, the mode changes to the trigger standby state. The A/D conversion operation is started by the trigger signal (ADCS bit = 1 in the ADM0 register), and the trigger standby state (ADCS bit = 0) is returned when the A/D conversion operation ends. User's Manual U16031EJ4V1UD 749 CHAPTER 12 A/D CONVERTER 12.4.2 Operation mode and trigger mode Various conversion operations can be specified for the A/D converter by specifying the operation mode and trigger mode. The operation mode and trigger mode are set by the ADM0 to ADM2 registers. The following shows the relationship between the operation mode and trigger mode. Table 12-2. Relationship Between Operation Mode and Trigger Mode Trigger Mode Operation Mode ADM0 A/D trigger Select 1 buffer 4 buffers Scan Timer trigger Select 1 buffer 4 buffers Scan External trigger Select 1 buffer 4 buffers Scan xx010000B xx110000B xxx00000B xx010000B xx110000B xxx00000B xx010000B xx110000B xxx00000B xx10xxxxB 00001xxxB Set Value ADM1 00000xxxB ADM2 00000xxxB 00000xxxB 00000xxxB 00000xxxB 00000xxxB 00000xxxB 00000xxxB 00000xxxB 00000xxxB ANI0 to ANI7 ANI0 to ANI7 ANI0 to ANI7 ANI0 to ANI7 ANI0 to ANI7 ANI0 to ANI7 ANI0 to ANI7 ANI0 to ANI7 ANI0 to ANI7 Analog Input (1) Trigger mode There are three types of trigger modes that serve as the start timing of A/D conversion processing: A/D trigger mode, timer trigger mode, and external trigger mode. These trigger modes are set by the TRG1 and TRG0 bits of the ADM1 register. (a) A/D trigger mode This mode starts the conversion timing of the analog input set to the ANI0 to ANI7 pins, and by setting the ADCE bit of the ADM0 register to 1, starts A/D conversion. Unless the ADCE bit is cleared to 0 after conversion, the next conversion operation is repeated. If data is written to the ADM0 to ADM2 registers during conversion, conversion is stopped and then executed from the beginning again. (b) Timer trigger mode This mode specifies the conversion timing of the analog input set for the ANI0 to ANI7 pins using the values set to the timer C capture/compare register. This register creates the analog input conversion timing by generating the compare match interrupts of the four capture/compare registers (CCC40, CCC41, CCC50, CCC51) connected to the 16-bit timer C (TMC4, TMC5). If the ADCE bit of the ADM0 register is set to 1, the A/D converter waits for an interrupt (INTCCC40, INTCCC41, INTCCC50, or INTCCC51), and starts conversion when INTCCC40, INTCCC41, INTCCC50, or INTCCC51 occurs (ADCS bit = 1 in the ADM0 register). When conversion has finished, the converter waits for an interrupt again (ADCS = 0). If data is written to the ADM0 to ADM2 registers during conversion, conversion is stopped and then executed from the beginning again. 750 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER (c) External trigger mode This mode specifies the conversion timing of the analog input to the ANI0 to ANI7 pins using the ADTRG pin. The EGA1 and EGA0 bits of the ADM1 register are used to specify the valid edge to be input to the ADTRG pin. When the ADCE bit of the ADM0 register is set to 1, the A/D converter waits for an external trigger (ADTRG), and starts conversion when the valid edge of ADTRG is detected (ADCS bit = 1 in the ADM0 register). When the converter has completed its conversion operation, it waits for an external trigger again (ADCS bit = 0). If the valid edge is detected at the ADTRG pin during conversion, conversion is executed from the beginning again. If data is written to the ADM0 to ADM2 registers during conversion, conversion is stopped and then executed from the beginning again. (2) Operation mode There are two operation modes that set the ANI0 to ANI7 pins: select mode and scan mode. The select mode has sub-modes that consist of 1-buffer mode and 4-buffer mode. These modes are set by the BS and MS bits of the ADM0 register. (a) Select mode In this mode, one analog input specified by the ADM2 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input (ANIn). For this mode, the 1-buffer mode and 4-buffer mode are provided for storing the A/D conversion results (n = 0 to 7). * 1-buffer mode In this mode, one analog input specified by the ADM2 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input (ANIn) (n = 0 to 7). The ANIn and ADCRn register correspond one to one, and an A/D conversion end interrupt (INTAD) is generated each time one A/D conversion ends. After conversion has finished, the next conversion operation is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. User's Manual U16031EJ4V1UD 751 CHAPTER 12 A/D CONVERTER Figure 12-3. Select Mode Operation Timing: 1-Buffer Mode (ANI1) ANI1 (input) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 A/D conversion Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 5 (ANI1) Data 6 (ANI1) ADCR1 register Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 5 (ANI1) INTAD interrupt Conversion ADCE start bit set (ADM0 register setting) ADCE bit set ADCE bit set Conversion ADCE start bit set (ADM0 register setting) Analog input ADCRn register ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 752 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER * 4-buffer mode In this mode, one analog input is A/D converted four times and the results are stored in the ADCRn register. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions end (n = 0 to 3 when the lower analog input channel is specified and n = 4 to 7 when the higher analog input channel is specified). After conversion has finished, the next conversion operation is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. Figure 12-4. Select Mode Operation Timing: 4-Buffer Mode (ANI2) ANI2 (input) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 A/D conversion Data 1 (ANI2) Data 2 (ANI2) Data 3 (ANI2) Data 4 (ANI2) Data 5 (ANI2) Data 6 (ANI2) ADCRn register Data 1 (ANI2) ADCR0 Data 2 (ANI2) ADCR1 Data 3 (ANI2) ADCR2 Data 4 (ANI2) ADCR3 Data 5 (ANI2) ADCR0 INTAD interrupt Conversion start (ADM0 register setting) Conversion start (ADM0 register setting) Analog input ADCRn register ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 User's Manual U16031EJ4V1UD 753 CHAPTER 12 A/D CONVERTER (b) Scan mode In this mode, the analog inputs specified by the ADM2 register are selected sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7). When the conversion of the specified analog input ends, the A/D conversion end interrupt (INTAD) is generated. After conversion has finished, the next conversion operation is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. Figure 12-5. Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3) ANI0 (input) Data 1 Data 5 ANI1 (input) Data 2 Data 6 ANI2 (input) Data 3 ANI3 (input) Data 4 A/D conversion Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI1) ADCRn register Data 1 (ANI0) ADCR0 Data 2 (ANI1) ADCR1 Data 3 (ANI2) ADCR2 Data 4 (ANI3) ADCR3 Data 5 (ANI0) ADCR0 INTAD interrupt Conversion start (ADM0 register setting) Conversion start (ADM0 register setting) Analog input ADCRn register ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 754 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER 12.5 Operation in A/D Trigger Mode When the ADCE bit of the ADM0 register is set to 1, A/D conversion is started. 12.5.1 Select mode operation In this mode, the analog input specified by the ADM2 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input. In the select mode, the 1-buffer mode and 4-buffer mode are supported according to the storing method of the A/D conversion results (n = 0 to 7). (1) 1-buffer mode (A/D trigger select: 1 buffer) In this mode, one analog input is A/D converted once. The conversion results are stored in one ADCRn register. The analog input and ADCRn register correspond one to one. Each time an A/D conversion is executed, an A/D conversion end interrupt (INTAD) is generated and A/D conversion ends. The next conversion operation is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. Analog Input ANIn A/D Conversion Result Register ADCRn This mode is most appropriate for applications in which the results of each first-time A/D conversion are read. Figure 12-6. Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer) ADM2 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) The ADCE bit of ADM0 is set to 1 (enable) ANI2 is A/D converted The conversion result is stored in ADCR2 The INTAD interrupt is generated User's Manual U16031EJ4V1UD 755 CHAPTER 12 A/D CONVERTER (2) 4-buffer mode (A/D trigger select: 4 buffers) In this mode, one analog input is A/D converted four times and the results are stored in the ADCRn register. When the 4th A/D conversion ends, an A/D conversion end interrupt (INTAD) is generated and the A/D conversion is stopped. The next conversion operation is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. Analog Input ANI0 to ANI3 A/D Conversion Result Register ADCR0 (1st time) ADCR1 (2nd time) ADCR2 (3rd time) ADCR3 (4th time) ANI4 to ANI7 ADCR4 (1st time) ADCR5 (2nd time) ADCR6 (3rd time) ADCR7 (4th time) This mode is suitable for applications in which the average of the A/D conversion results is calculated. Figure 12-7. Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers) ADM2 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 (x4) A/D converter ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) The ADCE bit of ADM0 is set to 1 (enable) ANI3 is A/D converted The conversion result is stored in ADCR0 ANI3 is A/D converted The conversion result is stored in ADCR1 (6) (7) (8) (9) ANI3 is A/D converted The conversion result is stored in ADCR2 ANI3 is A/D converted The conversion result is stored in ADCR3 (10) The INTAD interrupt is generated 756 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER 12.5.2 Scan mode operations In this mode, the analog inputs specified by the ADM2 register are selected sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7). When conversion of all the specified analog input ends, the A/D conversion end interrupt (INTAD) is generated, and A/D conversion is stopped. The next conversion operation is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. Analog Input ANI0 A/D Conversion Result Register ADCR0 . . . ANIn Note . . . ADCRn Note Set by the ANIS2 to ANIS0 bits of the ADM2 register. This mode is most appropriate for applications in which multiple analog inputs are constantly monitored. Figure 12-8. Example of Scan Mode Operation (A/D Trigger Scan) ADM2 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) (6) (7) The ADCE bit of ADM0 is set to 1 (enable) ANI0 is A/D converted The conversion result is stored in ADCR0 ANI1 is A/D converted The conversion result is stored in ADCR1 ANI2 is A/D converted The conversion result is stored in ADCR2 (8) (9) ANI3 is A/D converted The conversion result is stored in ADCR3 (10) ANI4 is A/D converted (11) The conversion result is stored in ADCR4 (12) ANI5 is A/D converted (13) The conversion result is stored in ADCR5 (14) The INTAD interrupt is generated User's Manual U16031EJ4V1UD 757 CHAPTER 12 A/D CONVERTER 12.6 Operation in Timer Trigger Mode In this mode, the conversion timing of the analog input signal set by the ANI0 to ANI7 pins is defined by the value set to the capture/compare registers of timers C4 and C5. The analog input conversion timing is generated when a compare match interrupt (INTCCC40, INTCCC41, INTCCC50, or INTCCC51) is generated by the capture/compare register connected to 16-bit timer C4 or C5 (TMC4 or TMC5). When the ADCE bit of the ADM0 register is set to 1, the A/D converter waits for the interrupt (INTCCC40, INTCCC41, INTCCC50, or INTCCC51), and starts conversion when INTCCC40, INTCCC41, INTCCC50, or INTCCC51 occurs (ADCS bit = 1 in the ADM0 register). When conversion is finished, the converter waits for an interrupt again (ADCS bit = 0). If INTCCC40, INTCCC41, INTCCC50, or INTCCC51 occurs during conversion, the conversion operation is executed from the beginning again. If data is written to the ADM0 to ADM2 registers during conversion, the conversion operation is stopped and executed from the beginning again. 758 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER 12.6.1 Select mode operation In this mode, an analog input (ANI0 to ANI7) specified by the ADM2 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input. In the select mode, the 1-buffer mode and 4-buffer mode are provided according to the storing method of the A/D conversion results. (1) 1-buffer mode (timer trigger select: 1 buffer) In this mode, one analog input is A/D converted once and the conversion results are stored in one ADCRn register. One analog input is A/D converted once using the trigger of the match interrupt signals (INTCCC40, INTCCC41, INTCCC50, INTCCC51) and the results are stored in one ADCRn register. An A/D conversion end interrupt (INTAD) is generated for each A/D conversion. Unless the ADCE bit of the ADM0 register is cleared to 0, A/D conversion is repeated each time a timer match interrupt is generated. Table 12-3. Correspondence Between Analog Input Pins and ADCRn Register (1-Buffer Mode (Timer Trigger Select: 1 Buffer)) Trigger INTCCCn interrupt INTCCCn interrupt INTCCCn interrupt INTCCCn interrupt INTCCCn interrupt INTCCCn interrupt INTCCCn interrupt INTCCCn interrupt Analog Input ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D Conversion Result Register ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 Remark n = 40, 41, 50, 51 Figure 12-9. Example of 1-Buffer Mode Operation (Timer Trigger Select: 1 Buffer) (ANI1) ANI0 INTCCC40 ADCR0 ADCR1 ADCR2 A/D converter ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) The ADCE bit of ADM0 is set to 1 (enable) The CCC40 compare is generated ANI1 is A/D converted The conversion result is stored in ADCR1 The INTAD interrupt is generated User's Manual U16031EJ4V1UD 759 CHAPTER 12 A/D CONVERTER (2) 4-buffer mode (timer trigger select: 4 buffers) In this mode, A/D conversion of one analog input is executed four times, and the results are stored in the ADCRn register. One analog input is A/D converted four times using the match interrupt signals (INTCCC40, INTCCC41, INTCCC50, INTCCC51) as a trigger, and the results are stored in four ADCRn registers. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions end. After conversion has finished, the next conversion is repeated, unless the ADCE bit of the ADM0 register is cleared to 0. This mode is suitable for applications in which the average of the A/D conversion results is calculated. Table 12-4. Correspondence Between Analog Input Pins and ADCRn Register (4-Buffer Mode (Timer Trigger Select: 4 Buffers)) Trigger INTCCCn interrupt Analog Input ANI0 to ANI3 A/D Conversion Result Register ADCR0 (1st time) ADCR1 (2nd time) ADCR2 (3rd time) ADCR3 (4th time) ANI4 to ANI7 ADCR4 (1st time) ADCR5 (2nd time) ADCR6 (3rd time) ADCR7 (4th time) Remark n = 40, 41, 50, 51 Figure 12-10. Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (ANI3) INTCC40 (x4) ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 (x4) ADCR0 ADCR1 ADCR2 A/D converter ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) (6) (7) The ADCE bit of ADM0 is set to 1 (enable) The CCC40 compare is generated ANI3 is A/D converted The conversion result is stored in ADCR0 The CCC40 compare is generated ANI3 is A/D converted The conversion result is stored in ADCR1 (8) (9) The CCC40 compare is generated ANI3 is A/D converted (10) The conversion result is stored in ADCR2 (11) The CCC40 compare is generated (12) ANI3 is A/D converted (13) The conversion result is stored in ADCR3 (14) The INTAD interrupt is generated 760 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER 12.6.2 Scan mode operation In this mode, the analog inputs specified by the ADM2 register are selected sequentially from the ANI0 pin and are A/D converted the specified number of times using the timer match interrupt signal as a trigger. The result of conversion is stored in the ADCRn register corresponding to the analog input. When all the specified analog input signals have been converted, an A/D conversion end interrupt (INTAD) occurs. After conversion has finished, the A/D converter waits for a trigger unless the ADCE bit of the ADM0 register is cleared to 0. When a timer match interrupt occurs again, the converter starts A/D conversion again, starting from the ANI0 input. This mode is most appropriate for applications in which multiple analog inputs are constantly monitored. Table 12-5. Correspondence Between Analog Input Pins and ADCRn Register (Scan Mode (Timer Trigger Scan)) Trigger INTCCCn interrupt Analog Input ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D Conversion Result Register ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 Remark n = 40, 41, 50, 51 Figure 12-11. Example of Scan Mode Operation (Timer Trigger Scan) (ANI0 to ANI4) ANI0 ANI1 INTCCC40 ADCR0 ADCR1 ADCR2 A/D converter ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) (6) (7) The ADCE bit of ADM0 is set to 1 (enable) The CCC40 compare is generated ANI0 is A/D converted The conversion result is stored in ADCR0 ANI1 is A/D converted The conversion result is stored in ADCR1 ANI2 is A/D converted (8) (9) The conversion result is stored in ADCR2 ANI3 is A/D converted (10) The conversion result is stored in ADCR3 (11) ANI4 is A/D converted (12) The conversion result is stored in ADCR4 (13) The INTAD interrupt is generated User's Manual U16031EJ4V1UD 761 CHAPTER 12 A/D CONVERTER 12.7 Operation in External Trigger Mode In this mode, the conversion timing of the analog signals input to the ANI0 to ANI7 pins is specified by the ADTRG pin. Detection of the valid edge at the ADTRG input pin is specified by using the EGA1 and EGA0 bits of the ADM1 register. When the ADCE bit of the ADM0 register is set to 1, the A/D converter waits for an external trigger (ADTRG), and starts conversion when the valid edge of ADTRG is detected (ADCS bit = 1 in the ADM0 register). When the converter has ended conversion, it waits for the external trigger again (ADCS bit = 0). If the valid edge is detected at the ADTRG pin during conversion, conversion is executed from the beginning again. If data is written to the ADM0 to ADM2 registers during conversion, conversion is stopped and executed from the beginning again. 12.7.1 Select mode operations In this mode, one analog input (ANI0 to ANI7) specified by the ADM2 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input. In the select mode, there are two select modes: 1-buffer mode and 4-buffer mode, according to the storing method of the conversion results. (1) 1-buffer mode (external trigger select: 1-buffer) In this mode, one analog input is A/D converted using the ADTRG signal as a trigger. The conversion results are stored in one ADCRn register. The analog input and the A/D conversion results register correspond one to one. The A/D conversion end interrupt (INTAD) is generated for each A/D conversion, and A/D conversion is stopped. Trigger ADTRG signal Analog Input ANIn A/D Conversion Result Register ADCRn While the ADCE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from the ADTRG pin. This mode is most appropriate for applications in which the results are read after each A/D conversion. 762 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER Figure 12-12. Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (ANI1) ANI0 ADTRG ADCR0 ADCR1 ADCR2 A/D converter ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) The ADCE bit of ADM0 is set to 1 (enable) The external trigger is generated ANI1 is A/D converted The conversion result is stored in ADCR1 The INTAD interrupt is generated User's Manual U16031EJ4V1UD 763 CHAPTER 12 A/D CONVERTER (2) 4-buffer mode (external trigger select: 4 buffers) In this mode, one analog input is A/D converted four times using the ADTRG signal as a trigger and the results are stored in the ADCRn register. The A/D conversion end interrupt (INTAD) is generated and A/D conversion is stopped after the 4th A/D conversion. Trigger ADTRG signal Analog Input ANI0 to ANI3 A/D Conversion Result Register ADCR0 (1st time) ADCR1 (2nd time) ADCR2 (3rd time) ADCR3 (4th time) ANI4 to ANI7 ADCR4 (1st time) ADCR5 (2nd time) ADCR6 (3rd time) ADCR7 (4th time) While the ADCE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from the ADTRG pin. This mode is suitable for applications in which the average of the A/D conversion results is calculated. Figure 12-13. Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (ANI2) ANI0 (x4) ADTRG ADCR0 ADCR1 (x4) ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) (6) (7) The ADCE bit of ADM0 is set to 1 (enable) The external trigger is generated ANI2 is A/D converted The conversion result is stored in ADCR0 The external trigger is generated ANI2 is A/D converted The conversion result is stored in ADCR1 (8) (9) The external trigger is generated ANI2 is A/D converted (10) The conversion result is stored in ADCR2 (11) The external trigger is generated (12) ANI2 is A/D converted (13) The conversion result is stored in ADCR3 (14) The INTAD interrupt is generated 764 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER 12.7.2 Scan mode operation In this mode, the analog inputs specified by the ADM2 register are selected sequentially from the ANI0 pin using the ADTRG signal as a trigger, and A/D converted. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7). When conversion of all the specified analog inputs has ended, the A/D conversion end interrupt (INTAD) is generated. Unless the ADCE bit of the ADM0 register is cleared to 0 after end of conversion, the A/D converter waits for a trigger. The converter starts A/D conversion from the ANI0 input when a trigger is input to the ADTRG pin again. Trigger ADTRG signal Analog Input ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D Conversion Result Register ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 When a trigger is input to the ADTRG pin while the ADCE bit of the ADM0 register is 1, A/D conversion is started again. This is most appropriate for applications in which multiple analog inputs are constantly monitored. Figure 12-14. Example of Scan Mode Operation (External Trigger Scan) (ANI0 to ANI3) ANI0 ANI1 ANI2 ADTRG ADCR0 ADCR1 ADCR2 A/D converter ANI3 ANI4 ANI5 ANI6 ANI7 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 (1) (2) (3) (4) (5) (6) The ADCE bit of ADM0 is set to 1 (enable) The external trigger is generated ANI0 is A/D converted The conversion result is stored in ADCR0 ANI1 is A/D converted The conversion result is stored in ADCR1 (7) (8) (9) ANI2 is A/D converted The conversion result is stored in ADCR2 ANI3 is A/D converted (10) The conversion result is stored in ADCR3 (11) The INTAD interrupt is generated User's Manual U16031EJ4V1UD 765 CHAPTER 12 A/D CONVERTER 12.8 Cautions Cautions concerning the A/D converter are shown below. (1) Stopping conversion operation When the ADCE bit of the ADM0 register is cleared to 0 during a conversion operation, the conversion operation stops and the conversion results are not stored in the ADCRn register (n = 0 to 7). (2) External/timer trigger interval Set the interval (input time interval) of the trigger in the external or timer trigger mode longer than the conversion time specified by the FR3 to FR0 bits of the ADM1 register. When 0 < interval conversion operation time When the following external trigger or timer trigger is input during a conversion operation, the conversion operation is aborted and the conversion starts according to the last external trigger input or timer trigger input. When conversion operations are aborted, the conversion results are not stored in the ADCRn register (n = 0 to 7). However, the number of times the trigger has been input is counted. When an interrupt occurs, the values that have been converted are stored in the ADCRn register. (3) Operation in standby mode <1> HALT mode In this mode, A/D conversion continues. When this mode is released by NMI input or unmasked maskable interrupt input (see 8.6.3 (2) Release of HALT mode), the ADM0, ADM1, and ADM2 registers and ADCRn register hold the value (n = 0 to 7). <2> IDLE mode, software STOP mode As clock supply to the A/D converter is stopped, no conversion operations are performed. When these modes are released by NMI input, the ADM0, ADM1, and ADM2 registers and the ADCRn register hold the value (n = 0 to 7). However, when the IDLE or software STOP mode is set during a conversion operation, the conversion operation is stopped. At this time, if the mode released by NMI input or unmasked maskable interrupt input (see 8.6.4 (2) Release of IDLE mode, 8.6.5 (2) Release of software STOP mode), the conversion operation resumes, but the conversion result written to the ADCRn register will become undefined. (4) Compare match interrupt in timer trigger mode The compare register's match interrupt becomes an A/D conversion start trigger and starts the conversion operation. When this happens, the compare register's match interrupt also functions as a compare register match interrupt for the CPU. In order to prevent match interrupts from the compare register for the CPU, disable interrupts using the interrupt mask bits (CCC4MK0, CCC4MK1, CCC5MK0, CCC5MK1) of the interrupt control register (CCC4IC0, CCC4IC1, CCC5IC0, CCC5IC1). (5) Input range of ANI0 to ANI7 Use the input voltage at ANI0 to ANI7 within the specified range. If a voltage outside the range of AVREFP and AVREFM is input to any of these pins (even within the absolute maximum rating range), the converted value of the channel is undefined. In addition, the converted value of the other channels may also be affected. 766 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER (6) Conflict <1> Conflict between writing A/D conversion result registers (ADCRn, ADCRnH) at end of conversion and reading ADCRn and ADCRnH registers by instruction Reading the ADCRn and ADCRnH registers takes precedence. After these registers have been read, the new conversion result is written to the ADCRn and ADCRnH registers. <2> Conflict between writing ADCRn and ADCRnH at end of conversion and input of external trigger signal The external trigger signal is not accepted during A/D conversion. Therefore, it is not accepted while ADCRn and ADCRnH are being written. <3> Conflict between writing ADCRn and ADCRnH at end of conversion and writing A/D converter mode register 1 (ADM1) or A/D converter mode register 2 (ADM2) If ADM1 or ADM2 is written immediately after ADCRn and ADCRnH have been written on completion of A/D conversion, the conversion result is written to the ADCRn and ADCRnH registers, but the A/D conversion end interrupt (INTAD) may not occur depending on the timing. User's Manual U16031EJ4V1UD 767 CHAPTER 12 A/D CONVERTER 12.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). %FSR indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1%FSR = (Max. value of analog input voltage that can be converted - Min. value of analog input voltage that can be converted)/100 = (AVREFP - AVREFM)/100 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, linearity error and errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. Figure 12-15. Overall Error 1......1 Ideal line Digital output Overall error 0......0 AVREFM Analog input AVREFP 768 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 12-16. Quantization Error 1......1 Digital output 1/2LSB Quantization error 1/2LSB 0......0 AVREFM Analog input AVREFP (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0......000 to 0......001. Figure 12-17. Zero-Scale Error 111 Digital output (Lower 3 bits) Ideal line 100 Zero-scale error 011 010 001 000 -1 0 1 2 3 1023 Analog input (LSB) User's Manual U16031EJ4V1UD 769 CHAPTER 12 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1......110 to 1......111. Figure 12-18. Full-Scale Error Full-scale error Digital output (Lower 3 bits) 111 100 011 010 000 -0 1021 1022 1023 1024 Analog input (LSB) (6) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 12-19. Differential Linearity Error 1......1 Ideal 1LSB width Digital output Differential linearity error 0......0 AVREFM AVREFP Analog input 770 User's Manual U16031EJ4V1UD CHAPTER 12 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 12-20. Integral Linearity Error 1......1 Ideal line Digital output 0......0 AVREFM Integral linearity error AVREFP Analog input (8) Conversion time This expresses the time from when a trigger was generated to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Figure 12-21. Sampling Time Sampling time Conversion time User's Manual U16031EJ4V1UD 771 CHAPTER 13 PWM UNIT 13.1 Features * PWMn: 2 channels * 12- to 16-bit accuracy selectable * Minimization of low-pass filter size due to main pulse + ancillary pulse configuration Main pulse 4/5/6/7/8 bits Ancillary pulse 8 bits * Repeat frequency: 129 kHz to 2 MHz (fPWMC = 33 MHz) * Selecting pulse width rewrite period: Every 1 pulse/256 pulses * Active level of PWM output pulse selectable * PWM operating clock (fPWMC): fX/4, fX/8, fX/16, or fX/32 selectable Remarks 1. n = 0, 1 2. fPWMC: PWM operating clock fX: Main clock 13.2 Configuration PWMn has a PWM output configuration of 256 main pulses and sets the active-level width using modulo H register n. (1) Prescaler The prescaler divides fX to generate the PWM operating clock (fPWMC). The output frequency of the prescaler can be selected from fX/4, fX/8, fX/16, and fX/32, by using the CKSPn1 and CKSPn0 bits of the PWMCn register (n = 0, 1). (2) Reload controller The reload controller controls reloading of the modulo register value. The reload timing (PWM pulse width rewrite period) can be selected from 2x/fPWMC or 2x+8/fPWMC by using the SYNn bit of the PWMCn register (n = 0, 1, x = 4 to 8 (main pulse bit length)). (3) Main pulse generator/output controller This circuit controls the output timing of the main pulse. It generates the main pulse from the reload signal generated by the reload controller, according to the value of modulo H register n (n = 0, 1). (4) Ancillary pulse generator/output controller This circuit controls the output timing of the ancillary pulse. It generates an ancillary pulse from the reload signal generated by the reload controller, according to the value of modulo L register n (n = 0, 1). 772 User's Manual U16031EJ4V1UD CHAPTER 13 PWM UNIT (5) Pulse synthesizer/output controller This circuit controls the timing of the PWM pulse signal output by synthesizing the main pulse and ancillary pulse. Figure 13-1. Block Diagram of PWM Unit fPWMC Main pulse Main pulse generator/output controller 2x/fPWMC Ancillary Ancillary pulse generator/ pulse output controller 2x+8/fPWMC fX/4 Prescaler Pulse synthesizer/ output controller PWMn Selector x Reload control 8 PWMEn PMPn2 PMPn1 PMPn0 ALVn SYNn CKSPn1 CKSPn0 15 87 0 Modulo H register n Modulo L register n PWM control register n (PWMCn) 8 16 Internal bus Remarks 1. n = 0, 1 x = 4 to 8 (specified by PMPn2 to PMPn0 bits) 2. fPWMC: PWM operating clock fX: Main clock User's Manual U16031EJ4V1UD 773 CHAPTER 13 PWM UNIT 13.3 Control Registers (1) PWM control registers 0 and 1 (PWMC0 and PWMC1) PWMCn is a register that controls PWMn (n = 0, 1). These registers can be read or written in 8-bit or 1-bit units. Cautions 1. Do not change the setting of the PMPn2 to PMPn0, SYNn, CKSPn1, and CKSPn0 bits during PWM operation (when PWMEn bit = 1); otherwise the operation cannot be guaranteed. 2. Note that, if the setting of the ALVn bit is changed during PWM operation (when PWMEn bit = 1), noise may be generated. 774 User's Manual U16031EJ4V1UD CHAPTER 13 PWM UNIT 7 PWMC0 PWME0 6 PMP02 5 PMP01 4 PMP00 3 ALV0 2 SYN0 1 0 Address FFFFFB00H After reset 08H CKSP01 CKSP00 PWMC1 PWME1 PMP12 PMP11 PMP10 ALV1 SYN1 CKSP11 CKSP10 FFFFFB10H 08H Bit position 7 Bit name PWMEn Function This bit enables or disables the operation of PWMn. 0: Disables PWM operation. Outputs the inactive level as PWM output (PWMn). 1: Enables PWM operation. 6 to 4 PMPn2 to PMPn0 These bits specify the number of main pulse length specification bits and the main pulse length. PMPn2 PMPn1 PMPn0 Number of main pulse length specification bits 0 0 0 0 1 0 0 1 1 0 Other than above 0 1 0 1 0 8 bits 7 bits 6 bits 5 bits 4 bits Setting prohibited 2 (256 bits) 2 (128 bits) 2 (64 bits) 2 (32 bits) 2 (16 bits) 4 5 6 7 8 Main pulse bit length 3 ALVn This bit specifies the active level of PWMn. 0: Active low 1: Active high At reset, the inactive level of the ALVn bit (low level) is output as PWM output. 2 SYNn This bit specifies the period during which the pulse width of PWMn is to be rewritten. 0: Long period (every 256 PWM cycles (2 /fPWMC)) x 1: Short period (every 1 PWM cycle (2 /fPWMC)) x+8 1, 0 CKSPn1, CKSPn0 These bits specify the operating clock of PWMn (fPWMC). CKSPn1 0 0 1 1 CKSPn0 0 1 0 1 fX/4 fX/8 fX/16 fX/32 Operating clock (fPWMC) Remarks 1. n = 0, 1 x = 4 to 8 (specified by PMPn2 to PMPn0 bits) 2. fX: Main clock User's Manual U16031EJ4V1UD 775 CHAPTER 13 PWM UNIT (2) PWM modulo registers 0 and 1 (PWM0 and PWM1) These 16-bit registers determine the pulse width of the PWM pulse. These registers can be read or written in 16-bit units. If the higher 8 bits of the PWMn register are used as a PWMHn register and the lower 8 bits are used as a PWMLn register, these registers can be read or written in 8-bit units. <1> Modulo H register n (PWMHn): Bits 15 to 8 This register specifies the active level of the main pulse. The data of the active level width of only the bit length specified by the PMPn2 to PMPn0 bits of the PWMCn register is valid. If the counter length is set to 4 to 7 bits by the PMPn2 to PMPn0 bits, data input to the higher bits is invalid. <2> Modulo L register n (PWMLn): Bits 7 to 0 This register adjusts the timing of the ancillary pulse for fine tuning (see Figure 13-2). A value of 0000H to FFFFH can be set to the PWMn register, and the PWM output changed linearly. If a value of 0000H is set, the inactive level is held. If the value is FFFFH, the PWM output becomes inactive for one ancillary pulse (1/fPWMC) in one rewrite cycle (216/fPWMC) (see Figure 13-3). 15 PWMn 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PWM0: FFFFFB02H PWM1: FFFFFB12H After reset 0000H Modulo H register n (for generating main pulse) Modulo L register n (for generating ancillary pulse) 776 User's Manual U16031EJ4V1UD CHAPTER 13 PWM UNIT 13.4 Operation 13.4.1 PWM basic operation PWMn is divided into 256 parts, each of which is called a main pulse. Each main pulse has 4- to 8-bit accuracy. PWMn realizes a signal with an accuracy of 12 to 16 bits by synthesizing the required number of main pulses and an ancillary pulse with a pulse width of one clock. The main pulse is set by the PMPn2 to PMPn0 bits of PWM control register n (PWMCn), and the pulse width is determined by the value of modulo H register n (valid number of bits). The repeat cycle of the PWM pulse output is the operating clock cycle (fPWMC) of PWMn specified by the CKSPn1 and CKSPn0 bits of the PWMCn register divided by 2x (fPWMC/2x). Of the 256 main pulses, the ancillary pulses are generated only for the main pulses of the set number specified by modulo L register n. The pulse width is 1/fPWMC. The logical sum of the main pulse and the ancillary pulse is output as the PWM pulse signal. Therefore, the average value of 256 PWM pulse signals is the PWM pulse signal with a resolution of 12 to 16 bits. The duty factor of the output PWM pulse is determined as follows, by the value set to modulo H register n of PWM modulo register n (PWM0 or PWM1). (1) If ancillary pulse is not generated Duty of output PWM pulse = (Value of modulo H register n) 2x (2) If ancillary pulse is generated Duty of output PWM pulse = (Value of modulo H register n) + 1 2x Remark x = 4 to 8 (bit length of main pulse) User's Manual U16031EJ4V1UD 777 CHAPTER 13 PWM UNIT Figure 13-2. Example of PWM Output with Main Pulse and Ancillary Pulse 16-bit accuracy when 256 output pulses are averaged 0 PWMn = xx40H Main pulse Ancillary pulse (modulo L = 40H) PWM output PWMn = xxC0H 1 2 3 4 5 6 7 8 9 10 11 12 13 254 255 Main pulse Ancillary pulse (modulo L = C0H) PWM output 1/fPWMC x TX 1/fPWMC 1/fPWMC x 2X Remarks 1. n = 0, 1 2. fPWMC: PWM operating clock Tx: x: Value of modulo H register n Number of valid bits of modulo H register n (specified by PMPn2 to PMPn0 bits of PWMCn register) Active level: High 778 User's Manual U16031EJ4V1UD CHAPTER 13 PWM UNIT Figure 13-3. Example of PWM Output Operation 16-bit accuracy when 256 output pulses are averaged 0 PWMn = 0000H Main pulse Ancillary pulse (modulo L = 00H) PWM output PWMn = 0001H 1 2 3 4 5 6 7 8 ... 126 127 128 ... 254 255 L L L Main pulse Ancillary pulse (modulo L = 01H) PWM output L PWMn = FF00H Main pulse Ancillary pulse (modulo L = 00H) PWM output PWMn = FFFFH Main pulse Ancillary pulse (modulo L = FFH) PWM output L Remarks 1. n = 0, 1 2. Condition: Number of valid bits of modulo H register n = 8 16-bit accuracy Active level: High User's Manual U16031EJ4V1UD 779 CHAPTER 13 PWM UNIT 13.4.2 Starting/stopping PWM operation To output a PWM pulse, set data to PWM modulo register n (PWMn) and then set the PWMEn bit of PWM control register n (PWMCn) to 1 (n = 0, 1). As a result, the PWM output pin outputs a PWM pulse of the active level specified by the ALVn bit of the PWMCn register. When the PWMEn bit of the PWMCn register is cleared to 0, the PWM output unit immediately stops the PWM output operation, and the PWM output pin becomes inactive. (1) Setting for starting PWM operation Before starting the operation of PWMn (when PWMEn bit of PWMCn register = 0), be sure to initialize the following registers. * PMCDH, PFCDH registers: * PWMn register: * PWMCn register: CKSPn1 and CKSPn0 bits: Specify the operating clock (fPWMC) (fX/4, fX/8, fX/16, fX/32) PMPn2 to PMPn0 bits: ALVn bit: SYNn bit: Specify the bit length (x) of the main pulse. Specify the active level of the PWM pulse. Specify the PWM pulse width rewrite period. Set the control mode. Set the pulse width. Cautions 1. Do not change the setting of the PMPn2 to PMPn0, SYNn, CKSPn1, and CKSPn0 bits when PWMEn bit of the PWMCn register = 1; otherwise the operation cannot be guaranteed. 2. Note that, if the setting of the ALVn bit is changed during PWM operation (when PWMEn bit = 1), noise may be generated. Remark n = 0, 1 When the PWMEn bit of the PWMCn register is set, PWMn starts operating. Immediately after PWMn has started operating, however, the PWM pin maintains the status of the port mode (inactive level) until the reload signal of the PWMn register is generated. After the operation has been started, the PWM output becomes active when the reload signal is generated, regardless of the setting of the SYNn bit (PWMn = other than 00xxH). If the timing of rewriting the pulse width is set to 2x+8 (long period: SYNn bit = 0), the operation is started up to 2x+8/fPWMC after the PWMEn bit has been set. The PWMn register can be rewritten even during PWM output. 780 User's Manual U16031EJ4V1UD CHAPTER 13 PWM UNIT (2) Setting for stopping PWM operation When the PWMEn bit of the PWMCn register (n = 0, 1) is cleared to 0, the PWM operation is immediately stopped, and the PWM output becomes inactive immediately. Figure 13-4. PWM Operation Timing PWMEn bit 2X/fPWMC Reload signal 2X/fPWMC 2X/fPWMC PWM output Operation setting PWMn operation starts (PWMEn = 1) PWMn operation stops (PWMEn = 0) Remarks 1. n = 0, 1 x = 4 to 8 (specified by PMPn2 to PMPn0 bits of PWMCn register) 2. fPWMC: PWM operating clock User's Manual U16031EJ4V1UD 781 CHAPTER 13 PWM UNIT 13.4.3 Setting active level of PWM pulse The ALVn bit of PWM control register n (PWMCn) specifies the active level of the PWM pulse output from the PWM output pin (n = 0, 1). If the ALVn bit is set to 1, an active-high pulse is output; if it is cleared to 0, an active-low pulse is output. If the ALVn bit is rewritten, the active level of PWM output is immediately changed. The figure below shows the setting of the active level of PWM output and pin status. Regardless of the setting of the PWMEn bit (which enables or disables PWM), the active level of PWM output can be changed by manipulating the ALVn bit. Figure 13-5. Setting Active Level of PWM Output ALVn (Active-high) (Active-low) PWMn (Rewriting ALVn bit) Remark n = 0, 1 782 User's Manual U16031EJ4V1UD CHAPTER 13 PWM UNIT 13.4.4 Specifying PWM pulse width rewrite period PWM output is started and the pulse width is changed every 256 cycles of the PWM pulse (2x+8/fPWMC) or every one PWM cycle (2x/fPWMC). This PWM pulse width rewrite period is specified by the SYNn bit of the PWMCn register (n = 0, 1). When the SYNn bit is cleared to 0, the pulse width is changed every 256 PWM pulse cycles (2x+8/fPWMC) (long period). Therefore, it takes up to 2x+8 clocks to output a pulse of the width corresponding to the data written to the PWMn register. An example of the PWM output timing at this time is shown in Figure 13-6. When the SYNn bit is set to 1, the pulse width is changed every one PWM pulse cycle (2x/fPWMC) (short period). In this case, it takes up to 2x clocks to output a pulse of the width corresponding to the data written to the PWMn register. If the PWM pulse rewrite period is specified to be every 2x/fPWMC (if the SYNn bit is set to 1), the accuracy of the PWM pulse is x bits or more and (x+8) bits or less, or is lower than the accuracy when the rewrite cycle is set to 2x+8/fPWMC. However, the response speed improves because the repeat cycle increases. Figure 13-7 shows an example of the PWM output timing where the rewrite timing is 2x/fPWMC. Figure 13-6. PWM Output Timing Example 1 (PWM Pulse Width Rewrite Period: 2x+8/fPWMC) PWM pulse 2x+8 cycles PWM pulse 2x+8 cycles PWMn output pin Contents of PWMn register m Rewriting PWMn register l PWM output enabled (PWMEn = 1) PWM pulse width rewriting timing PWM pulse width rewriting timing PWM pulse width rewriting timing Cautions 1. The pulse width is rewritten every 256 cycles of the PWM pulse 2. The accuracy of the PWM pulse is (x+8) bits. Remark n = 0, 1 User's Manual U16031EJ4V1UD 783 CHAPTER 13 PWM UNIT Figure 13-7. PWM Output Timing Example 2 (PWM Pulse Width Rewrite Period: 2x/fPWMC) 1 PWM pulse cycle PWMn output pin Contents of PWMn register m k l m PWM output enabled (PWMEn = 1) Rewriting PWMn register Rewriting PWMn register Rewriting PWMn register PWM pulse width changing timing Cautions 1. The pulse width is rewritten every one PWM pulse cycle. 2. The accuracy of the PWM pulse is x bits or more and (x+8) bits or less. Remarks 1. k, l, and m indicate the contents of the PWMn register. 2. n = 0, 1 13.4.5 Repeat cycle The following table shows the repeat cycle of PWMn (n = 0, 1). Table 13-1. Repeat Cycle of PWMn Main Pulse Accuracy 4 bits 5 bits 6 bits 7 bits 8 bits Ancillary Pulse Accuracy 8 bits 8 bits 8 bits 8 bits 8 bits 16/fPWMC 32/fPWMC 64/fPWMC 128/fPWMC 256/fPWMC Repeat Cycle Pulse Width Rewrite Period Long Period (SYNn Bit = 0) 2 /fPWMC 2 /fPWMC 2 /fPWMC 2 /fPWMC 2 /fPWMC 16 15 14 13 12 Short Period (SYNn Bit = 1) 2 /fPWMC 2 /fPWMC 2 /fPWMC 2 /fPWMC 2 /fPWMC 8 7 6 5 4 Remarks 1. n = 0, 1 2. fPWMC: PWM operating clock 784 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.1 Features * Input-only ports: 1 I/O ports: 77 * Function alternately as other peripheral I/O pins. * It is possible to specify input and output in 1-bit units. 14.2 Port Configuration The V850E/ME2 incorporates a total of 78 input/output ports (including 1 input-only port) labeled ports 1, 2, 5 to 7, AL, AH, DH, CS, CT, CM, and CD. The port configuration is shown below. P10 Port 1 P13 PAH0 Port AH PAH9 P20 P21 Port 2 P25 PDH0 Port DH PDH15 P50 Port 5 P55 PCS0 Port CS PCS7 P65 Port 6 P67 PCT0 PCT5 PCT7 Port CT P72 Port 7 P77 PCM0 Port CM PCM5 Port AL PAL0 PAL1 PCD0 Port CD PCD3 User's Manual U16031EJ4V1UD 785 CHAPTER 14 PORT FUNCTIONS (1) Function of each port The port functions of this product are shown below. 8-bit and 1-bit operations are possible on all ports, allowing various kinds of control to be performed. In addition to their port functions, these pins also function as on-chip peripheral I/O input/output pins in the control mode. For the block types of each port, see (3) Block diagram of port. Port Name Port 1 Pin Name P10 to P13 Port Function 4-bit I/O Function in Control Mode Serial interface I/O (CSI30, UARTB0) External interrupt input USB clock signal input Port 2 P20 to P25 1-bit input, 5-bit I/O NMI input Serial interface I/O (CSI31, UARTB1) External interrupt input DMA controller I/O External interrupt input Timer/counter I/O Port 6 P65 to P67 3-bit I/O Timer/counter I/O External interrupt input DMA controller I/O Timer/counter I/O External interrupt input Port AL PAL0, PAL1 2-bit I/O External address bus (A0, A1) External interrupt input External address bus (A16 to A25) External data bus (D16 to D31) External interrupt input PWM output Timer/counter I/O Port CS Port CT PCS0 to PCS7 PCT0 to PCT5, PCT7 PCM0 to PCM5 8-bit I/O 7-bit I/O External bus interface control signal output External bus interface control signal output D-2, J-2 D-2, J-3 G-3 Block Type F-1, F-3, H-1, J-1 A-1, F-4, G-2, H-1 Port 5 P50 to P55 6-bit I/O F-2, F-3, G-1, G-2, J-1 L-3, L-5 Port 7 P72 to P77 6-bit I/O L-1, L-2, L-4 Port AH Port DH PAH0 to PAH9 PDH0 to PDH15 10-bit input 16-bit I/O D-2 M-1, M-2, M-3 Port CM 6-bit I/O Wait insertion signal input External bus interface control signal I/O Self-refresh request signal input A/D converter external trigger input C-1, D-1, D-2, F-5 Port CD PCD0 to PCD3 4-bit I/O External bus interface control signal output Bus clock output D-1, D-2 786 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Cautions 1. When switching the mode of a port that functions as an output or I/O pin to control mode, be sure to follow the procedure below. <1> Set the inactive level of the signals output in control mode to the appropriate bits in port n (n = 1, 2, 5 to 7, AL, AH, DH, CS, CT, CM, and CD). <2> The mode is switched to control mode by the port n mode control register (PMCn). If <1> above is not performed, the contents of port n may be output for a moment when the mode is switched from port mode to control mode. 2. To manipulate a port by using a bit manipulation instruction (SET1, CLR1, or NOT1), read the port in byte units, process the data of only the bit to be manipulated, and then write back the byte data to the port after conversion. In the case of a port having a mixture of input and output pins, the contents of the output latch are written over bits other than the bit to be manipulated. Consequently, the output latch of the input pin is undefined (in the input mode, however, the pin status does not change because the output buffer is turned off). To change the port mode from the input to the output mode, therefore, set an expected output value to the corresponding bits, and then change the mode to the output mode. The same applies to a port that has both a control mode and an output mode. User's Manual U16031EJ4V1UD 787 CHAPTER 14 PORT FUNCTIONS (2) Function when each port's pins are reset and registers that set the port/control mode (1/3) Port Name Port 1 P10/INTP10/UCLK P11/INTP11/SCK0 P12/SI0/RXD0 P13/SO0/TXD0 Port 2 P20/NMI P21/INTP21/RXD1 P22/INTP22/TXD1 P23/INTP23/SCK1 P24/INTP24/SI1 P25/INTP25/SO1 Port 5 P50/INTP50/DMARQ0 P51/INTP51/DMAAK0 P52/INTP52/TC0 P53/INTPC00/TIC0/DMARQ1 P54/INTPC01/DMAAK1 P55/TOC0/TC1 Port 6 P65/INTP65/INTPC10/TIC1 P66/INTP66/INTPC11 P67/INTP67/TOC1 Port 7 P72/INTPC20/TIC2/DMARQ2 P73/INTPC21/DMAAK2 P74/TOC2/TC2 P75/INTPC30/TIC3/DMARQ3 P76/INTPC31/DMAAK3 P77/TOC3/TC3 Port AL Port AH PAL0/INTPL0/A0 PAL1/INTPL1/A1 PAH0/A16 to PAH9/A25 P10 (input mode) P11 (input mode) P12 (input mode) P13 (input mode) NMI P21 (input mode) P22 (input mode) P23 (input mode) P24 (input mode) P25 (input mode) P50 (input mode) P51 (input mode) P52 (input mode) P53 (input mode) P54 (input mode) P55 (input mode) P65 (input mode) P66 (input mode) P67 (input mode) P72 (input mode) P73 (input mode) P74 (input mode) P75 (input mode) P76 (input mode) P77 (input mode) A0 A1 A16 to A25 PMCAH PMCAL, PFCALL PMC7, PFC7 PMC6, PFC6 PMC5, PFC5 - PMC2, PFC2 Pin Name Pin Function After Reset Register That Sets the Mode PMC1, PFC1 788 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2/3) Port Name Port CS PCS0/CS0 PCS1/CS1 PCS2/CS2/IOWR PCS3/CS3 PCS4/CS4 PCS5/CS5/IORD PCS6/CS6 PCS7/CS7 Port CT PCT0/LLWR/LLBE/LLDQM PCT1/LUWR/LUBE/LUDQM PCT2/ULWR/ULBE/ULDQM PCT3/UUWR/UUBE/UUDQM PCT4/RD PCT5/WE/WR PCT7/BCYST Port CM PCM0/WAIT PCM1 PCM2/HLDAK PCM3/HLDRQ PCM4/REFRQ PCM5/SELFREF/ADTRG Port CD PCD0/SDCKE PCD1/BUSCLK PCD2/SDCAS PCD3/SDRAS HLDAK HLDRQ REFRQ SELFREF SDCKE BUSCLK SDCAS SDRAS PMCCM, PFCCM PMCCD CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 LLWR/LLDQM LUWR/LUDQM ULWR/ULDQM UUWR/UUDQM RD WE/WR BCYST WAIT - PMCCM PMCCM - PMCCT PMCCT, PFCCT PMCCS, PFCCS PMCCS PMCCS, PFCCS PMCCS Pin Name Pin Function After Reset Register That Sets the Mode PMCCS User's Manual U16031EJ4V1UD 789 CHAPTER 14 PORT FUNCTIONS (3/3) Port Name Port DH PDH0/D16/INTPD0 PDH1/D17/INTPD1 PDH2/D18/INTPD2/TOC4 PDH3/D19/INTPD3 PDH4/D20/INTPD4 PDH5/D21/INTPD5/TOC5 PDH6/D22/INTPD6/INTP100/TCUD10 PDH7/D23/INTPD7/INTP101/TCLR10 PDH8/D24/INTPD8/TO10 PDH9/D25/INTPD9/TIUD10 PDH10/D26/INTPD10/INTP110/TCUD11 PDH11/D27/INTPD11/INTP111/TCLR11 PDH12/D28/INTPD12/TO11 PDH13/D29/INTPD13/TIUD11 PDH14/D30/INTPD14/PWM0 PDH15/D31/INTPD15/PWM1 Pin Name Pin Function After Reset 16-Bit Mode Note Register That Note 32-Bit Mode D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Sets the Mode PMCDH PDH0 (input mode) PDH1 (input mode) PDH2 (input mode) PDH3 (input mode) PDH4 (input mode) PDH5 (input mode) PDH6 (input mode) PDH7 (input mode) PDH8 (input mode) PDH9 (input mode) PDH10 (input mode) PDH11 (input mode) PDH12 (input mode) PDH13 (input mode) PDH14 (input mode) PDH15 (input mode) PMCDH, PFCDH PMCDH PMCDH, PFCDH Note For details of the operating modes, refer to 3.3.2 Operating mode specification. 790 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (3) Block diagram of port Figure 14-1. Block Diagram of Type A-1 WRINTR NMIR0 WRINTF Internal bus NMIF0 Selector 0 1 A P20 Address RD NMI Noise elimination Edge detection Remark A: Masked in cycles other than read cycles User's Manual U16031EJ4V1UD 791 CHAPTER 14 PORT FUNCTIONS Figure 14-2. Block Diagram of Type C-1 WRPMC PMCCMn WRPM PMCMn A Internal bus WRPORT PCMn PCMn Selector Address C RD Input signal in control mode Selector B Remarks 1. n = 0, 3 2. A: Active in output port mode B: Active in read cycle of port mode or in control mode C: Masked in port mode 792 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-3. Block Diagram of Type D-1 WRPMC PMCmn WRPM PMmn A Internal bus WRPORT Selector Output signal in control mode Pmn Pmn Selector Selector B Address RD Remarks 1. mn = CM1, CD1 2. A: Active in output port mode or control mode B: Masked in cycles other than read cycles User's Manual U16031EJ4V1UD 793 CHAPTER 14 PORT FUNCTIONS Figure 14-4. Block Diagram of Type D-2 WRPMC Output buffer off signalNote PMCmn WRPM PMmn A Internal bus Selector WRPORT Output signal in control mode Pmn Pmn Selector Selector B Address RD Note PAH0 to PAH9: These signals become active in the IDLE mode and software STOP mode, and by bus hold and reset. PCS0, PCS1, PCS3, PCS4, PCS6, PCS7, PCD2, PCD3, PCT4, PCT5, PCT7: These signals become active by bus hold and reset. PCM2, PCM4, PCD0: These signals become active at reset. Remarks 1. mn = AH0 to AH9, CS0, CS1, CS3, CS4, CS6, CS7, CT4, CT5, CT7, CM2, CM4, CD0, CD2, CD3 2. A: Active in output port mode or control mode B: Masked in cycles other than read cycles 794 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-5. Block Diagram of Type F-1 WRPFC PFC12 WRPMC PMC12 WRPM A Internal bus PM12 WRPORT P12 P12 P Selector Address RD Input signal in control mode Selector C Selector B Remark A: Active in output port mode B: Active in read cycle of port mode or in control mode C: Masked in port mode User's Manual U16031EJ4V1UD 795 CHAPTER 14 PORT FUNCTIONS Figure 14-6. Block Diagram of Type F-2 WRPFC PFC53 WRPMC PMC53 WRPM A PM53 Internal bus WRPORT P53 P53 P Selector Address RD Input signal in control mode Selector C Selector B Remark A: Active in output port mode B: Active in read cycle of port mode or in control mode C: Masked in port mode 796 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-7. Block Diagram of Type F-3 WRINTR INTRmn WRINTF INTFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn A WRPORT Pmn Pmn Selector Address Selector RD C Input signal in control mode Selector B Noise elimination Edge detection Remarks 1. mn = 10, 50 2. A: Active in output port mode B: Active in read cycle of port mode or in control mode C: Masked in port mode User's Manual U16031EJ4V1UD 797 CHAPTER 14 PORT FUNCTIONS Figure 14-8. Block Diagram of Type F-4 WRINTR INTR2n WRINTF INTF2n WRPFC PFC2n WRPMC PMC2n Internal bus WRPM PM2n A WRPORT P2n P2n Selector Address Selector RD C Input signal in control mode Selector B Noise elimination Edge detection Remarks 1. n = 1, 4 2. A: Active in output port mode B: Active in read cycle of port mode or in control mode C: Masked in port mode 798 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-9. Block Diagram of Type F-5 WRPFC PFCCM5 WRPMC PMCCM5 WRPM Internal bus PMCM5 A WRPORT PCM5 PCM5 Selector Address RD Selector B C Input signal in control mode Selector Remark A: Active in output port mode B: Active in read cycle of port mode or in control mode C: Masked in port mode User's Manual U16031EJ4V1UD 799 CHAPTER 14 PORT FUNCTIONS Figure 14-10. Block Diagram of Type G-1 WRPFC PFC54 A WRPMC PMC54 WRPM Internal bus PM54 B Selector WRPORT Output signal in control mode P54 P54 Selector Address Selector D RD Input signal in control mode C Remark A: Active in output control mode B: Active in output port mode C: Active in read cycle of port mode or in input control mode D: Masked in port mode or output control mode 800 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-11. Block Diagram of Type G-2 WRINTR INTRmn WRINTF INTFmn WRPFC PFCmn WRPMC A PMCmn Internal bus WRPM B PMmn Selector WRPORT Output signal in control mode Pmn Pmn Selector Address Selector RD Input signal in control mode Noise elimination Edge detection D C Remarks 1. mn = 22, 25, 51, 52 2. A: Active in output control mode B: Active in output port mode C: Active in read cycle of port mode or in input control mode D: Masked in port mode or output control mode User's Manual U16031EJ4V1UD 801 CHAPTER 14 PORT FUNCTIONS Figure 14-12. Block Diagram of Type G-3 WRINTR INTRmn WRINTF INTFmn WRPFC Output buffer off signalNote PFCmn WRPMC A Internal bus PMCmn WRPM B PMmn Selector WRPORT Output signal in control mode PALn Pmn Selector Address Selector RD Input signal in control mode Noise elimination Edge detection D C Note Signal that becomes active in IDLE mode and software STOP mode, and by bus hold and reset Remarks 1. n = 0, 1 2. A: Active in output control mode B: Active in output port mode C: Active in read cycle of port mode or in input control mode D: Masked in port mode or output control mode 802 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-13. Block Diagram of Type H-1 WRINTR INTRmn WRINTF INTFmn WRPFC PFCmn WRPMC Output enable signal in control mode PMCmn Internal bus B WRPM A PMmn Selector WRPORT Output signal in control mode Pmn Pmn Selector Address Selector RD D Input signal in control mode Selector C Noise elimination Edge detection Remarks 1. mn = 11, 23 2. A: Active in output port mode B: Bidirectional control mode (DIR control): Active in output direction C: Active in read cycle of port mode or in input control mode D: Masked in port mode User's Manual U16031EJ4V1UD 803 CHAPTER 14 PORT FUNCTIONS Figure 14-14. Block Diagram of Type J-1 WRPFC PFCmn WRPMC PMCmn WRPM PMmn Internal bus A Output signal in control mode WRPORT Selector Selector Pmn Pmn Selector Selector B Address RD Remarks 1. mn = 13, 55 2. A: Active in output port mode or control mode B: Masked in cycles other than read cycles 804 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-15. Block Diagram of Type J-2 WRPFC PFCCSn WRPMC Output buffer off signalNote PMCCSn WRPM PMCSn Internal bus A Selector Output signal in control mode WRPORT Selector PCSn PCSn Selector Selector B Address RD Note Signal that becomes active by bus hold and reset Remarks 1. n = 2, 5 2. A: Active in output port mode or control mode B: Masked in cycles other than read cycles User's Manual U16031EJ4V1UD 805 CHAPTER 14 PORT FUNCTIONS Figure 14-16. Block Diagram of Type J-3 WRPFC PFCCTn WRPMC Output buffer off signalNote PMCCTn WRPM PMCTn Internal bus A Selector Output signal in control mode WRPORT Selector PCTn PCTn Selector Selector B Address RD Note Signal that becomes active by bus hold and reset Remarks 1. n = 0 to 3 2. A: Active in output port mode or control mode B: Masked in cycles other than read cycles 806 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-17. Block Diagram of Type L-1 WRPFC PFC7n WRPMC PMC7n WRPM PM7n A Internal bus Selector WRPORT Output signal in control mode Selector P7n P7n Selector Address RD Remarks 1. n = 4, 7 2. A: Active in output port mode or control mode B: Masked in cycles other than read cycles Selector B User's Manual U16031EJ4V1UD 807 CHAPTER 14 PORT FUNCTIONS Figure 14-18. Block Diagram of Type L-2 WRPFC A PFC7n WRPMC PMC7n WRPM B PM7n Internal bus Selector WRPORT Output signal in control mode P7n P7n Selector Address C RD Input signal in control mode Remarks 1. n = 3, 6 2. A: Active in output control mode B: Active in output port mode C: Masked in port mode or output control mode 808 User's Manual U16031EJ4V1UD Selector CHAPTER 14 PORT FUNCTIONS Figure 14-19. Block Diagram of Type L-3 WRINTR INTR67 WRINTF INTF67 WRPFC A PFC67 WRPMC PMC67 Internal bus WRPM B PM67 Selector WRPORT Output signal in control mode P67 P67 Selector Address Selector RD Input signal in control mode C Noise elimination Edge detection Remark A: Active in output control mode B: Active in output port mode C: Masked in port mode or output control mode User's Manual U16031EJ4V1UD 809 CHAPTER 14 PORT FUNCTIONS Figure 14-20. Block Diagram of Type L-4 WRPFC PFC7n WRPMC PMC7n WRPM A Internal bus PM7n WRPORT P7n P7n Selector Address RD B Input signal in control mode Selector Remarks 1. n = 2, 5 2. A: Active in output port mode B: Masked in port mode 810 User's Manual U16031EJ4V1UD Selector CHAPTER 14 PORT FUNCTIONS Figure 14-21. Block Diagram of Type L-5 WRINTR INTR6n WRINTF INTF6n WRPFC PFC6n WRPMC PMC6n Internal bus WRPM A PM6n WRPORT P6n P6n Selector Address RD Input signal in control mode Selector Selector B Noise elimination Edge detection Remarks 1. n = 5, 6 2. A: Active in output port mode B: Masked in port mode User's Manual U16031EJ4V1UD 811 CHAPTER 14 PORT FUNCTIONS Figure 14-22. Block Diagram of Type M-1 WRINTR INTRDHn WRINTF Output enable signal in 32-bit mode INTFDHn Output buffer off signalNote WRPMC A PMCDHn WRPM PMDHn 32-bit mode select signal Internal bus WRPORT Selector Output signal in 32-bit mode PDHn PDHn Selector Address Selector RD Input signal in control mode Noise elimination Edge detection B C 32-bit mode select signal Output enable signal in 32-bit mode Input signal in 32-bit mode Note Signal that becomes active in IDLE mode and software STOP mode, and by bus hold and reset Remarks 1. n = 0, 1, 3, 4 2. A: Active in output port mode B: Active in read cycle of port mode, or in control mode or 32-bit mode C: Masked in port mode or 32-bit mode 812 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-23. Block Diagram of Type M-2 WRINTR INTRDHn WRINTF Output enable signal in 32-bit mode INTFDHn WRPFC A PFCDHn WRPMC Output buffer off signalNote PMCDHn WRPM Internal bus B PMDHn Select signal in 32-bit mode Selector WRPORT Output signal in control mode Selector Output signal in 32-bit mode PDHn PDHn Selector Selector Address C RD Input signal in control mode D Noise elimination Edge detection 32-bit mode select signal Output enable signal in 32-bit mode Input signal in 32-bit mode Note Signal that becomes active in IDLE mode and software STOP mode, and by bus hold and reset Remarks 1. n = 2, 5, 8, 12, 14, 15 2. A: Active in output control mode B: Active in output port mode C: Active in read cycle of port mode, or in input control mode or 32-bit mode D: Masked in port mode, input control mode, or 32-bit mode User's Manual U16031EJ4V1UD 813 CHAPTER 14 PORT FUNCTIONS Figure 14-24. Block Diagram of Type M-3 WRINTR INTRDHn WRINTF INTFDHn WRPFC Output enable signal in 32-bit mode Output buffer off signalNote PFCDHn WRPMC PMCmn WRPM Internal bus A PMmn Output signal in 32-bit mode Selector WRPORT Output signal in control mode Selector Output signal in 32-bit mode PDHn Pmn Selector Address Selector RD C B Selector User's Manual U16031EJ4V1UD Input signal in control mode Noise elimination Edge detection 32-bit mode select signal Output enable signal in 32-bit mode Input signal in 32-bit mode Note Signal that becomes active in IDLE mode and software STOP mode, and by bus hold and reset Remarks 1. n = 6, 7, 9, 10, 11, 13 2. A: Active in output port mode B: Active in read cycle of port mode, or in control mode or 32-bit mode C: Masked in port mode or 32-bit mode 814 CHAPTER 14 PORT FUNCTIONS 14.3 Port Pin Functions 14.3.1 Port 1 Port 1 is a 4-bit I/O port that can be set to the input or output mode in 1-bit units. 7 P1 0 6 0 5 0 4 0 3 P13 2 P12 1 P11 0 P10 Address FFFFF402H After reset Undefined Bit position 3 to 0 Bit name P1n (n = 3 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, the port 1 pins can also operate as serial interface I/O (CSI30, UARTB0), USB clock signal input, and external interrupt request input in the control mode. (1) Operation in control mode Pin Name Pin No. GM P10 P11 159 155 F1 V11 R9 INTP10/UCLK INTP11/SCK0 External interrupt input/USB clock signal input External interrupt request input/ serial interface (CSI30) I/O Serial interface (CSI30) I/O/ serial interface (UARTB0) I/O F-3 H-1 Alternate Function Remark Block Type P12 P13 154 153 P9 V9 SI0/RXD0 SO0/TXD0 F-1 J-1 Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 815 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port 1 I/O mode setting is performed by the port 1 mode register (PM1), and the control mode setting is performed by the port 1 mode control register (PMC1) and port 1 function control register (PFC1). (a) Port 1 mode register (PM1) This register can be read or written in 8-bit or 1-bit units. 7 PM1 1 6 1 5 1 4 1 3 PM13 2 PM12 1 PM11 0 PM10 Address FFFFF422H After reset FFH Bit position 3 to 0 Bit name PM1n (n = 3 to 0) Specifies input/output mode for P1n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) Function (b) Port 1 mode control register (PMC1) This register can be read or written in 8-bit or 1-bit units. 7 PMC1 0 6 0 5 0 4 0 3 PMC13 2 PMC12 1 PMC11 0 PMC10 Address FFFFF442H After reset 00H Bit position 3 Bit name PMC13 Function Specifies operation mode of P13 pin in combination with the PFC1 register. 0: I/O port mode 1: SO0 output mode/TXD0 output mode 2 PMC12 Specifies operation mode of P12 pin in combination with the PFC1 register. 0: I/O port mode 1: SI0 input mode/RXD0 input mode 1 PMC11 Specifies operation mode of P11 pin in combination with the PFC1 register. 0: I/O port mode 1: External interrupt request (INTP11) input mode/SCK0 I/O mode 0 PMC10 Specifies operation mode of P10 pin in combination with the PFC1 register. 0: I/O port mode 1: External interrupt request (INTP10) input mode/UCLK input mode 816 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (c) Port 1 function control register (PFC1) This register can be read or written in 8-bit or 1-bit units. Caution When the port mode is specified by the port 1 mode control register (PMC1), the setting of this register becomes invalid. 7 PFC1 0 6 0 5 0 4 0 3 PFC13 2 PFC12 1 PFC11 0 PFC10 Address FFFFF462H After reset 00H Bit position 3 Bit name PFC13 Function Specifies operation mode of P13 pin in control mode. 0: SO0 output mode 1: TXD0 output mode 2 PFC12 Specifies operation mode of P12 pin in control mode. 0: SI0 input mode 1: RXD0 input mode 1 PFC11 Specifies operation mode of P11 pin in control mode. 0: External interrupt request (INTP11) input mode 1: SCK0 I/O mode 0 PFC10 Specifies operation mode of P10 pin in control mode. 0: External interrupt request (INPT10) input mode 1: UCLK input mode User's Manual U16031EJ4V1UD 817 CHAPTER 14 PORT FUNCTIONS (3) Selecting interrupt trigger mode The valid edges of the INTP10 and INTP11 pins can be selected by program. The levels to be detected can also be selected. External interrupt rising edge specification register 1 (INTR1) and external interrupt falling edge specification register 1 (INTF1) are used to specify the valid edge and level detection. (a) External interrupt rising edge specification register 1 (INTR1) and external interrupt falling edge specification register 1 (INTF1) These registers are used to specify the trigger mode of the external interrupt requests (INTP10 and INTP11) from external pins. The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTF10 and INTR10 bits: INTP10 * INTF11 and INTR11 bits: INTP11 The valid edge can be independently selected from the rising edge, falling edge, and both rising and falling edges. Both the registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC1 register before setting the trigger mode of the INTP10 and INTP11 pins. If the PMC1 register is set after the INTR1 and INTF1 registers have been set, an illegal interrupt may occur when the PMC1 register is set. 818 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 7 INTR1 0 6 0 5 0 4 0 3 0 2 0 1 INTR11 0 INTR10 Address FFFFFC22H After reset 03H INTF1 0 0 0 0 0 0 INTF11 INTF10 FFFFFC02H 00H Bit position 1, 0 Bit name INTF1n, INTR1n (n = 0, 1) Function Specify trigger mode of INTP10 and INTP11 pins. INTF1n 0 0 1 1 INTR1n 0 1 0 1 Falling edge Rising edge Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Operation Notes 1. The level of the INTP1n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P1IFn bit (n = 0, 1). Consequently, even when the CPU acknowledges the interrupt and the P1IFn bit of the interrupt control register (P1ICn) is automatically cleared to 0, the P1IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP1n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P1IFn bit to 0. 2. If a level-detected interrupt request (INTP1n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP1n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP1n) is held pending (n = 0, 1). To not acknowledge the interrupt request of INTP1n, clear the P1IFn bit of the interrupt control register. User's Manual U16031EJ4V1UD 819 CHAPTER 14 PORT FUNCTIONS 14.3.2 Port 2 Port 2 is an I/O port that can be set to the input or output mode in 1-bit units except for P20, which is an input-only pin. P20 always functions as an NMI pin. The level of the NMI pin can be read by reading the P20 bit of the P2 register. 7 P2 0 6 0 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 Address FFFFF404H After reset Undefined Bit position 5 to 0 Bit name P2n (n = 5 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, the port 2 pins can also operate as the serial interface (CSI31, UARTB1) I/O and external interrupt request input in the control mode. (1) Operation in control mode Pin Name Pin No. GM P20 P21 P22 P23 P24 P25 152 149 148 147 146 145 F1 T9 T8 U8 P8 V7 U7 NMI INTP21/RXD1 INTP22/TXD1 INTP23/SCK1 INTP24/SI1 INTP25/SO1 Non-maskable interrupt request input External interrupt request input/ serial interface (UARTB1) I/O External interrupt request input/ serial interface (CSI31) I/O A-1 F-4 G-2 H-1 F-4 G-2 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 820 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port 2 I/O mode setting is performed by the port 2 mode register (PM2), and the control mode setting is performed by the port 2 mode control register (PMC2) and the port 2 function control register (PFC2). (a) Port 2 mode register (PM2) This register can be read or written in 8-bit or 1-bit units. 7 PM2 1 6 1 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 1 Address FFFFF424H After reset FFH Bit position 5 to 1 Bit name PM2n (n = 5 to 1) Specifies input/output mode for P2n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) Function (b) Port 2 mode control register (PMC2) This register can be read or written in 8-bit or 1-bit units. 7 PMC2 0 6 0 5 PMC25 4 PMC24 3 PMC23 2 PMC22 1 PMC21 0 1 Address FFFFF444H After reset 01H Bit position 5 Bit name PMC25 Function Specifies operation mode of P25 pin in combination with the PFC2 register. 0: I/O port mode 1: External interrupt request (INTP25) input mode/SO1 output mode 4 PMC24 Specifies operation mode of P24 pin in combination with the PFC2 register. 0: I/O port mode 1: External interrupt request (INTP24) input mode/SI1 input mode 3 PMC23 Specifies operation mode of P23 pin in combination with the PFC2 register. 0: I/O port mode 1: External interrupt request (INTP23) input mode/SCK1 I/O mode 2 PMC22 Specifies operation mode of P22 pin in combination with the PFC2 register. 0: I/O port mode 1: External interrupt request (INTP22) input mode/TXD1 output mode 1 PMC21 Specifies operation mode of P21 pin in combination with the PFC2 register. 0: I/O port mode 1: External interrupt request (INTP21) input mode/RXD1 input mode User's Manual U16031EJ4V1UD 821 CHAPTER 14 PORT FUNCTIONS (c) Port 2 function control register (PFC2) This register can be read or written in 8-bit or 1-bit units. Caution When the port mode is specified by the port 2 mode control register (PMC2), the PFC2 setting becomes invalid. 7 PFC2 0 6 0 5 PFC25 4 PFC24 3 PFC23 2 PFC22 1 PFC21 0 0 Address FFFFF464H After reset 00H Bit position 5 Bit name PFC25 Function Specifies operation mode of P25 pin in control mode. 0: External interrupt request (INTP25) input mode 1: SO1 output mode 4 PFC24 Specifies operation mode of P24 pin in control mode. 0: External interrupt request (INTP24) input mode 1: SI1 input mode 3 PFC23 Specifies operation mode of P23 pin in control mode. 0: External interrupt request (INTP23) input mode 1: SCK1 I/O mode 2 PFC22 Specifies operation mode of P22 pin in control mode. 0: External interrupt request (INTP22) input mode 1: TXD1 output mode 1 PFC21 Specifies operation mode of P21 pin in control mode. 0: External interrupt request (INTP21) input mode 1: RXD1 input mode 822 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (3) Selecting interrupt trigger mode The valid edges of the INTP2n and NMI pins can be selected by program (n = 1 to 5). The level detection of the INTP2n pin can also be selected. External interrupt rising edge specification register 2 (INTR2) and external interrupt falling edge specification register 2 (INTF2) are used to specify the valid edge and level detection. (a) External interrupt rising edge specification register 2 (INTR2) and external interrupt falling edge specification register 2 (INTF2) These registers are used to specify the trigger mode of an external interrupt request (INTP2n) from an external pin and the non-maskable interrupt (NMI) (n = 1 to 5). The correspondence between each bit of this register and the external interrupt request and non-maskable interrupt controlled by that bit is as follows. * NMIF0 and NMIR0 bits: NMI * INTF21 and INTR21 bits: INTP21 * INTF22 and INTR22 bits: INTP22 * INTF23 and INTR23 bits: INTP23 * INTF24 and INTR24 bits: INTP24 * INTF25 and INTR25 bits: INTP25 The rising edge, falling edge, or both the rising and falling edges can be specified as the valid edge of the INTP2n pin and the rising or falling edge can be specified as the valid edge of the NMI pin, independently for each pin. Both the registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC2 register before setting the trigger mode of the INTP2n pin (n = 1 to 5). If the PMC2 register is set after the INTR2 and INTF2 registers have been set, an illegal interrupt may occur when the PMC2 register is set. User's Manual U16031EJ4V1UD 823 CHAPTER 14 PORT FUNCTIONS 7 INTR2 0 6 0 5 INTR25 4 INTR24 3 INTR23 2 INTR22 1 INTR21 0 NMIR0 Address FFFFFC24H After reset 3FH INTF2 0 0 INTF25 INTF24 INTF23 INTF22 INTF21 NMIF0 FFFFFC04H 00H Bit position 5 to 1 Bit name INTF2n, INTR2n (n = 1 to 5) Specify trigger mode of INTP2n pin. INTF2n 0 0 1 1 INTR2n 0 1 0 1 Falling edge Rising edge Function Operation Level detection (low-level detection) Both rising and falling edges Notes 1, 2 0 NMIF0, NMIR0 Specify trigger mode of NMI pin. NMIF0 0 0 1 1 NMIR0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Operation Notes 1. The level of the INTP2n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P2IFn bit (n = 1 to 5). Consequently, even when the CPU acknowledges the interrupt and the P2IFn bit of the interrupt control register (P2ICn) is automatically cleared to 0, the P2IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP2n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P2IFn bit to 0. 2. If a level-detected interrupt request (INTP2n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP2n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP2n) is held pending (n = 1 to 5). To not acknowledge the interrupt request of INTP2n, clear the P2IFn bit of the interrupt control register. 824 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.3.3 Port 5 Port 5 is a 6-bit I/O port that can be set to the input or output mode in 1-bit units. 7 P5 0 6 0 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 Address FFFFF40AH After reset Undefined Bit position 5 to 0 Bit name P5n (n = 5 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, the port 5 pins can also operate as the DMA controller I/O, timer/counter I/O, and external interrupt request input in the control mode. (1) Operation in control mode Pin Name Pin No. GM P50 P51 25 24 F1 J15 J16 INTP50/DMARQ0 INTP51/DMAAK0 External interrupt request input/DMA request input External interrupt request input/ DMA acknowledge signal output P52 P53 23 22 J17 J18 INTP52/TC0 INTPC00/TIC0/ DMARQ1 P54 21 K15 INTPC01/DMAAK1 External interrupt request input/DMA end signal output External interrupt request and timer C0 external capture trigger input/timer/counter input/DMA request input External interrupt request and timer C0 external capture trigger input/DMA acknowledge signal output P55 20 K14 TOC0/TC1 Timer/counter output/DMA end signal output J-1 G-1 F-2 F-3 G-2 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 825 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port 5 I/O mode setting is performed by the port 5 mode register (PM5), and the control mode setting is performed by the port 5 mode control register (PMC5) and port 5 function control register (PFC5). (a) Port 5 mode register (PM5) This register can be read or written in 8-bit or 1-bit units. 7 PM5 1 6 1 5 PM55 4 PM54 3 PM53 2 PM52 1 PM51 0 PM50 Address FFFFF42AH After reset FFH Bit position 5 to 0 Bit name PM5n (n = 5 to 0) Specifies input/output mode for P5n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) Function (b) Port 5 mode control register (PMC5) This register can be read or written in 8-bit or 1-bit units. 7 PMC5 0 6 0 5 PMC55 4 PMC54 3 PMC53 2 PMC52 1 PMC51 0 PMC50 Address FFFFF44AH After reset 00H Bit position 5 Bit name PMC55 Function Specifies operation mode of P55 pin in combination with the PFC5 register. 0: I/O port mode 1: TOC0 output mode/DMA end signal (TC1) output mode 4 PMC54 Specifies operation mode of P54 pin in combination with the PFC5 register. 0: I/O port mode 1: External interrupt request and timer C0 external capture trigger (INTPC01) input mode/DMA acknowledge signal (DMAAK1) output mode 3 PMC53 Specifies operation mode of P53 pin in combination with the PFC5 register. 0: I/O port mode 1: External interrupt request and timer C0 external capture trigger (INTPC00) input mode/TIC0 input mode/DMA request (DMARQ1) input mode 2 PMC52 Specifies operation mode of P52 pin in combination with the PFC5 register. 0: I/O port mode 1: External interrupt request (INTP52) input mode/DMA end signal (TC0) output mode 1 PMC51 Specifies operation mode of P51 pin in combination with the PFC5 register. 0: I/O port mode 1: External interrupt request (INTP51) input mode/DMA acknowledge signal (DMAAK0) output mode 0 PMC50 Specifies operation mode of P50 pin in combination with the PFC5 register. 0: I/O port mode 1: External interrupt request (INTP50) input mode/DMA request (DMARQ0) input mode 826 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (c) Port 5 function control register (PFC5) This register can be read or written in 8-bit or 1-bit units. Caution When the port mode is specified by the port 5 mode control register (PMC5), the setting of this register becomes invalid. 7 PFC5 0 6 0 5 PFC55 4 PFC54 3 PFC53 2 PFC52 1 PFC51 0 PFC50 Address FFFFF46AH After reset 00H Bit position 5 Bit name PFC55 Function Specifies operation mode of P55 pin in control mode. 0: TOC0 output mode 1: DMA end signal (TC1) output mode 4 PFC54 Specifies operation mode of P54 pin in control mode. 0: External interrupt request and timer C0 external capture trigger (INTPC01) input mode 1: DMA acknowledge signal (DMAAK1) output 3 PFC53 Specifies operation mode of P53 pin in control mode. 0: External interrupt request and timer C0 external capture trigger (INTPC01) input mode/TIC0 input mode 1: DMA request (DMARQ1) input mode There is no register that selects an external interrupt request and timer C0 external capture trigger (INTPC00) input mode or TIC0 input mode. * To use TIC0 input mode: Mask the external interrupt request and external capture trigger (INTPC00) of timer C0, or use the CCC00 register as a compare register. * To use external interrupt request and external capture trigger (INTPC00) of timer C0: Clear the ETIC0 bit of the TMCC01 register to 0. 2 PFC52 Specifies operation mode of P52 pin. 0: External interrupt request (INTP52) input mode 1: DMA end signal (TC0) output mode 1 PFC51 Specifies operation mode of P51 pin. 0: External interrupt request (INTP51) input mode 1: DMA acknowledge signal (DMAAK0) output 0 PFC50 Specifies operation mode of P50 pin in control mode. 0: External interrupt request (INTP50) input mode 1: DMA request (DMARQ0) input mode User's Manual U16031EJ4V1UD 827 CHAPTER 14 PORT FUNCTIONS (3) Selecting interrupt trigger mode The valid edges of the INTP5n pin can be selected by program (n = 0 to 2). The level detection of the INTP5n pin can also be selected. External interrupt rising edge specification register 5 (INTR5) and external interrupt falling edge specification register 5 (INTF5) are used to specify the valid edge and level detection. (a) External interrupt rising edge specification register 5 (INTR5) and external interrupt falling edge specification register 5 (INTF5) These registers are used to specify the trigger mode of an external interrupt request (INTP5n) from an external pin (n = 0 to 2). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTF50 and INTR50 bits: INTP50 * INTF51 and INTR51 bits: INTP51 * INTF52 and INTR52 bits: INTP52 The rising edge, falling edge, or both the rising and falling edges can be specified as the valid edge of the INTP5n pin, independently for each pin. Both the registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC5 register before setting the trigger mode. If the PMC5 register is set after the INTR5 and INTF5 registers have been set, an illegal interrupt may occur when the PMC5 register is set. 828 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 7 INTR5 0 6 0 5 0 4 0 3 0 2 INTR52 1 INTR51 0 INTR50 Address FFFFFC2AH After reset 07H INTF5 0 0 0 0 0 INTF52 INTF51 INTF50 FFFFFC0AH 00H Bit position 2 to 0 Bit name INTF5n, INTR5n (n = 0 to 2) Specify trigger mode of INTP5n pin. INTF5n 0 0 1 1 INTR5n 0 1 0 1 Falling edge Rising edge Function Operation Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Notes 1. The level of the INTP5n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P5IFn bit (n = 0 to 2). Consequently, even when the CPU acknowledges the interrupt and the P5IFn bit of the interrupt control register (P5ICn) is automatically cleared to 0, the P5IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP5n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P5IFn bit to 0. 2. If a level-detected interrupt request (INTP5n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP5n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP5n) is held pending (n = 0 to 2). To not acknowledge the interrupt request of INTP5n, clear the P5IFn bit of the interrupt control register. User's Manual U16031EJ4V1UD 829 CHAPTER 14 PORT FUNCTIONS 14.3.4 Port 6 Port 6 is a 3-bit I/O port that can be set to the input or output mode in 1-bit units. 7 P6 P67 6 P66 5 P65 4 0 3 0 2 0 1 0 0 0 Address FFFFF40CH After reset Undefined Bit position 7 to 5 Bit name P6n (n = 7 to 5) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, the port 6 pins can also operate as the timer/counter I/O and external interrupt request input in the control mode. (1) Operation in control mode Pin Name Pin No. GM P65 19 F1 K16 INTP65/INTPC10/ TIC1 External interrupt request and timer C1 external capture trigger input/ timer/counter input External interrupt request and timer C1 external capture trigger input P67 17 L18 INTP67/TOC1 External interrupt request input/ timer/counter output L-3 L-5 Alternate Function Remark Block Type P66 18 K17 INTP66/INTPC11 Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 830 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port 6 I/O mode setting is performed by the port 6 mode register (PM6), and the control mode setting is performed by the port 6 mode control register (PMC6) and port 6 function control register (PFC6). (a) Port 6 mode register (PM6) This register can be read or written in 8-bit or 1-bit units. 7 PM6 PM67 6 PM66 5 PM65 4 1 3 1 2 1 1 1 0 1 Address FFFFF42CH After reset FFH Bit position 7 to 5 Bit name PM6n (n = 7 to 5) Specifies input/output mode for P6n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) Function (b) Port 6 mode control register (PMC6) This register can be read or written in 8-bit or 1-bit units. 7 PMC6 PMC67 6 PMC66 5 PMC65 4 0 3 0 2 0 1 0 0 0 Address FFFFF44CH After reset 00H Bit position 7 Bit name PMC67 Specifies operation mode of P67 pin. Function 0: I/O port mode 1: External interrupt request (INTP67) input mode/TOC1 output mode 6 PMC66 Specifies operation mode of P66 pin. 0: I/O port mode 1: External interrupt request (INTP66) input mode/external interrupt request and timer C1 external capture trigger (INTPC11) input mode 5 PMC65 Specifies operation mode of P65 pin. 0: I/O port mode 1: External interrupt request (INTP65) input mode/external interrupt request and timer C1 external capture trigger (INTPC10) input mode/TIC1 input mode User's Manual U16031EJ4V1UD 831 CHAPTER 14 PORT FUNCTIONS (c) Port 6 function control register (PFC6) This register can be read or written in 8-bit or 1-bit units. Caution When the port mode is specified by the port 6 mode control register (PMC6), the setting of this register becomes invalid. 7 PFC6 PFC67 6 PFC66 5 PFC65 4 0 3 0 2 0 1 0 0 0 Address FFFFF46CH After reset 00H Bit position 7 Bit name PFC67 Function Specifies operation mode of P67 pin in control mode. 0: External interrupt request (INTP67) input mode 1: TOC1 output mode 6 PFC66 Specifies operation mode of P66 pin in control mode. 0: External interrupt request (INTP66) input mode 1: External interrupt request and timer C1 external capture trigger (INTPC11) input mode 5 PFC65 Specifies operation mode of P65 pin in control mode. 0: External interrupt request (INTP65) input mode 1: External interrupt request and timer C1 external capture trigger (INTPC10) input mode/TIC1 input mode There is no register that selects an external interrupt request and timer C1 external capture trigger (INTPC10) input mode or TIC1 input mode. * To use TIC1 input mode: Mask the external interrupt request and external capture trigger (INTPC10) of timer C1, or use the CCC10 register as a compare register. * To use external interrupt request and external capture trigger (INTPC10) of timer C1: Clear the ETIC1 bit of the TMCC11 register to 0. 832 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (3) Selecting interrupt trigger mode The valid edges of the INTP6n pin can be selected by program (n = 5 to 7). The level detection of the INTP6n pin can also be selected. External interrupt rising edge specification register 6 (INTR6) and external interrupt falling edge specification register 6 (INTF6) are used to specify the valid edge and level detection. (a) External interrupt rising edge specification register 6 (INTR6) and external interrupt falling edge specification register 6 (INTF6) These registers are used to specify the trigger mode of an external interrupt request (INTP6n) from an external pin (n = 5 to 7). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTF65 and INTR65 bits: INTP65 * INTF66 and INTR66 bits: INTP66 * INTF67 and INTR67 bits: INTP67 The rising edge, falling edge, or both the rising and falling edges can be specified as the valid edge of the INTP6n pin, independently for each pin. Both the registers can be read or written in 8-bit or 1-bit units. Caution Set the PMC6 register before setting the trigger mode. If the PMC6 register is set after the INTR6 and INTF6 registers have been set, an illegal interrupt may occur when the PMC6 register is set. User's Manual U16031EJ4V1UD 833 CHAPTER 14 PORT FUNCTIONS 7 INTR6 INTR67 6 INTR66 5 INTR65 4 0 3 0 2 0 1 0 0 0 Address FFFFFC2CH After reset E0H INTF6 INTF67 INTF66 INTF65 0 0 0 0 0 FFFFFC0CH 00H Bit position 7 to 5 Bit name INTF6n, INTR6n (n = 7 to 5) Specify trigger mode of INTP6n pin. INTF6n 0 0 1 1 INTR6n 0 1 0 1 Falling edge Rising edge Function Operation Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Notes 1. The level of the INTP6n pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the P6IFn bit (n = 5 to 7). Consequently, even when the CPU acknowledges the interrupt and the P6IFn bit of the interrupt control register (P6ICn) is automatically cleared to 0, the P6IFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTP6n pin of the external device inactive in the interrupt servicing routine, and forcibly clear the P6IFn bit to 0. 2. If a level-detected interrupt request (INTP6n) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTP6n) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTP6n) is held pending (n = 5 to 7). To not acknowledge the interrupt request of INTP6n, clear the P6IFn bit of the interrupt control register. 834 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.3.5 Port 7 Port 7 is a 6-bit I/O port that can be set to the input or output mode in 1-bit units. 7 P7 P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 0 0 0 Address FFFFF40EH After reset Undefined Bit position 7 to 2 Bit name P7n (n = 7 to 2) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, the port 7 pins can also operate as the DMA controller I/O, timer/counter I/O, and external interrupt request input in the control mode. (1) Operation in control mode Pin Name Pin No. GM P72 176 F1 U17 INTPC20/TIC2/ DMARQ2 External interrupt request and timer C2 external capture trigger input/ timer/counter input/DMA request input External interrupt request and timer C2 external capture trigger input/DMA acknowledge signal output P74 P75 174 173 V17 T15 TOC2/TC2 INTPC30/TIC3/ DMARQ3 Timer/counter output/DMA end signal output External interrupt request and timer C3 external capture trigger input/ timer/counter input/DMA request input External interrupt request and timer C3 external capture trigger input/DMA acknowledge signal output P77 171 V16 TOC3/TC3 Timer/counter output/DMA end signal output L-1 L-2 L-1 L-4 L-2 L-4 Alternate Function Remark Block Type P73 175 U16 INTPC21/DMAAK2 P76 172 U15 INTPC31/DMAAK3 Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 835 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port 7 I/O mode setting is performed by the port 7 mode register (PM7), and the control mode setting is performed by the port 7 mode control register (PMC7) and port 7 function control register (PFC7). (a) Port 7 mode register (PM7) This register can be read or written in 8-bit or 1-bit units. 7 PM7 PM77 6 PM76 5 PM75 4 PM74 3 PM73 2 PM72 1 1 0 1 Address FFFFF42EH After reset FFH Bit position 7 to 2 Bit name PM7n (n = 7 to 2) Specifies input/output mode for P7n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) Function (b) Port 7 mode control register (PMC7) This register can be read or written in 8-bit or 1-bit units. 7 PMC7 PMC77 6 PMC76 5 PMC75 4 PMC74 3 PMC73 2 PMC72 1 0 0 0 Address FFFFF44EH After reset 00H Bit position 7 Bit name PMC77 Function Specifies operation mode of P77 pin in combination with the PFC7 register. 0: I/O port mode 1: TOC3 output mode/DMA end signal (TC3) output mode 6 PMC76 Specifies operation mode of P76 pin in combination with the PFC7 register. 0: I/O port mode 1: External interrupt request and time C3 external capture trigger (INTPC31) input mode/DMA acknowledge signal (DMAAK3) output mode 5 PMC75 Specifies operation mode of P75 pin in combination with the PFC7 register. 0: I/O port mode 1: External interrupt request and timer C3 external capture trigger (INTPC30) input mode/TIC3 input mode/DMA request (DMARQ3) input mode 4 PMC74 Specifies operation mode of P74 pin in combination with the PFC7 register. 0: I/O port mode 1: TOC2 output mode/DMA end signal (TC2) output mode 3 PMC73 Specifies operation mode of P73 pin in combination with the PFC7 register. 0: I/O port mode 1: External interrupt request and time C2 external capture trigger (INTPC21) input mode/DMA acknowledge signal (DMAAK2) output mode 2 PMC72 Specifies operation mode of P72 pin in combination with the PFC7 register. 0: I/O port mode 1: External interrupt request and timer C2 external capture trigger (INTPC20) input mode/TIC2 input mode/DMA request (DMARQ2) input mode 836 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (c) Port 7 function control register (PFC7) This register can be read or written in 8-bit or 1-bit units. Caution When the port mode is specified by the port 7 mode control register (PMC7), the setting of this register becomes invalid. 7 PFC7 PFC77 6 PFC76 5 PFC75 4 PFC74 3 PFC73 2 PFC72 1 0 0 0 Address FFFFF46EH After reset 00H Bit position 7 Bit name PFC77 Function Specifies operation mode of P77 pin in control mode. 0: TOC3 output mode 1: DMA end signal (TC3) output mode 6 PFC76 Specifies operation mode of P76 pin in control mode. 0: External interrupt request and timer C3 external capture trigger (INTPC31) input mode 1: DMA acknowledge signal (DMAAK3) output 5 PFC75 Specifies operation mode of P75 pin in control mode. 0: External interrupt request and timer C3 external capture trigger (INTPC30) input mode/TIC3 input mode 1: DMA request (DMARQ3) input mode There is no register that selects an external interrupt request and timer C3 external capture trigger (INTPC30) input mode or TIC3 input mode. * To use TIC3 input mode: Mask the external interrupt request and external capture trigger (INTPC30) of timer C3, or use the CCC30 register as a compare register. * To use external interrupt request and external capture trigger (INTPC30) of timer C3: Clear the ETIC3 bit of the TMCC31 register to 0. 4 PFC74 Specifies operation mode of P74 pin. 0: TOC2 output mode 1: DMA end signal (TC2) output mode 3 PFC73 Specifies operation mode of P73 pin. 0: External interrupt request and timer C2 external capture trigger (INTPC21) input mode 1: DMA acknowledge signal (DMAAK2) output 2 PFC72 Specifies operation mode of P72 pin in control mode. 0: External interrupt request and timer C2 external capture trigger (INTPC20) input mode/TIC2 input mode 1: DMA request (DMARQ2) input mode There is no register that selects an external interrupt request and timer C2 external capture trigger (INTPC20) input mode or TIC2 input mode. * To use TIC2 input mode: Mask the external interrupt request and external capture trigger (INTPC20) of timer C2, or use the CCC20 register as a compare register. * To use external interrupt request and external capture trigger (INTPC20) of timer C2: Clear the ETIC2 bit of the TMCC21 register to 0. User's Manual U16031EJ4V1UD 837 CHAPTER 14 PORT FUNCTIONS 14.3.6 Port AL Port AL (PAL) is a 16-bit I/O port that can be set to the input or output mode in 1-bit units. When the higher 8 bits of port AL are used as port ALH (PALH) and the lower 8 bits as port ALL (PALL), port AL becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. 15 PAL 0 7 0 14 0 6 0 13 0 5 0 12 0 4 0 11 0 3 0 10 0 2 0 9 0 1 PAL1 8 0 0 PAL0 Address FFFFF001H Address FFFFF000H After reset Undefined Bit position 1, 0 Bit name PALn (n = 1, 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their functions as port pins, in the control mode, the port AL pins operate as an address bus for when the memory is externally expanded and external interrupt request input. (1) Operation in control mode Pin Name Pin No. GM PAL0 PAL1 76 75 F1 D7 C7 INTPL0/A0 INTPL1/A1 Address bus when memory expanded/ external interrupt request input G-3 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 838 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port AL I/O mode setting is performed by the port AL mode register (PMAL), and control mode setting is performed by port AL mode control register L (PMCALL) and the port AL function control register (PFCAL). (a) Port AL mode register (PMAL) The port AL mode register (PMAL) can be read or written in 16-bit units. When using the higher 8 bits of PMAL as port AL mode register H (PMALH) and the lower 8 bits as port AL mode register L (PMALL), the PMALH register is read-only, in 8-bit or 1-bit units, and the PMALL register can be read or written in 8-bit or 1-bit units. 15 PMAL 1 7 1 14 1 6 1 13 1 5 1 12 1 4 1 11 1 3 1 10 1 2 1 9 1 1 PMAL1 8 1 0 PMAL0 Address FFFFF021H Address FFFFF020H After reset FFFFH Bit position 1, 0 Bit name PMALn (n = 1, 0) Function Specifies input/output mode for PALn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port AL mode control register (PMCAL) The port AL mode control register (PMCAL) can be read or written in 16-bit units. When using the higher 8 bits of PMCAL as port AL mode control register H (PMCALH) and the lower 8 bits as port AL mode control register L (PMCALL), the PMCALH register is read-only, in 8-bit or 1-bit units, and the PMCALL register can be read or written in 8-bit or 1-bit units. 15 PMCAL 0 7 0 14 0 6 0 13 0 5 0 12 0 4 0 11 0 3 0 10 0 2 0 9 0 1 8 0 0 Address FFFFF041H Address FFFFF040H After reset 0002H PMCAL1 PMCAL0 Bit position 1 Bit name PMCAL1 Specifies operation mode of PAL1 pin. Function 0: I/O port mode 1: INTPL1 input mode/A1 output mode 0 PMCAL0 Specifies operation mode of PAL0 pin. 0: I/O port mode 1: INTPL0 input mode/A0 output mode User's Manual U16031EJ4V1UD 839 CHAPTER 14 PORT FUNCTIONS (c) Port AL function control register L (PFCALL) This register can be read or written in 8-bit or 1-bit units. Caution When the port mode is specified by the port AL mode control register (PMCAL), the setting of this register becomes invalid. 7 PFCALL 0 6 0 5 0 4 0 3 0 2 0 1 PFCAL1 0 PFCAL0 Address FFFFF058H After reset 03H Bit position 1 Bit name PFCAL1 Function Specifies operation mode of PAL1 pin in control mode. 0: External interrupt request (INTPL1) input mode 1: A1 output mode 0 PFCAL0 Specifies operation mode of PAL0 pin in control mode. 0: External interrupt request (INTPL0) input mode 1: A0 output mode 840 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (3) Selecting interrupt trigger mode The valid edges of the INTPLn pin can be selected by program (n = 0, 1). The level detection of the INTPLn pin can also be selected. External interrupt rising edge specification register AL (INTRAL) and external interrupt falling edge specification register AL (INTFAL) are used to specify the valid edge and level detection. (a) External interrupt rising edge specification register AL (INTRAL) and external interrupt falling edge specification register AL (INTFAL) These registers are used to specify the trigger mode of an external interrupt request (INTPLn) from an external pin (n = 0, 1). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTFAL0 and INTRAL0 bits: INTPAL0 * INTFAL1 and INTRAL1 bits: INTPAL1 The rising edge, falling edge, or both the rising and falling edges can be specified as the valid edge of the INTPLn pin, independently for each pin. Both the registers can be read or written in 8-bit or 1-bit units. Caution Before setting the trigger mode, set the PMCAL register. If the PMCAL register is set after the INTRAL and INTFAL registers have been set, an illegal interrupt may occur when the PMCAL register is set. User's Manual U16031EJ4V1UD 841 CHAPTER 14 PORT FUNCTIONS 7 INTRAL 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFFC30H After reset 03H INTRAL1 INTRAL0 INTFAL 0 0 0 0 0 0 INTFAL1 INTFAL0 FFFFFC10H 00H Bit position 1, 0 Bit name INTFALn, INTRALn (n = 0, 1) Specify trigger mode of INTPLn pin. INTFALn 0 0 1 1 INTRALn 0 1 0 1 Falling edge Rising edge Function Operation Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Notes 1. The level of the INTPLn pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the PLIFn bit (n = 0, 1). Consequently, even when the CPU acknowledges the interrupt and the PLIFn bit of the interrupt control register (PLICn) is automatically cleared to 0, the PLIFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTPLn pin of the external device inactive in the interrupt servicing routine, and forcibly clear the PLIFn bit to 0. 2. If a level-detected interrupt request (INTPLn) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTPLn) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTPLn) is held pending (n = 0, 1). To not acknowledge the interrupt request of INTPLn, clear the PLIFn bit of the interrupt control register. 842 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.3.7 Port AH Port AH (PAH) is a 10-bit I/O port that can be set in the input or output mode in 1-bit units. When the higher 8 bits of port AH are used as port AHH (PAHH) and the lower 8 bits as port AHL (PAHL), port AH becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. 15 PAH 0 7 PAH7 14 0 6 PAH6 13 0 5 PAH5 12 0 4 PAH4 11 0 3 PAH3 10 0 2 PAH2 9 PAH9 1 PAH1 8 PAH8 0 PAH0 Address FFFFF003H Address FFFFF002H After reset Undefined Bit position 9 to 0 Bit name PAHn (n = 9 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their functions as port pins, in the control mode, the port AH pins operate as an address bus for when the memory is externally expanded. (1) Operation in control mode Pin Name Pin No. GM PAH0 PAH1 PAH2 PAH3 PAH4 PAH5 PAH6 PAH7 PAH8 PAH9 58 57 52 51 50 49 48 47 46 45 F1 B11 E11 C13 D13 C14 A15 C15 A16 B16 A17 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 Address bus when memory expanded D-2 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 843 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port AH I/O mode setting is performed by the port AH mode register (PMAH), and the control mode setting is performed by the port AH mode control register (PMCAH). (a) Port AH mode register (PMAH) The port AH mode register (PMAH) can be read or written in 16-bit units. If the higher 8 bits of PMAH are used as port AH mode register H (PMAHH), and the lower 8 bits as port AH mode register L (PMAHL), these two 8-bit port mode registers can be read or written in 8-bit or 1-bit units. 15 PMAH 1 7 PMAH7 14 1 6 PMAH6 13 1 5 PMAH5 12 1 4 PMAH4 11 1 3 PMAH3 10 1 2 PMAH2 9 PMAH9 1 PMAH1 8 PMAH8 0 PMAH0 Address FFFFF023H Address FFFFF022H After reset FFFFH Bit position 9 to 0 Bit name PMAHn (n = 9 to 0) Function Specifies input/output mode for PAHn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port AH mode control register (PMCAH) The port AH mode control register (PMCAH) can be read or written in 16-bit units. If the higher 8 bits of PMCAH are used as port AH mode control register H (PMCAHH), and the lower 8 bits as port AH mode control register L (PMCAHL), these two 8-bit port mode registers can be read or written in 8-bit or 1-bit units. 15 PMCAH 0 7 14 0 6 13 0 5 12 0 4 11 0 3 10 0 2 9 8 Address FFFFF043H Address FFFFF042H After reset 03FFH PMCAH9 PMCAH8 1 0 PMCAH7 PMCAH6 PMCAH5 PMCAH4 PMCAH3 PMCAH2 PMCAH1 PMCAH0 Bit position 9 to 0 Bit name PMCAHn (n = 9 to 0) Specifies operation mode of PAHn pin. 0: I/O port mode 1: A25 to A16 output mode Function 844 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.3.8 Port DH Port DH (PDH) is a 16-bit I/O port that can be set in the input or output mode in 1-bit units. When the higher 8 bits of port DH are used as port DHH (PDHH), and the lower 8 bits as port DHL (PDHL), port DH becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. Caution In the 32-bit mode (MODE1 and MODE0 pins = 00) and when the BMODCN bit of the PFCDH register is set, all the register functions of port DH (see 14.3.8) become invalid. 15 PDH PDH15 7 PDH7 14 PDH14 6 PDH6 13 PDH13 5 PDH5 12 PDH12 4 PDH4 11 PDH11 3 PDH3 10 PDH10 2 PDH2 9 PDH9 1 PDH1 8 PDH8 0 PDH0 Address FFFFF007H Address FFFFF006H After reset Undefined Bit position 15 to 0 Bit name PDHn (n = 15 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their functions as port pins, in the control mode, the port DH pins operate as a data bus for when the memory is externally expanded, timer/counter I/O, PWM output, and external interrupt request input. User's Manual U16031EJ4V1UD 845 CHAPTER 14 PORT FUNCTIONS (1) Operation in control mode Pin Name Pin No. GM PDH0 PDH1 PDH2 112 113 114 F1 K3 K4 K5 D16/INTPD0 D17/INTPD1 D18/INTPD2/TOC4 Data bus when memory expanded/ external interrupt request input Data bus when memory expanded/ external interrupt request input Data bus when memory expanded/ external interrupt request input/ timer/counter output Data bus when memory expanded/ external interrupt request input Data bus when memory expanded/ external interrupt request input Data bus when memory expanded/ external interrupt request input/ timer/counter output Data bus when memory expanded/ external interrupt request input/ timer ENC10 external capture trigger input/ timer/counter input Data bus when memory expanded/ external interrupt request input/ timer ENC10 external capture trigger input/ timer/counter input Data bus when memory expanded/ external interrupt request input/ timer/counter output Data bus when memory expanded/ external interrupt request input/ timer/counter input Data bus when memory expanded/ external interrupt request input/ timer ENC11 external capture trigger input/ timer/counter input Data bus when memory expanded/ external interrupt request input/ timer ENC11 external capture trigger input/ timer/counter input Data bus when memory expanded/ external interrupt request input/ timer/counter output Data bus when memory expanded/ external interrupt request input/ timer/counter input Data bus when memory expanded/ external interrupt request input/PWM output Data bus when memory expanded/ external interrupt request input/PWM output M-2 M-2 M-2 M-2 M-1 Alternate Function Remark Block Type PDH3 PDH4 PDH5 117 118 119 L4 L5 M2 D19/INTPD3 D20/INTPD4 D21/INTPD5/TOC5 M-1 PDH6 120 M3 D22/INTPD6/ INTP100/TCUD10 M-3 PDH7 121 N1 D23/INTPD7/ INTP101/TCLR10 PDH8 122 N2 D24/INTPD8/TO10 PDH9 123 N3 D25/INTPD9/ TIUD10 D26/INTPD10/ INTP110/TCUD11 M-3 PDH10 124 N4 PDH11 125 P2 D27/INTPD11/ INTP111/TCLR11 PDH12 126 R1 D28/INTPD12/TO11 PDH13 127 P3 D29/INTPD13/ TIUD11 D30/INTPD14/ PWM0 D31/INTPD15/ PWM1 M-3 PDH14 PDH15 130 131 R3 U1 M-2 Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 846 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port DH I/O mode setting is performed by the port DH mode register (PMDH), and the control mode setting is performed by the port DH mode control register (PMCDH) and port DH function control register (PFCDH). (a) Port DH mode register (PMDH) The port DH mode register (PMDH) can be read or written in 16-bit units. If the higher 8 bits of PMDH are used as port DH mode register H (PMDHH), and the lower 8 bits as port DH mode register L (PMDHL), these two 8-bit port mode registers can be read or written in 8-bit or 1-bit units. 15 14 13 12 11 10 9 PMDH9 1 PMDH1 8 PMDH8 0 PMDH0 Address FFFFF027H Address FFFFF026H After reset FFFFH PMDH PMDH15 PMDH14 PMDH13 PMDH12 PMDH11 PMDH10 7 PMDH7 6 PMDH6 5 PMDH5 4 PMDH4 3 PMDH3 2 PMDH2 Bit position 15 to 0 Bit name PMDHn (n = 15 to 0) Function Specifies input/output mode for PDHn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port DH mode control register (PMCDH) The port DH mode control register (PMCDH) can be read or written in 16-bit units. If the higher 8 bits of PMCDH are used as port DH mode control register H (PMCDHH), and the lower 8 bits as port DH mode control register L (PMCDHL), these two 8-bit port mode registers can be read or written in 8-bit or 1-bit units. (1/2) 15 14 13 12 11 10 9 8 Address FFFFF047H Address FFFFF046H After reset 0000H PMCDH PMCDH15 PMCDH14 PMCDH13 PMCDH12 PMCDH11 PMCDH10 PMCDH9 PMCDH8 7 6 5 4 3 2 1 0 PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 Bit position 15 Bit name PMCDH15 Function Specifies operation mode of PDH15 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD15) input mode/PWM1 output mode 14 PMCDH14 Specifies operation mode of PDH14 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD14) input mode/PWM0 output mode 13 PMCDH13 Specifies operation mode of PDH13 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD13) input mode/TIUD11 input mode User's Manual U16031EJ4V1UD 847 CHAPTER 14 PORT FUNCTIONS (2/2) Bit position 12 Bit name PMCDH12 Function Specifies operation mode of PDH12 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD12) input mode/TO11 output mode 11 PMCDH11 Specifies operation mode of PDH11 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD11) input mode/timer ENC11 external capture trigger (INTP111) input mode/TCLR11 input mode 10 PMCDH10 Specifies operation mode of PDH10 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD10) input mode/timer ENC11 external capture trigger (INTP110) input mode/TCUD11 input mode 9 PMCDH9 Specifies operation mode of PDH9 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD9) input mode/TIUD10 input mode 8 PMCDH8 Specifies operation mode of PDH8 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD8) input mode/TO10 output mode 7 PMCDH7 Specifies operation mode of PDH7 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD7) input mode/timer ENC10 external capture trigger (INTP101) input mode/TCLR10 input mode 6 PMCDH6 Specifies operation mode of PDH6 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD6) input mode/timer ENC10 external capture trigger (INTP100) input mode/TCUD10 input mode 5 PMCDH5 Specifies operation mode of PDH5 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD5) input mode/TOC5 output mode 4 PMCDH4 Specifies operation mode of PDH4 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD4) input mode 3 PMCDH3 Specifies operation mode of PDH3 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD3) input mode 2 PMCDH2 Specifies operation mode of PDH2 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD2) input mode/TOC4 output mode 1 PMCDH1 Specifies operation mode of PDH1 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD1) input mode 0 PMCDH0 Specifies operation mode of PDH0 pin in combination with the PFCDH register. 0: I/O port mode 1: External interrupt request (INTPD0) input mode 848 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (c) Port DH function control register (PFCDH) This register can be read or written in 8-bit or 1-bit units. If the higher 8 bits of the PFCDH are used as port DH function control register H (PFCDHH), and the lower 8 bits as port DH function control register L (PFCDHL), these registers can be read or written in 8bit or 1-bit units. Caution When the port mode is specified by the port DH mode control register (PMCDH), the setting of this register becomes invalid. However, bit 0 is independent of the setting of the PMCDH0 bit of the PMCDH register. (1/3) 15 14 13 12 11 10 9 8 Address FFFFF057H Address FFFFF056H After reset 0000H PFCDH PFCDH15 PFCDH14 PFCDH13 PFCDH12 PFCDH11 PFCDH10 PFCDH9 PFCDH8 7 6 5 4 0 3 0 2 PFCDH2 1 0 0 BMODCN PFCDH7 PFCDH6 PFCDH5 Bit position 15 Bit name PFCDH15 Function Specifies operation mode of PDH15 pin in control mode. 0: External interrupt request (INTPD15) input mode 1: PWM1 output mode 14 PFCDH14 Specifies operation mode of PDH14 pin in control mode. 0: External interrupt request (INTPD14) input mode 1: PWM0 output mode 13 PFCDH13 Specifies operation mode of PDH13 pin in control mode. 0: External interrupt request (INTPD13) input mode 1: TIUD11 input mode 12 PFCDH12 Specifies operation mode of PDH12 pin in control mode. 0: External interrupt request (INTPD12) input mode 1: TO11 output mode 11 PFCDH11 Specifies operation mode of PDH11 pin in control mode. 0: External interrupt request (INTPD11) input mode 1: Timer ENC11 external capture trigger (INTP111) input mode/TCLR11 input mode There is no register that selects a timer ENC11 external capture trigger (INTP111) input mode or TCLR11 input mode. * To use TCLR11 input mode: Mask the external capture trigger (INTP111) of timer ENC11, or use the CC111 register as a compare register. * To use external capture trigger (INTP111) of timer ENC11: Set the CLR111 and CLR110 bits of the TMC11 register to other than 00. User's Manual U16031EJ4V1UD 849 CHAPTER 14 PORT FUNCTIONS (2/3) Bit position 10 Bit name PFCDH10 Function Specifies operation mode of PDH10 pin in control mode. 0: External interrupt request (INTPD10) input mode 1: Timer ENC11 external capture trigger (INTP110) input mode/TCUD10 input mode There is no register that selects a timer ENC11 external capture trigger (INTP110) input mode or TCUD11 input mode. * To use TUCD11 input mode: Mask the external capture trigger (INTP110) of timer ENC11, or use the CC110 register as a compare register. * To use external capture trigger (INTP110) of timer ENC11: Set the T1CMD1 bit of the TUM11 register to 0. 9 PFCDH9 Specifies operation mode of PDH9 pin in control mode. 0: External interrupt request (INTPD9) input mode 1: TIUD10 input mode 8 PFCDH8 Specifies operation mode of PDH8 pin in control mode. 0: External interrupt request (INTPD8) input mode 1: TO10 output mode 7 PFCDH7 Specifies operation mode of PDH7 pin in control mode. 0: External interrupt request (INTPD7) input mode 1: Timer ENC10 external capture trigger (INTP101) input mode/TCLR10 input mode There is no register that selects a timer ENC10 external capture trigger (INTP101) input mode or TCLR10 input mode. * To use TCLR10 input mode: Mask the external capture trigger (INTP101) of timer ENC10, or use the CC101 register as a compare register. * To use external capture trigger (INTP101) of timer ENC10: Set the CLR101 and CLR100 bits of the TMC10 register to other than 00. 6 PFCDH6 Specifies operation mode of PDH6 pin in control mode. 0: External interrupt request (INTPD6) input mode 1: Timer ENC10 external capture trigger (INTP100) input mode/TCUD10 input mode There is no register that selects a timer ENC10 external capture trigger (INTP100) input mode or TCUD10 input mode. * To use TUCD10 input mode: Mask the external capture trigger (INTP100) of timer ENC10, or use the CC100 register as a compare register. * To use external capture trigger (INTP100) of timer ENC10: Set the T1CMD0 bit of the TUM10 register to 0. 5 PFCDH5 Specifies operation mode of PDH5 pin in control mode. 0: External interrupt request (INTPD5) input mode 1: TOC5 output mode 2 PFCDH2 Specifies operation mode of PDH2 pin in control mode. 0: External interrupt request (INTPD2) input mode 1: TOC4 output mode 850 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (3/3) Bit position 0 Bit name BMODCN Function Specifies the operation mode of the D16 to D31 pins in the 16-bit mode (16-bit data bus). However, changing the value of the BMODCN bit from 0 to 1 is not reflected in the LBS register. 0: The D16 to D31 pins are not used for starting in the 16-bit mode (data bus width: 16/8 bits). 1: The D16 to D31 pins are not used for starting in the 16-bit mode (data bus width: 32/16/8 bits). Caution The BMODCN bit is valid only when the 16-bit mode is specified in accordance with the status of the MODE0 and MODE1 pins. This bit is invalid if the 32-bit mode is specified. The BMODCN bit can be rewritten only once. If it is rewritten twice or more, the operation is not guaranteed. When the BMODCN bit = 1, the operation is the same as when the 32-bit mode is specified in accordance with the status of the MODE0 and MODE1 pins. User's Manual U16031EJ4V1UD 851 CHAPTER 14 PORT FUNCTIONS (3) Selecting interrupt trigger mode The valid edges of the INTPDn pin can be selected by program (n = 0 to 15). The level detection of the INTPDn pin can also be selected. External interrupt rising edge specification register DH (INTRDH) and external interrupt falling edge specification register DH (INTFDH) are used to specify the valid edge and level detection. (a) External interrupt rising edge specification register DH (INTRDH) and external interrupt falling edge specification register DH (INTFDH) These registers are used to specify the trigger mode of an external interrupt request (INTPDn) from an external pin (n = 0 to 15). The correspondence between each bit of this register and the external interrupt request controlled by that bit is as follows. * INTFDH0 and INTRDH0 bits: * INTFDH1 and INTRDH1 bits: * INTFDH2 and INTRDH2 bits: * INTFDH3 and INTRDH3 bits: * INTFDH4 and INTRDH4 bits: * INTFDH5 and INTRDH5 bits: * INTFDH6 and INTRDH6 bits: * INTFDH7 and INTRDH7 bits: * INTFDH8 and INTRDH8 bits: * INTFDH9 and INTRDH9 bits: INTPD0 INTPD1 INTPD2 INTPD3 INTPD4 INTPD5 INTPD6 INTPD7 INTPD8 INTPD9 * INTFDH10 and INTRDH10 bits: INTPD10 * INTFDH11 and INTRDH11 bits: INTPD11 * INTFDH12 and INTRDH12 bits: INTPD12 * INTFDH13 and INTRDH13 bits: INTPD13 * INTFDH14 and INTRDH14 bits: INTPD14 * INTFDH15 and INTRDH15 bits: INTPD15 The rising edge, falling edge, or both the rising and falling edges can be specified as the valid edge of the INTPDn pin, independently for each pin. INTRDH and INTFDH registers can be read or written in 16-bit units. When the higher 8 bits of the INTRDH and INTFDH registers are used as INTRDHH and INTFDHH registers, and the lower 8 bits as INTRDHL and INTFDHL registers, these registers can be read or written in 8-bit or 1-bit units. Caution Set the PMCDH register before setting the trigger mode. If the PMCDH register is set after the INTRDH and INTFDH registers have been set, an illegal interrupt may occur when the PMCDH register is set. 852 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFC36H After reset FFFFH INTRDH INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR INTR DH15 DH14 DH13 DH12 DH11 DH10 DH9 DH8 DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0 INTFDH INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF INTF DH15 DH14 DH13 DH12 DH11 DH10 DH9 DH8 DH7 DH6 DH5 DH4 DH3 DH2 DH1 DH0 FFFFFC16H 0000H Bit position 15 to 0 Bit name INTFDHn, INTRDHn (n = 0 to 15) Specify trigger mode of INTPDn pin. INTFDHn 0 0 1 1 INTRDHn 0 1 0 1 Falling edge Rising edge Function Operation Level detection (low-level detection) Both rising and falling edges Notes 1, 2 Notes 1. The level of the INTPDn pin is sampled each time the main clock (fX) is divided by four. When the low level of this pin is detected, an interrupt request is latched as the PDIFn bit (n = 0 to 15). Consequently, even when the CPU acknowledges the interrupt and the PDIFn bit of the interrupt control register (PDICn) is automatically cleared to 0, the PDIFn bit is immediately set to 1 and interrupts occur consecutively. To avoid this status, make the INTPDn pin of the external device inactive in the interrupt servicing routine, and forcibly clear the PDIFn bit to 0. 2. If a level-detected interrupt request (INTPDn) with a lower priority occurs while an interrupt is being serviced and if this level-detected interrupt request (INTPDn) that has newly occurred becomes inactive before the current interrupt has been serviced, the interrupt request of the new interrupt (INTPDn) is held pending (n = 0 to 15). To not acknowledge the interrupt request of INTPDn, clear the PDIFn bit of the interrupt control register. User's Manual U16031EJ4V1UD 853 CHAPTER 14 PORT FUNCTIONS 14.3.9 Port CS Port CS (PCS) is an 8-bit I/O port that can be set to the input or output mode in 1-bit units. 7 PCS PCS7 6 PCS6 5 PCS5 4 PCS4 3 PCS3 2 PCS2 1 PCS1 0 PCS0 Address FFFFF008H After reset Undefined Bit position 7 to 0 Bit name PCSn (n = 7 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, in the control mode, the port pins can also operate as the chip select signal outputs when memory is externally expanded and the read/write strobe signal output to an external I/O. (1) Operation in control mode Pin Name Pin No. GM PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 44 43 42 41 40 37 36 35 F1 C17 B18 D16 D17 E15 E17 E18 F16 CS0 CS1 CS2/IOWR CS3 CS4 CS5/IORD CS6 CS7 Chip select signal output Chip select signal output Chip select signal output/write strobe signal output Chip select signal output Chip select signal output Chip select signal output/read strobe signal output Chip select signal output Chip select signal output J-2 D-2 J-2 D-2 D-2 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 854 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port CS I/O mode setting is performed by the port CS mode register (PMCS), and the control mode setting is performed by the port CS mode control register (PMCCS) and the port CS function control register (PFCCS). (a) Port CS mode register (PMCS) This register can be read or written in 8-bit or 1-bit units. 7 PMCS PMCS7 6 PMCS6 5 PMCS5 4 PMCS4 3 PMCS3 2 PMCS2 1 PMCS1 0 PMCS0 Address FFFFF028H After reset FFH Bit position 7 to 0 Bit name PMCSn (n = 7 to 0) Function Specifies input/output mode for PCSn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port CS mode control register (PMCCS) This register can be read or written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 0 Address FFFFF048H After reset FFH PMCCS PMCCS7 PMCCS6 PMCCS5 PMCCS4 PMCCS3 PMCCS2 PMCCS1 PMCCS0 Bit position 7 Bit name PMCCS7 Specifies operation mode of PCS7 pin. 0: I/O port mode 1: CS7 output mode Specifies operation mode of PCS6 pin. 0: I/O port mode 1: CS6 output mode Function 6 PMCCS6 5 PMCCS5 Specifies operation mode of PCS5 pin. 0: I/O port mode 1: CS5 output mode/IORD output mode Specifies operation mode of PCS4 pin. 0: I/O port mode 1: CS4 output mode Specifies operation mode of PCS3 pin. 0: I/O port mode 1: CS3 output mode Specifies operation mode of PCS2 pin. 0: I/O port mode 1: CS2 output mode/IOWR output mode Specifies operation mode of PCS1 pin. 0: I/O port mode 1: CS1 output mode Specifies operation mode of PCS0 pin. 0: I/O port mode 1: CS0 output mode 4 PMCCS4 3 PMCCS3 2 PMCCS2 1 PMCCS1 0 PMCCS0 User's Manual U16031EJ4V1UD 855 CHAPTER 14 PORT FUNCTIONS (c) Port CS function control register (PFCCS) This register can be read or written in 8-bit or 1-bit units. The LLWR, LUWR, ULWR and UUWR signals (hereafter referred to as the xxWR signal) and LLDQM, LUDQM, ULDQM, and UUDQM signals (hereafter referred to as the xxDQM signal) are alternate-function pins (xxWR/xxDQM), and the WR signal and WE signal are alternate-function pins (WR/WE). When an access to the SRAM interface device occurs immediately after an access to the SDRAM occurs, the rise of the xxDQM (xxWR) signal or the rise (inactive timing) of the WE (WR) signal overlaps the SRAM interface device cycle, which may cause erroneous write. To prevent this, set the CSDCn bit to 1 to delay the timing at which the CSn signal falls by one clock. Caution When the port mode is specified by the port CS mode control register (PMCCS), the PFCCS setting becomes invalid. 7 PFCCS CSDC7 6 CSDC6 5 PFCCS5 4 CSDC4 0 3 Note 1 2 PFCCS2 0 1 Note 1 0 CSDC0 Address FFFFF049H After reset 00H Bit position 7, 6, 4, 0 Bit name CSDCn Notes 2, 3, 4, 5 Function Specifies chip select signal (CSn) output timing. 0: No delay function 1: Delay function When this bit is set (1), the timing at which the corresponding chip select signal (CSn) falls is delayed by one clock. The output timing of signals other than CSn is not affected. 5 PFCCS5 Specifies operation mode of PCS5 pin in control mode. 0: CS5 output mode Note 6 1: IORD output mode 2 PFCCS2 Specifies operation mode of PCS2 pin in control mode. 0: CS2 output mode Note 6 1: IOWR output mode Notes 1. 2. Be sure to clear bits 3 and 1 to 0. Be sure to set the BTn0 and BTn1 bits of the BCT0 and BCT1 registers to 00 or 01 so that the device to which erroneous write may occur is connected to the CS space to which the CSDCn bit is set to 1. 3. 4. 5. 6. Do not change the value of the CSDCn bit for the CS space where the program under execution is allocated. Be sure to insert one or more address setup waits (required number of waits + 1) in the CS space for which the CSDCn bit is set to 1 using the ASC register. The CSDCn bit can be set to 1 only in the initialization sequence. To output the IORD and IOWR signals during access to the external I/O other than by a DMA flyby transfer, the IOEN bit of the BCP register must be set. Remark n = 0, 4, 6, 7 856 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS An example of a timing chart where the CSDCn bit is set to 1 is shown below. Figure 14-25. Timing When CSDCn Bit Is Set to 1 BUSCLK (output) CSn when CSDCn bit = 0 (output) The rising timing is not changed. CSn when CSDCn bit = 1 (output) Signal output timing is delayed by 1 clock. Remark n = 0, 4, 6, 7 User's Manual U16031EJ4V1UD 857 CHAPTER 14 PORT FUNCTIONS 14.3.10 Port CT Port CT (PCT) is a 6-bit I/O port that can be set to input or output mode in 1-bit units. 7 PCT PCT7 6 0 5 PCT5 4 PCT4 3 PCT3 2 PCT2 1 PCT1 0 PCT0 Address FFFFF00AH After reset Undefined Bit position 7, 5 to 0 Bit name PCTn (n = 7, 5 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to the port function, this port outputs, in the control mode, control signals to externally expand the memory and byte enable signals when SDRAM is accessed in byte units. (1) Operation in control mode Pin Name Pin No. GM PCT0 83 F1 A3 LLWR/LLBE/LLDQM Write strobe signal output/ byte enable signal output/ output disable/write mask signal PCT1 82 D5 LUWR/LUBE/LUDQM Write strobe signal output/ byte enable signal output/ output disable/write mask signal PCT2 81 C5 ULWR/ULBE/ULDQM Write strobe signal output/ byte enable signal output/ output disable/write mask signal PCT3 80 B5 UUWR/UUBE/UUDQM Write strobe signal output/ byte enable signal output/ output disable/write mask signal PCT4 PCT5 79 78 A5 C6 RD WE/WR Read strobe signal output Write enable signal output/ write strobe signal output PCT7 77 B6 BCYST Bus cycle status signal output D-2 J-3 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 858 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port CT I/O mode setting is performed by the port CT mode register (PMCT), and the control mode setting is performed by the port CT mode control register (PMCCT) and port CT function control register (PFCCT). (a) Port CT mode register (PMCT) This register can be read or written in 8-bit or 1-bit units. 7 PMCT PMCT7 6 1 5 PMCT5 4 PMCT4 3 PMCT3 2 PMCT2 1 PMCT1 0 PMCT0 Address FFFFF02AH After reset FFH Bit position 7, 5 to 0 Bit name PMCTn (n = 7, 5 to 0) Function Specifies input/output mode for PCTn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port CT mode control register (PMCCT) This register can be read or written in 8-bit or 1-bit units. 7 PMCCT PMCCT7 6 0 5 4 3 2 1 0 Address FFFFF04AH After reset BFH PMCCT5 PMCCT4 PMCCT3 PMCCT2 PMCCT1 PMCCT0 Bit position 7 Bit name PMCCT7 Specifies operation mode of PCT7 pin. 0: I/O port mode 1: BCYST output mode Function 5 PMCCT5 Specifies operation mode of PCT5 pin. 0: I/O port mode 1: WE/WR output mode The WE output mode and WR output mode are automatically selected by accessing the memory for which each mode is targeted. 4 PMCCT4 Specifies operation mode of PCT4 pin. 0: I/O port mode 1: RD output mode 3 PMCCT3 Specifies operation mode of PCT3 pin. 0: I/O port mode 1: UUWR output mode/UUBE output mode/UUDQM output mode 2 PMCCT2 Specifies operation mode of PCT2 pin. 0: I/O port mode 1: ULWR output mode/ULBE output mode/ULDQM output mode 1 PMCCT1 Specifies operation mode of PCT1 pin. 0: I/O port mode 1: LUWR output mode/LUBE output mode/LUDQM output mode 0 PMCCT0 Specifies operation mode of PCT0 pin. 0: I/O port mode 1: LLWR output mode/LLBE output mode/LLDQM output mode User's Manual U16031EJ4V1UD 859 CHAPTER 14 PORT FUNCTIONS (c) Port CT function control register (PFCCT) This register can be read or written in 8-bit or 1-bit units. Cautions 1. When the port mode is specified by the port CT mode control register (PMCCT), the setting of this register becomes invalid. 2. The timing of the xxDQM signal differs between when the xxWR output mode/xxDQM output mode is selected and when the xxBE output mode/xxDQM output mode is selected. However, if either mode is selected, no problems occur when connecting to SDRAM. For the output timing of the xxDQM signal, refer to the timing diagrams (Figures 5-9 to 5-11) in 5.3.5 SDRAM access (xx = UU, UL, LU, LL). 7 PFCCT 0 6 0 5 0 4 0 3 2 1 0 Address FFFFF04BH After reset 00H PFCCT3 PFCCT2 PFCCT1 PFCCT0 Bit position 3 Bit name PFCCT3 Function Specifies operation mode of PCT3 pin in control mode. 0: UUWR output mode/UUDQM output mode 1: UUBE output mode/UUDQM output mode The UUWR output mode and UUDQM output mode, and the UUBE output mode and UUDQM output mode are automatically selected by accessing the memory for which each mode is targeted. 2 PFCCT2 Specifies operation mode of PCT2 pin in control mode. 0: ULWR output mode/ULDQM output mode 1: ULBE output mode/ULDQM output mode The ULWR output mode and ULDQM output mode, and the ULBE output mode and ULDQM output mode are automatically selected by accessing the memory for which each mode is targeted. 1 PFCCT1 Specifies operation mode of PCT1 pin in control mode. 0: LUWR output mode/LUDQM output mode 1: LUBE output mode/LUDQM output mode The LUWR output mode and LUDQM output mode, and the LUBE output mode and LUDQM output mode are automatically selected by accessing the memory for which each mode is targeted. 0 PFCCT0 Specifies operation mode of PCT0 pin in control mode. 0: LLWR output mode/LLDQM output mode 1: LLBE output mode/LUDQM output mode The LLWR output mode and LLDQM output mode, and the LLBE output mode and LUDQM output mode are automatically selected by accessing the memory for which each mode is targeted. 860 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.3.11 Port CM Port CM (PCM) is a 6-bit I/O port that can be set to the input or output mode in 1-bit units. 7 PCM 0 6 0 5 PCM5 4 PCM4 3 PCM3 2 PCM2 1 PCM1 0 PCM0 Address FFFFF00CH After reset Undefined Bit position 5 to 0 Bit name PCMn (n = 5 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, in the control mode, the port CM pins operate as the wait insertion signal input, bus hold control signal output, refresh request signal output from SDRAM, and A/D converter external trigger input. (1) Operation in control mode Pin Name Pin No. GM PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 34 33 32 31 30 29 F1 F17 G15 F18 G16 G17 G18 HLDAK HLDRQ REFRQ SELFREF/ADTRG WAIT - Wait insertion signal input - Bus hold acknowledge signal output Bus hold request signal input Refresh request signal output Self-refresh request signal input C-1 D-1 D-2 C-1 D-2 F-5 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) User's Manual U16031EJ4V1UD 861 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port CM I/O mode setting is performed by the port CM mode register (PMCM), and the control mode setting is performed by the port CM mode control register (PMCCM) and the port CM function control register (PFCCM). (a) Port CM mode register (PMCM) This register can be read or written in 8-bit or 1-bit units. 7 PMCM 1 6 1 5 PMCM5 4 PMCM4 3 PMCM3 2 PMCM2 1 PMCM1 0 PMCM0 Address FFFFF02CH After reset FFH Bit position 5 to 0 Bit name PMCMn (n = 5 to 0) Function Specifies input/output mode for PCMn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port CM mode control register (PMCCM) This register can be read or written in 8-bit or 1-bit units. Be sure to clear bit 1 to 0. If it is set to 1, the operation is not guaranteed. 7 PMCCM 0 6 0 5 4 3 2 1 0 0 PMCCM0 Address FFFFF04CH After reset 3DH PMCCM5 PMCCM4 PMCCM3 PMCCM2 Bit position 5 Bit name PMCCM5 Specifies operation mode of PCM5 pin. Function 0: I/O port mode 1: SELFREF input mode/A/D converter external trigger (ADTRG) input mode 4 PMCCM4 Specifies operation mode of PCM4 pin. 0: I/O port mode 1: REFRQ output mode 3 PMCCM3 Specifies operation mode of PCM3 pin. 0: I/O port mode 1: HLDRQ input mode 2 PMCCM2 Specifies operation mode of PCM2 pin. 0: I/O port mode 1: HLDAK output mode 0 PMCCM0 Specifies operation mode of PCM0 pin. 0: I/O port mode 1: WAIT input mode 862 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (c) Port CM function control register (PFCCM) This register can be read or written in 8-bit or 1-bit units. Caution When the port mode is specified by the port CM mode control register (PMCCM), the PFCCM setting becomes invalid. 7 PFCCM 0 6 0 5 PFCCM5 4 0 3 0 2 0 1 0 0 0 Address FFFFF04DH After reset 00H Bit position 5 Bit name PFCCM5 Function Specifies operation mode of PCM5 pin in control mode. 0: SELFREF input mode 1: A/D converter external trigger (ADTRG) input mode User's Manual U16031EJ4V1UD 863 CHAPTER 14 PORT FUNCTIONS 14.3.12 Port CD Port CD (PCD) is a 4-bit I/O port that can be set to the input or output mode in 1-bit units. 7 PCD 0 6 0 5 0 4 0 3 PCD3 2 PCD2 1 PCD1 0 PCD0 Address FFFFF00EH After reset Undefined Bit position 3 to 0 Bit name PCDn (n = 3 to 0) I/O port Function Remark For reading/writing of the I/O port, see 14.5 Operation of Port Function. In addition to their function as port pins, the port CD pins operate as the clock enable signal output, bus clock output, column address strobe signal output, and row address strobe signal output in the control mode. (1) Operation in control mode Pin Name Pin No. GM PCD0 PCD1 PCD2 PCD3 91 88 87 86 F1 D3 B2 B3 C3 SDCKE BUSCLK SDCAS SDRAS Clock enable signal output Bus clock output Column address strobe signal output Row address strobe signal output D-2 D-1 D-2 Alternate Function Remark Block Type Remark GM: 176-pin plastic LQFP (fine pitch) (24 x 24) F1: 240-pin plastic FBGA (16 x 16) 864 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port CD I/O mode setting is performed by the port CD mode register (PMCD), and the control mode setting is performed by the port CD mode control register (PMCCD). (a) Port CD mode register (PMCD) This register can be read or written in 8-bit or 1-bit units. 7 PMCD 1 6 1 5 1 4 1 3 PMCD3 2 PMCD2 1 PMCD1 0 PMCD0 Address FFFFF02EH After reset FFH Bit position 3 to 0 Bit name PMCDn (n = 3 to 0) Function Specifies input/output mode for PCDn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port CD mode control register (PMCCD) This register can be read or written in 8-bit or 1-bit units. 7 PMCCD 0 6 0 5 0 4 0 3 2 1 0 Address FFFFF04EH After reset 0FH PMCCD3 PMCCD2 PMCCD1 PMCCD0 Bit position 3 Bit name PMCCD3 Specifies operation mode of PCD3 pin. 0: I/O port mode 1: SDRAS output mode Function 2 PMCCD2 Specifies operation mode of PCD2 pin. 0: I/O port mode 1: SDCAS output mode 1 PMCCD1 Specifies operation mode of PCD1 pin. 0: I/O port mode 1: BUSCLK output mode 0 PMCCD0 Specifies operation mode of PCD0 pin. 0: I/O port mode 1: SDCKE output mode User's Manual U16031EJ4V1UD 865 CHAPTER 14 PORT FUNCTIONS 14.4 Configuration of RESET, A2 to A15, and D0 to D15 Pins The RESET, A2 to A15, and D0 to D15 pins are not alternative function pins. Their configuration is as follows. (1) Configuration of RESET, A2 to A15, and D0 to D15 pins Pin Function RESET A2 to A15 D0 to D15 Schmitt buffer Output buffer off control Output buffer off control and DIR control Remark N-1 N-2 N-3 Block Type (2) Block diagram of RESET, A2 to A15, and D0 to D15 pins Figure 14-26. Block Diagram of Type N-1 Input signal RESET Figure 14-27. Block Diagram of Type N-2 Output buffer off signalNote Internal bus An Note Signal that becomes active in the IDLE and software STOP modes, and by bus hold and reset Remark n = 2 to 15 866 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS Figure 14-28. Block Diagram of Type N-3 Output buffer off signalNote Dn Internal bus Input buffer off signal Note Signal that becomes active in the IDLE and software STOP modes, and by bus hold and reset Remark n = 0 to 15 User's Manual U16031EJ4V1UD 867 CHAPTER 14 PORT FUNCTIONS 14.5 Operation of Port Function The operation of a port differs depending on whether it is set in the input or output mode, as follows. 14.5.1 Writing to I/O port (1) In output mode A value can be written to the output latch (Pn) by writing it to the port n register (Pn). The contents of the output latch are output from the pin. Once data is written to the output latch, it is held until new data is written to the output latch. (2) In input mode A value can be written to the output latch (Pn) by writing it to the port n register (Pn). However, the status of the pin does not change because the output buffer is off. Once data is written to the output latch, it is held until new data is written to the output latch. Caution A bit manipulation instruction (CLR1, SET1, NOT1) manipulates 1 bit but accesses a port in 8-bit units. If this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, are overwritten to the current input pin status and become undefined. 14.5.2 Reading from I/O port (1) In output mode The contents of the output latch (Pn) can be read by reading the port n register (Pn). The contents of the output latch do not change. (2) In input mode The status of the pin can be read by reading the port n register (Pn). The contents of the output latch (Pn) do not change. 14.5.3 Output status of alternate function in control mode The status of a port pin is not dependent upon the setting of the PMCn register and can be read by setting the port n mode register (PMn) to the input mode. If the PMn register is set to the output mode, the value of the port n register (Pn) can be read in the port mode, and the output status of the alternate function can be read in the control mode. 868 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.6 Noise Eliminator 14.6.1 Interrupt input pin The following timing controller used to secure the noise elimination time is provided for the NMI and port pins that operate in the control mode when the valid edge is input. Input signals that change within the noise elimination time are not internally acknowledged. Table 14-1. Noise Elimination Time of Interrupt Input Pins Pin NMI INTP10 INTP11 INTP21 INTP22 INTP23 INTP24 INTP25 INTP50 INTP51 INTP52 INTP65 INTP66 INTP67 INTPL0 INTPL1 INTPD0 INTPD1 INTPD2 INTPD3 INTPD4 INTPD5 INTPD6 INTPD7 INTPD8 INTPD9 INTPD10 INTPD11 INTPD12 INTPD13 INTPD14 INTPD15 Noise Elimination Time Analog delay (80 ns typ.) Cautions 1. The above non-maskable and maskable interrupt pins are used to release the standby mode. A timing circuit that controls the clock is not employed because the internal system clock (fCLK) is stopped in the standby mode. 2. The noise eliminator is valid only in the control mode. User's Manual U16031EJ4V1UD 869 CHAPTER 14 PORT FUNCTIONS 14.6.2 A/D converter input pin The following timing controller used to secure the noise elimination time is provided for the ADTRG pin. An input signal that changes within the noise elimination time is not internally acknowledged. Table 14-2. Noise Elimination Time of A/D Converter Input Pin Pin PCM5/ADTRG/SELFREF Noise Elimination Time Analog delay (80 ns typ.) Caution The noise eliminator is valid only in the control mode. 14.6.3 Timer C and timer ENC1 input pins The following noise filter that operates via clock sampling is provided for the pins of timers C and ENC1 that operate when the valid edge is input. Input signals that change within the noise elimination time are not internally acknowledged. Table 14-3. Noise Elimination Time of Timer C and Timer ENC1 Input Pins Pin INTPC00/TIC0 INTPC01 INTPC10/TIC1 INTPC11 INTPC20/TIC2 INTPC21 INTPC30/TIC3 INTPC31 INTP100/TCUD10 INTP101/TCLR10 TIUD10 INTP110/TCUD11 INTP111/TCLR11 TIUD11 Noise Elimination Time Selected from 0, 2, 3, or 5 clocks Cautions 1. The noise filter of the above pins cannot acknowledge an input signal when the CPU clock is stopped because it uses clock sampling. 2. The noise eliminator is valid only in the control mode. 870 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (1) Noise elimination width setting registers C0 to C3 (NCWC0 to NCWC3) These registers are used to set the noise elimination width of the digital noise filter of the timer C input pins. These registers can be read or written in 8-bit units. Be sure to clear bits 7 to 2 to 0. If they are set to 1, the operation is not guaranteed. Do not overwrite this register during a count operation. 7 NCWC0 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFF610H After reset 02H NCCC01 NCCC00 NCWC1 0 0 0 0 0 0 NCCC11 NCCC10 FFFFF630H 02H NCWC2 0 0 0 0 0 0 NCCC21 NCCC20 FFFFF650H 02H NCWC3 0 0 0 0 0 0 NCCC31 NCCC30 FFFFF670H 02H Bit position 1, 0 Bit name NCCCn1, NCCCn0 Function Specify number of clocks from which noise is to be eliminated. NCCCn1 0 0 1 1 NCCCn0 0 1 0 1 Number of clocks from which noise is to be eliminated 0 (through input) 2 3 5 Remark 1 clock = fX/4 fX: Main clock Remark n = 0 to 3 User's Manual U16031EJ4V1UD 871 CHAPTER 14 PORT FUNCTIONS (2) Noise elimination width setting registers 10, 11 (NCW10, NCW11) These registers are used to set the noise elimination width of the digital noise filter of the timer ENC1 input pins. These registers can be read or written in 8-bit units. Cautions 1. Whether the signal is input through or inverted can be specified for each of the INTP1n0/TCUD1n and TIUD1n pins. The noise elimination width set by the NCFn, NCC1n, and NCC0n bits is for each timer and cannot be changed for each pin. 2. The setting of the SRTCn bit is valid even when the INTP1n0/TCUD1n pin is used as a capture trigger (INTP1n0). 7 NCW10 0 6 0 5 SRTC0 4 SRTI0 3 0 2 NCF0 1 NCC10 0 NCC00 Address FFFFF5C0H After reset 02H NCW11 0 0 SRTC1 SRTI1 0 NCF1 NCC11 NCC01 FFFFF5F0H 02H Bit position 5 Bit name SRTCn Function Specifies the input mode of the INTP1n0/TCUD1n pin. 0: Through input 1: Inverted This bit specifies whether the signal input from the INTP1n0/TCUD1n pin is input through to TMENC1n, or inverted. 4 SRTIn Specifies the input mode of the TIUD1n pin. 0: Through input 1: Inverted This bit specifies whether the signal input from the TIUD1n pin is input through to TMENC1n, or inverted. 2 NCFn Specifies the clock frequency for noise elimination. 0: fX/4 1: fX/32 This bit selects a clock source for the noise filter. 1, 0 NCC1n, NCC0n Specify the number of clocks from which noise is to be eliminated. NCC1n 0 0 1 1 Note 1 NCC0n 0 1 0 1 Note 1 Number of clocks from which noise is to be eliminated 0 (through input) 2 3 5 Note 2 Notes 1. Do not overwrite this bit during a count operation. 2. Clear the NCFn bit to 0 to input the signal through. These bits are used to select the number of clocks from which noise is to be eliminated. Remark n = 0, 1 872 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS (a) Relationship between NCW1n register set value and noise elimination width Table 14-4. Relationship Between NCW1n Register Set Value and Noise Elimination Width NCW1n Register NCFn Bit 0 0 0 0 1 1 1 NCC1n Bit 0 0 1 1 0 1 1 NCC0n Bit 0 1 0 1 1 0 1 Noise Elimination Width (ns) fX = 150 MHz 0 53.3 to 80.0 80.0 to 106.7 133.3 to 160.0 426.7 to 640.0 640.0 to 853.3 fX = 133 MHz 0 60.2 to 90.2 90.2 to 120.3 150.4 to 180.5 481.2 to 721.8 721.8 to 962.9 fX = 100 MHz 0 80 to 120 120 to 160 200 to 240 640 to 960 960 to 1,280 1,600 to 1,920 Through (1/(fX/4)) x 2 (1/(fX/4)) x 3 (1/(fX/4)) x 5 (1/(fX/32)) x 2 (1/(fX/32)) x 3 (1/(fX/32)) x 5 Remark 1,066.7 to 1,280.0 1,203.0 to 1,443.6 Remarks 1. n = 0, 1 2. fX: Main clock User's Manual U16031EJ4V1UD 873 CHAPTER 14 PORT FUNCTIONS 14.7 Cautions 14.7.1 Cautions on setting port pins (1) Procedure to change mode from port mode to control mode Change the mode of a port pin that functions as an output or I/O pin in the control mode to the control mode using the following procedure. <1> Set the inactive level of the signal to be output in the control mode to the corresponding bit of port n (n = 1, 2, 5 to 7, AH, AL, CD, CM, CS, CT, DH). <2> Select the control mode by using the port n mode control register (PMCn). If <1> is not performed, the contents of port n may be momentarily output when the mode is changed from the port mode to the control mode. 874 User's Manual U16031EJ4V1UD CHAPTER 14 PORT FUNCTIONS 14.7.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. PCS0 Low-level output PCS1 to PCS7 Pin status: High level Port CS latch 0 0 0 0 0 0 0 0 Bit manipulation instruction (set1 0, PCS[r0]) is executed for PCS0 bit. PCS0 High-level output PCS1 to PCS7 Pin status: High level Port CS latch 1 1 1 1 1 1 1 1 Bit manipulation instruction for PCS0 bit <1> PCS register is read in 8-bit units. * In the case of PCS0, an output port, the value of the port latch (0) is read. * In the case of PCS1 to PCS7, input ports, the pin status (1) is read. <2> Set PCS0 bit to 1. <3> Write the results of <2> to the output latch of PCS register in 8-bit units. User's Manual U16031EJ4V1UD 875 CHAPTER 15 RESET FUNCTIONS 15.1 Overview * Reset function by RESET input * Forced reset function by DCU (See CHAPTER 16 DEBUG FUNCTION (DCU).) * Low level is input to the RESET pin for 100 s min. If an oscillation stabilization time of 100 s or longer is necessary, secure the low level for as long as the necessary oscillation stabilization time. * Reset generator (RG) eliminates noise from the RESET pin. 15.2 Configuration V850E/ME2 CPU core DCU Selector Peripheral reset RESET RG SSCG Remark SSCG: Spread spectrum frequency synthesizer phase locked loop (see CHAPTER 8 GENERATION FUNCTION) DCU: Debug Control Unit (see CHAPTER 16 DEBUG FUNCTION (DCU)) RG: Reset Generator CLOCK During a system reset, most pins (all excluding the BUSCLK, RESET, X2, EVDD, EVSS, IVDD, IVSS, PLLVDD, PLLVSS, OSCVDD, OSCVSS, UVDD, AVDD, AVREFP, AVREFM, and AVSS pins) enter the high-impedance state. Therefore, a pull-up (or pull-down) resistor must be connected to each pin of the address bus, data bus, and external bus control signals. If no resistor is connected, external memory may be destroyed when these pins enter the high-impedance state. For the same reason, the output signals of the on-chip peripheral I/O functions and other output ports should be handled in the same manner. 876 User's Manual U16031EJ4V1UD CHAPTER 15 RESET FUNCTIONS 15.3 Operation When a low-level signal is input to the RESET pin, a system reset is effected and each on-chip hardware is initialized. When the RESET pin level changes from low to high, the reset state is released and the CPU starts program execution using OSC output clock (FX). Register contents must be initialized as required in the program. When the reset signal is cleared, the oscillation stabilization time is not inserted. When the RESET signal is to be input (reset input on power application or reset input when the software STOP mode is released) while the clock oscillator is stopped, therefore, a low-level width longer than the oscillation stabilization time (100 s min.) must be secured at the RESET pin. When the RESET signal is to be input (reset input when the IDLE mode is released) while the clock oscillator is not stopped, a low level of 100 s min. must be secured at the RESET pin. Table 15-1. Hardware Status After Reset Hardware OSC Clock generator During Reset Period Oscillation/supply continues * Outputs OSC clock (FX) * Output is not guaranteed before oscillation stabilization time. CPU Internal instruction RAM, internal data RAM Debug function On-chip peripheral I/O registers On-chip peripheral functions other than above Pin function See 2.2 Pin Status. Stops operating Initialized to specific status Stops operating Can start operating Operable Stops operating Undefined * Outputs OSC clock (FX) * Operable at fX = FX x 8 by controlling the CKS register Starts operating After Reset Is Cleared User's Manual U16031EJ4V1UD 877 CHAPTER 15 RESET FUNCTIONS The reset operation when the RESET pin is input is illustrated below. Figure 15-1. Reset Operation with RESET Pin Input (1/2) (a) When IDLE mode is released Power supply voltage OSC output clock (FX) H Internal system clock (fCLK) Initialized to operation at fX = FX (OSC output) 100 s min. secured RESET (input) Analog delay (eliminated as noise) Internal system reset Analog delay 5 system clocks min. PLL lockup time (2 ms min.) Analog delay (eliminated as noise) Analog delay Operation at fX = FX x 8 (SSCG output) SSCG output stabilized (LOCK = 0) CPU operation starts. LOCK = 0 CKSSEL = 1 Caution Remark Secure the SSCG initialization time (100 s) by the low-level width of the RESET signal. LOCK: Bit 1 of LOCKR register CKSSEL: Bit 1 of CKS register 878 User's Manual U16031EJ4V1UD CHAPTER 15 RESET FUNCTIONS Figure 15-1. Reset Operation with RESET Pin Input (2/2) (b) When software STOP mode is released Power supply voltage H OSC output clock (FX) Internal system clock (fCLK) Initialized to operation at fX = FX (OSC output) Oscillation stabilization time (100 s min.) secured RESET (input) Analog delay (eliminated as noise) Internal system reset Analog delay 5 system clocks min. PLL lockup time (2 ms min.) Operation at fX = FX x 8 (SSCG output) SSCG output stabilized (LOCK = 0) Analog delay (elimintaed as noise) Analog delay CPU operation starts. LOCK = 0 CKSSEL = 1 Caution Secure the oscillation stabilization time and SSCG initialization time (100 s) by the low-level width of the RESET signal. Remark LOCK: Bit 1 of LOCKR register CKSSEL: Bit 1 of CKS register User's Manual U16031EJ4V1UD 879 CHAPTER 15 RESET FUNCTIONS The power-on reset operation is illustrated below. Figure 15-2. Power-on Reset Operation Power supply voltage OSC output clock (FX) Internal system clock (fCLK) Initialized to operation at fX = FX (OSC output) Oscillation stabilization time (100 s min.) secured RESET (input) Operation at fX = FX x 8 (SSCG output) SSCG output stabilized (LOCK = 0) Analog delay (eliminated as noise) Internal system reset Analog delay 5 system clocks min. PLL lockup time (2 ms min.) CPU LOCK = 0 operation starts. CKSSEL = 1 Cautions 1. Secure the oscillation stabilization time and SSCG initialization time (100 s) by the lowlevel width of the RESET signal. 2. Supply power in the order of IVDD (internal power supply) and EVDD (external power supply). Remark LOCK: Bit 1 of LOCKR register CKSSEL: Bit 1 of CKS register 880 User's Manual U16031EJ4V1UD CHAPTER 15 RESET FUNCTIONS The BUSCLK operation at power-on reset is illustrated below. Figure 15-3. BUSCLK Operation at Power-on Reset Power supply voltage OSC output clock (FX) OSC output insufficient Internal system clock (fCLK) OSC output stabilized fX = FX (OSC output) fX = FX x 8 (SSCG output) SSCG output stabilized (LOCK = 0) RESET (input) BUSCLKNote PLL lockup time (2 ms min.) <1> <2> <3> <4> <5> <6> Remarks 1. <1>: Power on <2>: OSC oscillation stabilization <3>: RESET cleared (counting of PLL lockup time starts) <4>: PLL lock status (LOCK bit of LOCKR register = 0) <5>: BUSCLK = fCLK/2 (CKM1 and CKM0 bits of BMC register = 01) <6>: Set to fX = FX x 8 (CKSSEL bit of CKS register = 1) 2. The above operation is when BUSCLK operates on 1/2 the cycle of the internal system clock (fCLK). User's Manual U16031EJ4V1UD 881 CHAPTER 15 RESET FUNCTIONS 15.4 Initialization Initialize the contents of each register as necessary while programming. The initial values of the CPU, internal data RAM, internal instruction RAM, and on-chip peripheral I/O after a reset are shown below. Table 15-2. Initial Value of CPU, Internal Data RAM, Internal Instruction RAM, and On-Chip Peripheral I/O After Reset (1/6) Internal Hardware CPU Program registers Register Name General-purpose register (r0) General-purpose register (r1 to r31) Program counter (PC) System registers Status saving registers during interrupt (EIPC, EIPSW) Status saving registers during NMI (FEPC, FEPSW) Interrupt source register (ECR) Program status word (PSW) Status saving registers during CALLT execution (CTPC, CTPSW) Status saving registers during exception/debug trap (DBPC, DBPSW) CALLT base pointer (CTBP) Internal instruction RAM, internal data RAM On-chip peripheral I/O Bus control functions - Chip area select control register n (CSCn) (n = 0, 1) Bus cycle type configuration register n (BCTn) (n = 0, 1) Local bus sizing control register (LBS) Endian configuration register (BEC) Line buffer control register n (LBCn) (n = 0, 1) Write access synchronization control register (WAS) Bus mode control register (BMC) Data wait control register n (DWCn) (n = 0, 1) Address setup wait control register (ASC) Bus cycle period control register (BCP) DMA flyby transfer wait control register (FWC) Bus cycle control register (BCC) DMA flyby transfer idle control register (FIC) Cache configuration register (BHC) Instruction cache control register (ICC) Instruction cache control register L (ICCL) Instruction cache control register H (ICCH) Instruction cache data configuration register (ICD) Internal instruction RAM mode register (IRAMM) System wait control register (VSWC) Memory control functions Page ROM configuration register (PRC) SDRAM configuration register n (SCRn) (n = 1, 3, 4, 6) SDRAM refresh control register n (RFSn) (n = 1, 3, 4, 6) Initial Value After Reset 00000000H Undefined 00100000H Undefined Undefined 00000000H 00000020H Undefined Undefined Undefined Undefined 2C11H 8888H 5555H/AAAAH 0000H 0000H Undefined 00H 7777H FFFFH 00H 7777H FFFFH 3333H 0000H 0003H 03H Note 2 Note 2 Note 1 00H Undefined 03H 77H 7000H 30C0H 0000H Notes 1. For details, see 4.5.2 (1) Local bus sizing control register (LBS). 2. For details, see 4.9.4 (1) Instruction cache control register (ICC). 882 User's Manual U16031EJ4V1UD CHAPTER 15 RESET FUNCTIONS Table 15-2. Initial Value of CPU, Internal Data RAM, Internal Instruction RAM, and On-Chip Peripheral I/O After Reset (2/6) Internal Hardware On-chip peripheral I/O DMA functions Register Name DMA source address register nH (DSAnH) (n = 0 to 3) DMA source address register nL (DSAnL) (n = 0 to 3) DMA destination address register nH (DDAnH) (n = 0 to 3) DMA destination address register nL (DDAnL) (n = 0 to 3) DMA transfer count register n (DBCn) (n = 0 to 3) DMA addressing control register n (DADCn) (n = 0 to 3) DMA channel control register n (DCHCn) (n = 0 to 3) DMA terminal count output control register (DTOC) DMA trigger factor register n (DTFRn) (n = 0 to 3) DMA interface control register (DIFC) Interrupt/exception control functions Interrupt control registers (P1IC0, P1CI1, P2IC1 to P2IC5, P5IC0 to P5IC2, P6IC5 to P6IC7, PDIC0 to PDIC15, PLIC0, PLIC1, OVCIC0 to OVCIC5, CCC0IC0, CCC0IC1, CCC1IC0, CCC1IC1, CCC2IC0, CCC2IC1, CCC3IC0, CCC3IC1, CCC4IC0, CCC4IC1, CCC5IC0, CCC5IC1, CMDIC0 to CMDIC3, CC10IC0, CC10IC1, CC11IC0, CC11IC1, CM10IC0, CM10IC1, CM11IC0, CM11IC1, OV1IC0, OV1IC1, UD1IC0, UD1IC1, DMAIC0 to DMAIC3, CSI3IC0, CSI3IC1, COVF3IC0, COVF3IC1, UREIC0, UREIC1, URIC0, URIC1, UTIC0, UTIC1, UIFIC0, UIFIC1, UTOIC0, UTOIC1, ADIC, US0BIC to US2BIC, USP2IC, USP4IC, RSUMIC) Interrupt mask register n (IMRn) (n = 0 to 5) Interrupt mask register nL (IMRnL) (n = 0 to 5) Interrupt mask register nH (IMRnH) (n = 0 to 5) NMI reset status register (NRS) In-service priority register (ISPR) External interrupt falling edge specification register n (INTFn) (n = 1, 2, 5, 6, AL) External interrupt falling edge specification register DH (INTFDH) External interrupt falling edge specification register DHL (INTFDHL) External interrupt falling edge specification register DHH (INTFDHH) External interrupt rising edge specification register n (INTRn) (n = 1, AL) External interrupt rising edge specification register 2 (INTR2) External interrupt rising edge specification register 5 (INTR5) External interrupt rising edge specification register 6 (INTR6) External interrupt rising edge specification register DH (INTRDH) External interrupt rising edge specification register DHL (INTRDHL) External interrupt rising edge specification register DHH (INTRDHH) Valid edge select register Cn (SESCn) (n = 0 to 3) Valid edge select register 1n (SESA1n) (n = 0, 1) Initial Value After Reset Undefined Undefined Undefined Undefined Undefined 0000H 00H 01H 00H 00H 47H FFFFH FFH FFH 00H 00H 00H 0000H 00H 00H 03H 3FH 07H E0H FFFFH FFH FFH 00H 00H User's Manual U16031EJ4V1UD 883 CHAPTER 15 RESET FUNCTIONS Table 15-2. Initial Value of CPU, Internal Data RAM, Internal Instruction RAM, and On-Chip Peripheral I/O After Reset (3/6) Internal Hardware On-chip peripheral I/O Clock generation functions Register Name Clock control register (CKC) Clock source select register (CKS) SSCG control register (SSCGC) USB clock control register (UCKC) Lock register (LOCKR) Oscillation stabilization time select register (OSTS) Power-save mode register (PSMR) Power-save control register (PSC) System control Timer/counter functions (timer C) Command register (PRCMD) Timer Cn (TMCn) (n = 0 to 5) Capture/compare registers Cn0, Cn1 (CCCn0, CCCn1) (n = 0 to 5) Timer mode control register Cn0 (TMCCn0) (n = 0 to 5) Timer mode control register Cn1 (TMCCn1) (n = 0 to 5) Valid edge select register Cn (SESCn) (n = 0 to 3) Noise elimination width setting register Cn (NCWCn) (n = 0 to 3) Timer/counter functions (timer D) Timer Dn (TMDn) (n = 0 to 3) Compare register Dn (CMDn) (n = 0 to 3) Timer mode control register Dn (n = 0 to 3) Timer/counter functions (timer ENC1) Timer ENC1n (TMENC1n) (n = 0, 1) Compare register 1n (CM1n) (n = 00, 01, 10, 11) Capture/compare register 1n (CC1n) (n = 00, 01, 10, 11) Timer unit mode register 1n (TUM1n) (n = 0, 1) Timer control register 1n (TMC1n) (n = 0, 1) Capture/compare control register 1n (CCR1n) (n = 0, 1) Valid edge select register 1n (SESA1n) (n = 0, 1) Prescaler mode register 1n (PRM1n) (n = 0, 1) Status register 1n (STATUS1n) (n = 0, 1) Noise elimination width setting register 1n (NCW1n) (n = 0, 1) Serial interface functions (USBF) UF0 EP0NAK register (UF0E0N) UF0 EP0NAKALL register (UF0E0NA) UF0 EPNAK register (UF0EN) UF0 EPNAK mask register (UF0ENM) UF0 SNDSIE register (UF0SDS) UF0 CLR request register (UF0CLR) UF0 SET request register (UF0SET) UF0 EP status n register (UF0EPSn) (n = 0 to 2) UF0 INT status n register (UF0ISn) (n = 0 to 4) UF0 INT mask n register (UF0IMn) (n = 0 to 4) UF0 INT clear n register (UF0ICn) (n = 0 to 4) UF0 INT & DMARQ register (UF0IDR) UF0 DMA status n register (UF0DMSn) (n = 0, 1) UF0 FIFO clear n register (UF0FICn) (n = 0, 1) Initial Value After Reset 03H 00H See 8.3.3 00H 01H 04H 00H 00H Undefined 0000H 0000H 00H 20H 00H 02H 0000H 0000H 00H 0000H 0000H 0000H 00H 00H 00H 00H 07H 00H 02H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 884 User's Manual U16031EJ4V1UD CHAPTER 15 RESET FUNCTIONS Table 15-2. Initial Value of CPU, Internal Data RAM, Internal Instruction RAM, and On-Chip Peripheral I/O After Reset (4/6) Internal Hardware On-chip peripheral I/O Serial interface functions (USBF) Register Name UF0 data end register (UF0DEND) UF0 GPR register (UF0GPR) UF0 mode control register (UF0MODC) UF0 mode status register (UF0MODS) UF0 active interface number register (UF0AIFN) UF0 active alternative setting register (UF0AAS) UF0 alternative setting status register (UF0ASS) UF0 endpoint n interface mapping register (UF0EnIM) (n = 1 to 4, 7, 8) UF0 EP0 read register (UF0E0R) UF0 EP0 length register (UF0E0L) UF0 EP0 setup register (UF0E0ST) UF0 EP0 write register (UF0E0W) UF0 bulk out n register (UF0BOn) (n = 1, 2) UF0 bulk out n length register (UF0BO1L) (n = 1, 2) UF0 bulk in n register (UF0BIn) (n = 1, 2) UF0 interrupt n register (UF0INTn) (n = 1, 2) UF0 device status register L (UF0DSTL) UF0 EPn status register L (UF0EnSL) (n = 0 to 4, 7, 8) UF0 address register (UF0ADRS) UF0 configuration register (UF0CNF) UF0 interface n register (UF0IFn) (n = 0 to 4) UF0 descriptor length register (UF0DSCL) UF0 device descriptor register n (UF0DDn) (n = 0 to 17) UF0 configuration/interface/endpoint descriptor register n (UF0CIEn) (n = 0 to 255) USB function 0 DMA channel select register (UF0CS) USB function 0 buffer control register (UF0BC) Serial interface functions (UARTB) UARTBn control register 0 (UBnCTL0) (n = 0, 1) UARTBn control register 2 (UBnCTL2) (n = 0, 1) UARTBn status register (UBnSTR) (n = 0, 1) UARTBn transmit data register (UBnTX) (n = 0, 1) UARTBn receive data register AP (UBnRXAP) (n = 0, 1) UARTBn receive data register (UBnRX) (n = 0, 1) UARTBn FIFO control register 0 (UBnFIC0) (n = 0, 1) UARTBn FIFO control register 1 (UBnFIC1) (n = 0, 1) UARTBn FIFO control register 2 (UBnFIC2) (n = 0, 1) UARTBn FIFO control register 2L (UBnFIC2L) (n = 0, 1) UARTBn FIFO control register 2H (UBnFIC2H) (n = 0, 1) UARTBn FIFO status register 0 (UBnFIS0) (n = 0, 1) UARTBn FIFO status register 1 (UBnFIS1) (n = 0, 1) Initial Value After Reset 00H 00H 00H 00H 00H 00H 00H 00H Undefined 00H 00H Undefined Undefined 00H Undefined Undefined 00H 00H 00H 00H 00H 00H 00H Undefined 0000H 00H 10H FFFFH 00H FFH 00FFH FFH 00H 00H 0000H 00H 00H 00H 10H User's Manual U16031EJ4V1UD 885 CHAPTER 15 RESET FUNCTIONS Table 15-2. Initial Value of CPU, Internal Data RAM, Internal Instruction RAM, and On-Chip Peripheral I/O After Reset (5/6) Internal Hardware On-chip peripheral I/O Serial interface functions (CSI3) Register Name Clocked serial interface mode register 3n (CSIM3n) (n = 0, 1) Clocked serial interface clock select register 3n (CSIC3n) (n = 0, 1) Receive data buffer register 3n (SIRB3n) (n = 0, 1) Receive data buffer register 3nL (SIRB3nL) (n = 0, 1) Receive data buffer register 3nH (SIRB3nH) (n = 0, 1) Transmit data CSI buffer register 3n (SFDB3n) Transmit data CSI buffer register 3nL (SFDB3nL) Transmit data CSI buffer register 3nH (SFDB3nH) CSIBUF status register 3n (SFA3n) (n = 0, 1) Transfer data length select register 3n (CSIL3n) (n = 0, 1) Transfer data number specification register 3n (SFN3n) (n = 0, 1) A/D converter A/D converter mode register n (ADMn) (n = 0 to 2) ADC trigger select register (ADTS) A/D conversion result register n (ADCRn) (10 bits) (n = 0 to 7) A/D conversion result register nH (ADCRnH) (8 bits) (n = 0 to 7) PWM PWM control register n (PWMCn) (n = 0, 1) PWM modulo register n (PWMn) (n = 0, 1) PWM modulo register Ln (PWMLn) (n = 0, 1) PWM modulo register Hn (PWMHn) (n = 0, 1) Port functions Ports (P1, P2, P5 to P7, PCS, PCT, PCM, PCD) Port (PAL) Port (PALL) Port (PALH) Port (PAH) Port (PAHL) Port (PAHH) Port (PDH) Port (PDHL) Port (PDHH) Mode register (PM1, PM2, PM5 to PM7, PMCS, PMCT, PMCM, PMCD) Mode register (PMAL) Mode register (PMALL) Mode register (PMALH) Mode register (PMAH) Mode register (PMAHL) Mode register (PMAHH) Mode register (PMDH) Mode register (PMDHL) Mode register (PMDHH) Mode control register (PMC1, PMC5 to PMC7) Mode control register (PMC2) Mode control register (PMCCS) Initial Value After Reset 00H 07H 0000H 00H 00H 0000H 00H 00H 20H 00H 00H 00H 00H Undefined Undefined 08H 0000H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFH FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH 00H 01H FFH 886 User's Manual U16031EJ4V1UD CHAPTER 15 RESET FUNCTIONS Table 15-2. Initial Value of CPU, Internal Data RAM, Internal Instruction RAM, and On-Chip Peripheral I/O After Reset (6/6) Internal Hardware On-chip peripheral I/O Port functions Register Name Mode control register (PMCCT) Mode control register (PMCCM) Mode control register (PMCCD) Mode control register (PMCAL) Mode control register (PMCALL) Mode control register (PMCALH) Mode control register (PMCAH) Mode control register (PMCAHL) Mode control register (PMCAHH) Mode control register (PMCDH) Mode control register (PMCDHL) Mode control register (PMCDHH) Function control registers (PFC1, PFC2, PFC5 to PFC7, PFCCS, PFCCT, PFCCM) Function control register L (PFCALL) Function control register (PFCDH) Function control register (PFCDHL) Function control register (PFCDHH) External interrupt falling edge specification register n (INTFn) (n = 1, 2, 5, 6, AL) External interrupt falling edge specification register DH (INTFDH) External interrupt falling edge specification register DHL (INTFDHL) External interrupt falling edge specification register DHH (INTFDHH) External interrupt rising edge specification register n (INTRn) (n = 1, AL) External interrupt rising edge specification register 2 (INTR2) External interrupt rising edge specification register 5 (INTR5) External interrupt rising edge specification register 6 (INTR6) External interrupt rising edge specification register DH (INTRDH) External interrupt rising edge specification register DHL (INTRDHL) External interrupt rising edge specification register DHH (INTRDHH) Noise elimination width setting register Cn (NCWCn) (n = 0 to 3) Noise elimination width setting register 1n (NCW1n) (n = 0, 1) Initial Value After Reset BFH 3DH 0FH 0002H 02H 00H 03FFH FFH 03H 0000H 00H 00H 00H 03H 0000H 00H 00H 00H 0000H 00H 00H 03H 3FH 07H E0H FFFFH FFH FFH 02H 02H Caution "Undefined" in the above table is undefined after power-on-reset, or undefined as a result of data destruction when RESET is input and the data write timing has been synchronized. For other RESET signals, data is held in the same state it was in before the RESET operation. User's Manual U16031EJ4V1UD 887 CHAPTER 16 DEBUG FUNCTION (DCU) The debug control unit (DCU) consists of three function units: an execution control unit (RCU) that realizes communication with JTAG and execution of debug processing, a trace control unit (TRCU) that implements trace functions, and a trigger event unit (TEU) that implements event detection functions. V850E/ME2 can be executed by connecting an N-Wire type emulator. Caution The debug function is supported by the V850E/ME2, but whether this function can be used or not depends on the debugger used. On-chip debugging of the 16.1 Functional Outline 16.1.1 Debug function (1) Debug interface This interface establishes communication with the host machine by using the DRST, DCK, DMS, DDI, and DDO signals, via an N-Wire type emulator. The communication specifications of JTAG are used for this interface. It does not support a boundary scan function. (2) On-chip debug On-chip debugging can be performed if wiring and connectors for debugging are provided on the target system. Connect an N-Wire type emulator to the connector for debugging. (3) Forced reset function The V850E/ME2 can be forcibly reset. (4) Forced break function Execution of the user program can be forcibly stopped (however, the handler of the illegal instruction code exception (first address: 00000060H) cannot be used). (5) Debug monitor function During debugging, a memory space for debugging, different from the user memory space, is used (background monitor format). The user program can be executed starting from any address. While execution of the user program is stopped, the user resources (such as memory and I/O) can be read/written, and the user program can be downloaded. (6) Mask function (a) NMI and all maskable interrupt request signals can be masked. (b) When the debugger is connected, the RESET pin input on the target board is masked by default (the RESET pin input is masked when the debugger is started after power application to the V850E/ME2). The RESET pin input can be unmasked from the debugger. If a signal is input to the RESET pin during debugging (during RUN execution), however, the following problems may occur. * The break function may malfunction. If this happens, restart. * Trace data may be illegal before and after RESET pin input. Recovery will occur after the RESET signal has been released. 888 User's Manual U16031EJ4V1UD CHAPTER 16 DEBUG FUNCTION (DCU) 16.1.2 Trace function (1) PC trace (branch trace) function All branches (transition of processing) that occur during user program execution can be traced. The trace sources can be selected from 12 types of branch sources that are classified by function, and PC trace can be started from execution of an instruction at any address, and the trace source can be changed. Two trace start triggers are available. (2) Data trace function A data access issued by the CPU to any address can be traced in a range of 1 KB to 4 bytes. Read or written data can be traced, and two data trace points are available. However, a data access issued by the DMAC cannot be traced. (3) Real-time trace mode Branch and data access can be traced during real-time execution of the user program. The trace packet of the trace source detected is stored in a trace buffer, and output from trace interface pins (TRCCLK, TRCDATA0 to TRCDATA3, and TRCEND) (some trace packets may not be traced if no more trace packets can be stored in the trace buffer). (4) Full trace mode (non-real-time trace mode) All branches and data accesses of the user program can be traced. In the full trace mode, the pipeline of the CPU is temporarily held and instruction execution is stopped to secure the time of trace data output from trace interface pins, so that all trace packets can be correctly traced. 16.1.3 Event function (1) Instruction event detection function Event detection (10 events) via size comparison by the execution PC and range event detection (up to four pairs with each pair consisting of two events) of the execution PC can be executed. If an instruction event source is used as a break source, two breakpoints before execution of the instruction at which an event is detected and eight breakpoints after instruction execution can be detected. (2) Access event detection function Events can be detected as follows. * Comparison of access addresses (4 addresses) * Range of access address (up to two pairs with each pair consisting of two addresses) * Match or mismatch of access data * Data of specific bit by masking data * Access size An access event source is detected after access. If an access event source is used as a break source, a break occurs after several instructions have been executed after the instruction that issued the access that caused event detection. (3) Sequential event detection function An event can be detected when up to four stages of events have successively occurred or an event that clears successive occurrence of events can be detected. Sequential events can be counted by using a 12-bit pass counter. User's Manual U16031EJ4V1UD 889 CHAPTER 16 DEBUG FUNCTION (DCU) 16.2 Connection with N-Wire Type Emulator A connector for the emulator and a connection circuit must be provided on the target system. Figure 16-1. Connecting N-Wire Type Emulator MICTOR connector (PLUG) (AMP) MICTOR connector (RECEPTACLE (2-767004-2)) (AMP) To host machine High-speed N-Wire emulator Target system 890 User's Manual U16031EJ4V1UD CHAPTER 16 DEBUG FUNCTION (DCU) 16.2.1 Emulator connector The following table shows the pin functions of the emulator connector. Table 16-1. Emulator Connector Pin Function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin Name GND GND DCK VDD DMS DRST DDI PORT0_OUT DDO PORT1_OUT (Reserved 1) PORT2_OUT (Reserved 2) PORT0_IN (Reserved 3) PORT1_IN TRCCLK PORT2_IN TRCEND TRCCE TRCDATA0 TRCDATA8 TRCDATA1 TRCDATA9 TRCDATA2 TRCDATA10 TRCDATA3 TRCDATA11 TRCDATA4 TRCDATA12 TRCDATA5 TRCDATA13 TRCDATA6 TRCDATA14 TRCDATA7 TRCDATA15 GND GND I/O Direction - - Emulator V850E/ME2 - Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 V850E/ME2 Emulator Emulator V850E/ME2 - Emulator V850E/ME2 - V850E/ME2 Emulator - V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator V850E/ME2 Emulator - - Pin Function - - Clock for debug serial interface (Emulator V850E/ME2) +3.3 V (V850E/ME2 Emulator) (for monitoring power to target) Transfer mode select for debug serial interface (Emulator V850E/ME2) DCU reset (Emulator V850E/ME2) Data for debug serial interface (Emulator V850E/ME2) General-purpose control signal 0 (Emulator V850E/ME2) Data for debug serial interface (V850E/ME2 Emulator) General-purpose control signal 1 (Emulator V850E/ME2) (Leave this pin open) General-purpose control signal 2 (Emulator V850E/ME2) (Leave this pin open) General-purpose control signal 0 (V850E/ME2 Emulator) (Leave this pin open) General-purpose control signal 1 (V850E/ME2 Emulator) Trace clock (V850E/ME2 Emulator) General-purpose control signal 2 (V850E/ME2 Emulator) Trace data end (V850E/ME2 Emulator) Trace packet compression enable signal (V850E/ME2 Emulator) Trace data 0 (V850E/ME2 Emulator) Trace data 8 (V850E/ME2 Emulator) Trace data 1 (V850E/ME2 Emulator) Trace data 9 (V850E/ME2 Emulator) Trace data 2 (V850E/ME2 Emulator) Trace data 10 (V850E/ME2 Emulator) Trace data 3 (V850E/ME2 Emulator) Trace data 11 (V850E/ME2 Emulator) Trace data 4 (V850E/ME2 Emulator) Trace data 12 (V850E/ME2 Emulator) Trace data 5 (V850E/ME2 Emulator) Trace data 13 (V850E/ME2 Emulator) Trace data 6 (V850E/ME2 Emulator) Trace data 14 (V850E/ME2 Emulator) Trace data 7 (V850E/ME2 Emulator) Trace data 15 (V850E/ME2 Emulator) - - Remark Cautions are given on the next page. User's Manual U16031EJ4V1UD 891 CHAPTER 16 DEBUG FUNCTION (DCU) Cautions 1. The connection of pins not supported by the V850E/ME2 depends on the emulator used. 2. The pattern on the target board must satisfy the following conditions to support high-speed interfacing. * Lay out the pattern with the odd pins facing the device (V850E/ME2). * Keep the pattern length to within 1.97 inches (50 mm). * Shield the clock signal with GND. V850E/ME2 MICTOR connector (RECEPTACLE (2-767004-2)) 1 2 37 38 16.2.2 Recommended circuit example The following figure shows an example of the recommended circuit of the emulator connector (on the target system side). Figure 16-2. Example of Recommended Emulator Connection Circuit +3.3 V V850E/ME2 4.7 k 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 1, 37 MICTOR connector (RECEPTACLE) 2-767004-2 DCK DMS DDI DDO DRST Note 2 Note 1 Note 1 Note 1 Note 1 22 TRCCLK TRCEND TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 Note 2 Note 1 Note 1 Note 1 Note 1 Note 1 22 22 22 22 22 22 (Open) (Open) (Open) 50 k 50 k 50 k 50 k DCK DMS DDI DDO (Reserved 1) (Reserved 2) (Reserved 3) TRCCLK TRCEND TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 TRCDATA4 TRCDATA5 TRCDATA6 TRCDATA7 GND GND VDDNote 3 DRST PORT0_OUT PORT1_OUT PORT2_OUT PORT0_IN PORT1_IN PORT2_IN TRCCE TRCDATA8 TRCDATA9 TRCDATA10 TRCDATA11 TRCDATA12 TRCDATA13 TRCDATA14 TRCDATA15 GND 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 2, 38 +3.3 V 50 k 50 k 50 k 50 k 50 k 50 k 50 k 50 k 50 k GROUND BUS Notes 1. Keep the pattern length to within 1.97 inches (50 mm). 2. Shield the DCK and TRCCLK signals by GND. 3. For detecting power to the target board Caution The recommended circuit example shown above assumes that a 3.3 V interface is used. 892 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol IVDD IVSS EVDD EVSS OSCVDD OSCVSS PLLVDD PLLVSS UVDD AVDD AVSS Input voltage Clock input voltage Output current, low VI VK IOL IVDD pin IVSS pin EVDD pin, EVDD IVDD EVSS pin OSCVDD pin OSCVSS pin PLLVDD pin PLLVSS pin UVDD pin AVDD pin, AVDD < EVDD 0.5 V AVSS pin Except for X1 pin, VI < EVDD + 0.3 V X1 pin Per pin Total of all pins Output current, high IOH Per pin Total of all pins Output voltage Analog input voltage A/D converter reference input voltage Operating ambient temperature Storage temperature Tstg VO VWASN AVREFP AVREFM TA 30 pF < output pin load capacitance 50 pF Output pin load capacitance 30 pF EVDD = 3.3 V 0.3 V ANI0 to ANI7 pins, AVDD = 3.3 V 0.3 V Conditions Ratings -0.5 to +2.0 -0.5 to +0.5 -0.5 to +4.6 -0.5 to +0.5 -0.5 to +4.6 -0.5 to +0.5 -0.5 to +2.0 -0.5 to +0.5 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +0.5 -0.5 to +4.6 -0.5 to OSCVDD + 0.5 4.0 100 -4.0 -100 -0.5 to EVDD + 0.5 -0.3 to AVDD + 0.3 -0.3 to AVDD + 0.3 -0.3 to +0.3 -40 to +70 -40 to +85 -60 to +150 Note Note Unit V V V V V V V V V V V V V mA mA mA mA V V V V C C C Note Note Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to IVDD, EVDD, and GND. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC Characteristics and AC Characteristics represent the quality assurance range during normal operation. User's Manual U16031EJ4V1UD 893 CHAPTER 17 ELECTRICAL SPECIFICATIONS Capacitance (TA = 25C, IVDD = IVSS = EVDD = EVSS = OSCVDD = OSCVSS = PLLVDD = PLLVSS = UVDD = AVDD = AVSS = 0 V) Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO fc = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF Operating Conditions Part Number Internal Operation Clock Frequency (fX) 10 to 100 MHz Operating Ambient Temperature (TA) When external pin load capacitance CL = 50 pF, -40 to +70C When external pin load capacitance CL = 30 pF, -40 to +85C Supply Voltage (VDD) IVDD = 1.5 V 0.15 V PLLVDD = 1.5 V 0.15 V EVDD = 3.3 V 0.3 V OSCVDD = 3.3 V 0.3 V UVDD = 3.3 V 0.3 V AVDD = 3.3 V 0.3 V PD7030111AGM-10-UEU PD7030111AGM-13-UEU PD7030111AF1-13-GA3 10 to 133 MHz When external pin load capacitance CL = 50 pF, -40 to +70C When external pin load capacitance CL = 30 pF, -40 to +85C PD7030111AGM-15-UEU PD7030111AF1-15-GA3 10 to 150 MHz When external pin load capacitance CL = 50 pF, -40 to +70C IVDD = 1.4 to 1.65 V PLLVDD = 1.4 to 1.65 V EVDD = 3.3 V 0.3 V OSCVDD = 3.3 V 0.3 V UVDD = 3.3 V 0.3 V AVDD = 3.3 V 0.3 V 894 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS Recommended Oscillator (a) Ceramic resonator (i) Murata Mfg. Co., Ltd. (TA = -40 to +85C) X1 X2 Rd C1 C2 Type Part Number Oscillation Frequency fX (MHz) Recommended Circuit Constant Oscillation Voltage Range Oscillation Stabilization Time (MAX.) TOST (ms) C1 (pF) On-chip On-chip On-chip On-chip On-chip C2 (pF) On-chip On-chip On-chip On-chip On-chip Rd (k) 0 0 0 0 0 MIN. (V) 3.0 3.0 3.0 3.0 3.0 MAX. (V) 3.6 3.6 3.6 3.6 3.6 Surface mounting CSTCE10M0G55-R0 CSTCE12M5G55-R0 CSTCE16M6V53-R0 CSTCE18M0V53-R0 CSTCE18M7V53-R0 10.000 12.500 16.625 18.000 18.750 0.07 0.08 0.04 0.03 0.03 Cautions 1. Connect the oscillator as close as possible to the X1 and X2 pins. 2. Do not route the wiring near broken lines. 3. Sufficiently evaluate the matching between the PD703111A and the resonator. User's Manual U16031EJ4V1UD 895 CHAPTER 17 ELECTRICAL SPECIFICATIONS (ii) TDK (TA = -40 to +85C) X1 X2 Rd C1 C2 Type Part Number Oscillation Frequency fX (MHz) Recommended Circuit Constant Oscillation Voltage Range Oscillation Stabilization Time (MAX.) TOST (ms) C1 (pF) C2 (pF) Rd (k) MIN. (V) MAX. (V) Lead Surface mounting FCR10.0MC5 CCR18.0MXC7 10.0 18.0 On-chip On-chip On-chip On-chip 0 0 3.0 3.0 3.6 3.6 0.076 0.9 Cautions 1. Connect the oscillator as close as possible to the X1 and X2 pins. 2. Do not route the wiring near broken lines. 3. Sufficiently evaluate the matching between the PD703111A and the resonator. 896 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C, EVDD = 3.3 V 0.3 V, EVSS = 0 V) Parameter Input voltage, high Symbol VIH Conditions Except for Notes 1, 2 Note 1 Note 2 Input voltage, low VIL Except for Notes 1, 2 Note 1 Note 2 Schmitt-triggered input threshold voltage Schmitt-triggered input hysteresis width Output voltage, high VT + MIN. 2.0 0.75EVDD 2.0 -0.5 -0.5 -0.5 TYP. MAX. EVDD + 0.3 EVDD + 0.3 UVDD + 0.3 0.8 0.2EVDD 0.8 Unit V V V V V V V V V V V V Note 1, rising edge Note 1, falling edge Note 1 Except for Note 2 IOH = -2.5 mA IOH = -100 A 0.3 0.8EVDD EVDD - 0.4 2.8 1.9 1.3 0.6 VT- VT -VT- + VOH Note 2, RL = 15 k (EVSS connection) Output voltage, low VOL Except for Note 2, IOL = 2.5 mA Note 2, RL = 15 k (UVDD connection) Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Analog pin input leakage current Supply current Normal ILIH ILIL ILOH ILOL ILWASN IDD1 VI = EVDD, except for Note 3 VI = 0 V, except for Note 3 VO = EVDD VO = 0 V Note 3 IVDD + PLLVDD pins EVDD pin HALT IDD2 Note 4 0.45 0.3 10 -10 10 -10 10 0.82 x fX + 10 0.82 x fX + 4 0.015 x fX + 10 500 4 500 0.90 x fX + 117 Note 5 V V A A A A A mA mA mA mA mA 0.33 x FBUS + 3.2 0.66 x FBUS + 6.4 0.33 x FBUS + 3.2 0.66 x FBUS + 6.4 IVDD + PLLVDD pins EVDD pin Note 4 0.85 x fX + 114 Note 5 IDLE IDD3 IVDD + PLLVDD pins EVDD pin Note 4 A mA STOP IDD4 IVDD + PLLVDD pins EVDD pin Note 4 A Notes 1. P11/SCK0/INTP11, P12/RXD0/SI0, P20/NMI, P21/RXD1/INTP21, P23/SCK1/INTP23, P24/SI1/INTP24, PCM1, RESET 2. UDM, UDP 3. ANI0 to ANI7 4. Current value with no load 5. Calculate the current value with a load using the following expression. Current value per pin (A) = 3.63 x CL x F CL: Load capacitance (pF) F: Pin average operating frequency Remarks 1. TYP. values are reference values for when TA = 25C, EVDD = 3.3 V. The current that flows through pullup resistors is not included. 2. fX: Main clock frequency (MHz) FBUS: USCLK frequency (MHz) User's Manual U16031EJ4V1UD 897 CHAPTER 17 ELECTRICAL SPECIFICATIONS AC Characteristics (TA = -40 to +85C, IVDD = PLLVDD = 1.5 V 0.15 VNote, EVDD = OSCVDD = 3.3 V 0.3 V, IVSS = EVSS = PLLVSS = OSCVSS = 0 V, output pin load capacitance: CL = 30 pF) (TA = -40 to +70C, IVDD = PLLVDD = 1.5 V 0.15 VNote, EVDD = OSCVDD = 3.3 V 0.3 V, IVSS = EVSS = PLLVSS = OSCVSS = 0 V, output pin load capacitance: CL = 50 pF) Note Consider the operation conditions when operating at 133.34 to 150 MHz. AC test input measurement points (a) P11/SCK0/INTP11, P12/RXD0/SI0, P20/NMI, P21/RXD1/INTP21, P23/SCK1/INTP23, P24/SI1/INTP24, PCM1, RESET EVDD Input signal 0.75EVDD 0.2EVDD Measurement points 0.75EVDD 0.2EVDD 0V (b) Other than (a) EVDD Input signal 2.0 V 0.8 V Measurement points 2.0 V 0.8 V 0V AC test output measurement points 0.7EVDD Output signal Measurement points 0.7EVDD 0.2EVDD 0.2EVDD 898 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS Load conditions DUT (Device under test) C L = 50 pF or CL = 30 pF Caution At -40 to +70C: If the load capacitance exceeds 50 pF due to the circuit configuration, make the load capacitance of this device 50 pF or lower by inserting a buffer, etc. At -40 to +85C: If the load capacitance exceeds 30 pF due to the circuit configuration, make the load capacitance of this device 30 pF or lower by inserting a buffer, etc. User's Manual U16031EJ4V1UD 899 CHAPTER 17 ELECTRICAL SPECIFICATIONS (1) Clock timing Parameter X1 input cycle BUSCLK output cycle Symbol <1> <2> tCYX tCYK Conditions Including resonator error Output load capacitance 30 pF, TA = -40 to +85C 30 pF < output load capacitance 50 pF, TA = -40 to +70C BUSCLK high-level width BUSCLK low-level width BUSCLK rise time BUSCLK fall time <3> <4> <5> <6> tWKH1 tWKL1 tKR1 tKF1 0.5T - 2 0.5T - 2 0.5T + 2 0.5T + 2 3 3 ns ns ns ns 19.0 400 Note MIN. 52.5 14.3 MAX. 100 400 Note Unit ns ns ns Note The output cycle after SSCG output is selected by the CKS register. T = tCYK Remark <1> X1 BUSCLK (output) <5> <6> <3> <2> <4> 900 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (2) Output waveform (other than X1, BUSCLK) Parameter Output rise time Symbol <7> tOR Other than Note Note Output fall time <8> tOF Other than Note Note Conditions MIN. MAX. 6 8 6 8 Unit ns ns ns ns Note P10/UCLK/INTP10, P12/RXD0/SI0, P20/NMI, P21/RXD1/INTP21, P22/TXD1/INTP22, P24/SI1/INTP24, P50/DMARQ0/INTP50, P51/DMAAK0/INTP51, P52/TC0/INTP52, P53/DMARQ1/TIC0/INTPC00, P54/DMAAK1/INTPC01, P55/TC1/TOC0, P65/INTPC10/TIC1/INTP65, P66/INTPC11/INTP66, P67/TOC1/INTP67, P72/DMARQ2/INTPC20/TIC2, P73/DMAAK2/INTPC21, P74/TC2/TOC2, P75/DMARQ3/INTPC30/TIC3, P76/DMAAK3/INTPC31, P77/TC3/TOC3 <7> <8> Signal other than X1, BUSCLK (3) Reset timing Parameter RESET pin high-level width RESET pin low-level width Symbol <9> <10> tWRSH tWRSL Including oscillation stabilization time at power on and STOP mode release. However, when the oscillation stabilization time exceeds 100 s, secure the necessary oscillation stabilization time. Excluding at power on and STOP mode release. 100 Conditions MIN. 500 100 MAX. Unit ns s s Caution Sufficiently evaluate the oscillation stabilization time. <9> <10> RESET (input) User's Manual U16031EJ4V1UD 901 CHAPTER 17 ELECTRICAL SPECIFICATIONS (4) SRAM, external ROM, external I/O access timing (a) Access timing (SRAM, external ROM, external I/O) (1/2) Parameter Address, CSn output delay time (from BUSCLK) Address, CSn output hold time (from BUSCLK) RD, IORD delay time (from BUSCLK) RD, IORD delay time (from BUSCLK) xxWR, IOWR, WR delay time (from BUSCLK) xxWR, IOWR, WR delay time (from BUSCLK) BCYST delay time (from BUSCLK) BCYST delay time (from BUSCLK) WAIT setup time (to BUSCLK) WAIT hold time (from BUSCLK) Data input setup time (to BUSCLK) Data input hold time (from BUSCLK) Data output delay time (from BUSCLK) Data float delay time (from BUSCLK) Symbol <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> tDKA tHKA tDKRDL tDKRDH tDKWRL tDKWRH tDKBSL tDKBSH tSWK tHKW tSKID tHKID tDKOD1 tHKOD Conditions MIN. 2 2 1 2 2 1 2 2 6 2 6 2 2 2 11 11 MAX. 11 11 11 11 11 11 11 11 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. Observe at least one of the data input hold times tHRDID and tHKID. 2. n = 0 to 7 xx = UU, UL, LU, LL 902 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (a) Access timing (SRAM, external ROM, external I/O) (2/2) T1 BUSCLK (output) TW T2 <11> A0 to A25 (output) CSn (output) <12> <17> <18> <17> BCYST (output) <14> IORD, RD (output) [read] <13> <14> <13> <16> UUWR, ULWR (output) LUWR, LLWR (output) IOWR, WR (output) [write] <15> <16> <15> <21> <24> D0 to D31 (I/O) [read] <22> <23>Note D0 to D31 (I/O) [write] <20> <19> <19> <20> <24> WAIT (input) Note When a write cycle is executed without inserting a T0 state immediately after a read cycle, the data output timing is delayed by a half clock (in synchronization with the falling edge of BUSCLK). Remarks 1. Timing when the number of waits set by the DWC0 and DWC1 registers is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7 User's Manual U16031EJ4V1UD 903 CHAPTER 17 ELECTRICAL SPECIFICATIONS (b) Read timing (SRAM, external ROM, external I/O) (1/2) Parameter Data input setup time (to address) Data input setup time (to RD) RD, IORD low-level width RD, IORD high-level width Delay time from address, CSn to RD, IORD Delay time from RD, IORD to address Data input hold time (from RD, IORD) Delay time from RD, IORD to data output WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) WAIT high-level width Data output hold time (from xxWR, IOWR, WR) <33> <34> <35> <36> <37> tSAW tSBSW tHBSW tWWH tHWROD Note 1 Note 1 Note 1 Note 2 (wAS + wD) T + 2 T+2 (0.5 + i) T - 5.5 (1 + wAS) T - 17 (1 + wAS) T - 17 ns ns ns ns ns <32> tDRDOD (0.5 + i) T - 6 ns <31> tHRDID 0 ns <30> tDRDA iT - 2 ns Symbol <25> <26> <27> <28> <29> tSAID tSRDID tWRDL tWRDH tDARD (1.5 + w + wD) T - 6 (0.5 + wAS + i) T - 6 (0.5 + wAS) T - 7.5 Conditions MIN. MAX. (2 + w + wD + wAS) T - 17 (1.5 + w + wD) T - 17 Unit ns ns ns ns ns Notes 1. At the first WAIT sampling 2. Time necessary for releasing the wait state Remarks 1. T = tCYK 2. w: Number of waits inserted due to WAIT 3. wD: Number of waits inserted by DWC0 and DWC1 registers 4. Observe at least one of the data input hold times tHRDID and tHKID. 5. n = 0 to 7 xx = UU, UL, LU, LL 6. i: Number of idle states 7. wAS: Number of address setup waits inserted by ASC register 8. For the number of w and wD to be inserted, refer to 4.7.3 Relationship between programmable wait and external wait. 904 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (b) Read timing (SRAM, external ROM, external I/O) (2/2) TASW T1 TW T2 TI BUSCLK (output) A0 to A25 (output) CSn (output) UUBE,ULBE (output) LUBE, LLBE (output) Note UUWR, ULWR (output) LUWR, LLWR (output) IOWR, WR (output) <28> <27> <30> RD, IORD (output) <29> <37> <26> <25> <32> <31> D0 to D31 (I/O) <33> <36> WAIT (input) <34> <35> BCYST (output) Note In the case of the CSn signal Remarks 1. Timing when the number of waits inserted by the DWC0 or DWC1 register is 0, the number of idle states inserted by the BCC register is 1, and the number of waits inserted by the ASC register is 1. 2. Broken lines indicate high impedance. 3. n = 0 to 7 User's Manual U16031EJ4V1UD 905 CHAPTER 17 ELECTRICAL SPECIFICATIONS (c) Write timing (SRAM, external ROM, external I/O) (1/2) Parameter WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) WAIT high-level width Delay time from address, CSn to xxWR, IOWR, WR Address setup time (to xxWR, IOWR, WR) Delay time from xxWR, IOWR, WR to address xxWR, IOWR, WR high-level width xxWR, IOWR, WR low-level width Data output setup time (to xxWR, IOWR, WR) Data output hold time (from xxWR, IOWR, WR) <37> tHWROD (0.5 + i) T - 5.5 ns <42> <43> tWWRL tSODWR (1 + w + wD) T - 5 (1.5 + wAS + w + wD) T - 5 ns ns <41> tWWRH (1 + i + wAS) T - 5 ns <40> tDWRA (0.5 + i) T - 5 ns <39> tSAWR (1.5 + w + wD + wAS) T - 10 ns Symbol <33> <34> <35> <36> <38> tSAW tSBSW tHBSW tWWH tDAWR Conditions Note 1 Note 1 Note 1 Note 2 (wAS + wD) T + 2 T+2 (0.5 + wAS) T - 7 MIN. MAX. (1 + wAS) T - 17 (1 + wAS) T - 17 Unit ns ns ns ns ns Notes 1. At the first WAIT sampling 2. Time necessary for releasing the wait state Remarks 1. T = tCYK 2. w: Number of waits inserted due to WAIT 3. wD: Number of waits inserted by DWC0 and DWC1 registers 4. n = 0 to 7 xx = UU, UL, LU, LL 5. i: Number of idle states 6. wAS: Number of address setup waits inserted by ASC register 7. For the number of w and wD to be inserted, refer to 4.7.3 Relationship between programmable wait and external wait. 906 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (c) Write timing (SRAM, external ROM, external I/O) (2/2) TASW BUSCLK (output) T1 TW T2 TI A0 to A25 (output) CSn (output) UUBE, ULBE (output) LUBE, LLBE (output) Note <39> <38> <41> <42> <40> UUWR, ULWR (output) LUWR, LLWR (output) IOWR, WR (output) <43> D0 to D31 (I/O) <37> <33> <36> WAIT (input) <34> <35> BCYST (output) Note In the case of the CSn signal Remarks 1. Timing when the number of waits inserted by the DWC0 or DWC1 register is 0, the number of idle states inserted by the BCC register is 1, and the number of waits inserted by the ASC register is 1. 2. Broken lines indicate high impedance. 3. n = 0 to 7 User's Manual U16031EJ4V1UD 907 CHAPTER 17 ELECTRICAL SPECIFICATIONS (d) DMA flyby transfer timing (transfer from SRAM to external I/O) (1/2) Parameter WAIT setup time (to BUSCLK) WAIT hold time (from BUSCLK) RD low-level width RD high-level width Delay time from address, CSn to RD Delay time from RD to address Delay time from RD to data output WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) WAIT high-level width Delay time from address to IOWR Address setup time (to IOWR) Delay time from IOWR to address IOWR high-level width IOWR low-level width Delay time from IOWR to RD Symbol <19> <20> <27> <28> <29> <30> <32> <33> <34> <35> <36> <38> <39> <40> <41> <42> <44> tSWK tHKW tWRDL tWRDH tDARD tDRDA tDRDOD tSAW tSBSW tHBSW tWWH tDAWR tSAWR tDWRA tWWRH tWWRL tDIWRRD tDDAWR tDWRDA Note Note Note (wAS + wFW) T + 2 T+2 (0.5 + wAS) T - 7 (1.5 + w + wFW + wAS) T - 10 (0.5 + i) T - 5 (0.5 + i + wAS) T - 5 (1 + w + wFW) T - 5 0.5T - 4 (0.5 + wAS) T - 7.5 (1.5 + i) T - 10 Conditions MIN. 6 2 (1.5 + w + wFW) T - 6 (0.5 + wAS + i) T - 6 (0.5 + wAS) T - 7.5 iT - 2 (0.5 + i) T - 6 (1 + wAS + wFW) T - 17 (1 + wAS + wFW) T - 17 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Delay time from DMAAKm to IOWR <45> Delay time from IOWR to DMAAKm <46> Note At the second and subsequent WAIT sampling Remarks 1. T = tCYK 2. w: Number of waits inserted due to WAIT 3. wFW: Number of waits inserted by FWC register 4. n = 0 to 7, m = 0 to 3 5. i: Number of idle states 6. wAS: Number of address setup waits inserted by ASC register 908 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (d) DMA flyby transfer timing (transfer from SRAM to external I/O) (2/2) TASW BUSCLK (output) T1 TF TW T2 TI A0 to A25 (output) CSn (output) UUBE, ULBE (output) LUBE, LLBE (output) <28> <27> Note <30> RD (output) <29> <44> UUWR, ULWR (output) LUWR, LLWR (output) WR (output) DMAAKm (output) <45> IORD (output) <39> <38> <41> IOWR (output) <42> <40> <46> <32> D0 to D31 (I/O) <33> <19> WAIT (input) <34> <35> BCYST (output) <36> <20> <19> <20> Note In the case of the CSn signal Remarks 1. Timing when the number of waits inserted by the FWC register is 1, the number of idle states inserted by the FIC register is 1, and the number of waits inserted by the ASC register is 1. 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 User's Manual U16031EJ4V1UD 909 CHAPTER 17 ELECTRICAL SPECIFICATIONS (e) DMA flyby transfer timing (transfer from external I/O to SRAM) (1/2) Parameter WAIT setup time (to BUSCLK) WAIT hold time (from BUSCLK) IORD low-level width IORD high-level width Delay time from address, CSn to IORD Delay time from IORD to address Delay time from IORD to data output WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) WAIT high-level width Delay time from address to xxWR, WR Address setup time (to xxWR, WR) Delay time from xxWR, WR to address xxWR, WR high-level width xxWR, WR low-level width <41> <42> tWWRH tWWRL tDWRIRD tDDARD tDRDDA (1 + i + wAS) T - 5 (1 + w + wFW) T - 5 0.5T - 4 (0.5 + wAS) T - 7.5 (0.5 + i) T - 7.5 ns ns ns ns ns <40> tDWRA (0.5 + i) T - 5 ns <39> tSAWR (1.5 + w + wFW + wAS) T - 10 ns <30> <32> <33> <34> <35> <36> <38> tDRDA tDRDOD tSAW tSBSW tHBSW tWWH tDAWR Note Note Note (wAS + wFW) T + 2 T+2 (0.5 + wAS) T - 7 iT - 2 (0.5 + i) T - 6 (1 + wAS + wFW) T - 17 (1 + wAS + wFW) T - 17 ns ns ns ns ns ns ns Symbol <19> <20> <27> <28> <29> tSWK tHKW tWRDL tWRDH tDARD Conditions MIN. 6 2 (2 + w + wFW) T - 6 (1 + wAS + i) T - 6 (0.5 + wAS) T - 7.5 MAX. Unit ns ns ns ns ns Delay time from xxWR, WRto IORD <47> Delay time from DMAAKm to IORD Delay time from IORD to DMAAKm <48> <49> Note At the second and subsequent WAIT sampling Remarks 1. T = tCYK 2. w: Number of waits inserted due to WAIT 3. wFW: Number of waits inserted by FWC register 4. n = 0 to 7, m = 0 to 3 xx = UU, UL, LU, LL 5. i: Number of idle states inserted when a write cycle is inserted after a read cycle 6. wAS: Number of address setup waits inserted by ASC register 910 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (e) DMA flyby transfer timing (transfer from external I/O to SRAM) (2/2) TASW BUSCLK (output) T1 TF TW T2 TI A0 to A25 (output) CSn (output) UUBE, ULBE (output) LUBE, LLBE (output) <38> <41> UUWR, ULWR (output) LUWR, LLWR (output) WR (output) Note <39> <42> <40> <47> RD (output) <48> <49> DMAAKm (output) IOWR (output) <29> <28> IORD (output) <27> <30> <32> D0 to D31 (I/O) <33> <19> WAIT (input) <34> <35> BCYST (output) <36> <20> <19> <20> Note In the case of the CSn signal Remarks 1. Timing when the number of waits inserted by the FWC register is 1, the number of idle states inserted by the FIC register is 1, and the number of waits inserted by the ASC register is 1. 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 User's Manual U16031EJ4V1UD 911 CHAPTER 17 ELECTRICAL SPECIFICATIONS (5) Page ROM access timing (1/2) Parameter WAIT setup time (to BUSCLK) WAIT hold time (from BUSCLK) Data input setup time (to BUSCLK) Data input hold time (from BUSCLK) Off-page data input setup time (to address) Off-page data input setup time (to RD) Data input hold time (from RD) Delay time from RD to data output On-page data input setup time (to address) <50> tSOAID (2 + w + wPR) T - 17 ns <31> <32> tHRDID tDRDOD 2 (0.5 + i) T - 6 ns ns <26> tSRDID (1.5 + w + wD) T - 17 ns <25> tSAID (2 + w + wD + wAS) T - 17 ns <22> tHKID 2 ns Symbol <19> <20> <21> tSWK tHKW tSKID Conditions MIN. 6 2 6 MAX. Unit ns ns ns Remarks 1. T = tCYK 2. w: Number of waits inserted due to WAIT 3. wD: Number of waits inserted by DWC0 and DWC1 registers 4. wPR: Number of waits inserted by PRC register 5. i: Number of idle states inserted when a write cycle is inserted after a read cycle 6. wAS: Number of address setup waits inserted by ASC register 7. Observe at least one of the data input hold times tHRDID and tHKID. 8. For the number of w and wD to be inserted, refer to 4.7.3 Relationship between programmable wait and external wait. 912 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (5) Page ROM access timing (2/2) TASW BUSCLK (output) T1 TDW TWT2 TO1 TPRW TW TO2 CSn (output) AddressNote (output) <21> <25> UUWR, ULWR (output) LUWR, LLWR (output) WR (output) <26> RD (output) <31> <21> <22> D0 to D31 (I/O) <20> <19> WAIT (input) <19> <20> <19> <20> <32> <19> <20> <22> <50> Note On-page addresses and off-page addresses are shown below. PRC register MA6 0 0 0 0 1 MA5 0 0 0 1 1 MA4 0 0 1 1 1 MA3 0 1 1 1 1 A0 to A2 A0 to A3 A0 to A4 A0 to A5 A0 to A6 A3 to A25 A4 to A25 A5 to A25 A6 to A25 A7 to A25 On-page address Off-page address Remarks 1. Timing in the following case. Number of waits inserted by DWC0 or DWC1 register (TDW): 1 Number of waits inserted by PRC register (TPRW): 1 Number of waits inserted by ASC register (TASW): 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 User's Manual U16031EJ4V1UD 913 CHAPTER 17 ELECTRICAL SPECIFICATIONS (6) SDRAM access timing (a) Read timing (SDRAM access) (1/2) Parameter Address delay time (from BUSCLK) BCYST delay time (from BUSCLK) CSn delay time (from BUSCLK) SDRAS delay time (from BUSCLK) SDCAS delay time (from BUSCLK) xxDQM delay time (from BUSCLK) SDCKE delay time (from BUSCLK) Data input setup time (SDRAM read, from BUSCLK) Data input hold time (SDRAM read, from BUSCLK) Delay time from BUSCLK to data output <59> tDSDOD (0.5 + i) T ns <58> tHKDRM 2 ns Symbol <11> <51> <52> <53> <54> <55> <56> <57> tDKA tDKBC tDKCS tDKRAS tDKCAS tDKDQM tDKCKE tSDRMK Conditions MIN. 2 2 2 2 2 2 2 6 MAX. 11 11 11 11 11 11 11 Unit ns ns ns ns ns ns ns ns Caution If an SRAM (external I/O) cycle that uses the xxWR signal is generated immediately after a read cycle to SDRAM, an SRAM (external I/O) writing error may occur. In this case, set the BCC register to insert an idle state in the SDRAM space or execute a countermeasure using external circuits. However, no writing error occurs in a synchronization design in which the xxWR signal is sampled using BUSCLK. Remarks 1. T = tCYK 2. i: Number of idle states 3. n = 1, 3, 4, 6 xx = UU, UL, LU, LL 914 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (a) Read timing (SDRAM access) (2/2) T0 SDCLK (output) <11> Bank address, A2 to A11, address other than A12 (output) <11> Bank address (output) <11> A12 (output) <11> A2 to A11 (output) <51> BCYST (output) <52> SDRAM: CSn (output) <53> SDRAS (output) <54> SDCAS (output) <54> <53> <52> Row address <11> Row address <51> Column address <11> Bank address Address <11> TACT TBCW TREAD TLATE TLATE WE (output) <55> UUDQM, ULDQM (output) LUDQM, LLDQM (output) <59> <57> <58> D0 to D31 (I/O) <56> SDCKE (output) Data <56> <55> Remarks 1. Number of waits inserted by BCW1n and BCW0n bits of the SCRn register (TBCW): 2 2. Broken lines indicate high impedance. 3. n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 915 CHAPTER 17 ELECTRICAL SPECIFICATIONS (b) Write timing (SDRAM access) (1/2) Parameter Address delay time (from BUSCLK) BCYST delay time (from BUSCLK) CSn delay time (from BUSCLK) SDRAS delay time (from BUSCLK) SDCAS delay time (from BUSCLK) xxDQM delay time (from BUSCLK) SDCKE delay time (from BUSCLK) WE delay time (from BUSCLK) Data output delay time (from BUSCLK) Data float delay time (from BUSCLK) <62> tHZKDT 2 11 ns Symbol <11> <51> <52> <53> <54> <55> <56> <60> <61> tDKA tDKBC tDKCS tDKRAS tDKCAS tDKDQM tDKCKE tDKWE tDKDT Conditions MIN. 2 2 2 2 2 2 2 2 2 MAX. 11 11 11 11 11 11 11 11 11 Unit ns ns ns ns ns ns ns ns ns Caution If an SRAM (external I/O) cycle that uses the xxWR signal is generated immediately after a read cycle to SDRAM, an SRAM (external I/O) writing error may occur. countermeasure using external circuits. However, no writing error occurs in a synchronization design in which the xxWR signal is sampled using BUSCLK. Remark n = 1, 3, 4, 6 xx = UU, UL, LU, LL In this case, execute a 916 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (b) Write timing (SDRAM access) (2/2) T0 BUSCLK (output) TACT TBCW TWR <11> Bank address, A2 to A11, address other than A12 (output) <11> Bank address (output) <11> A12 (output) <11> A2 to A11 (output) <51> BCYST (output) <52> SDRAM: CSn (output) <53> SDRAS (output) <54> SDCAS (output) <60> WE (output) <55> UUDQM, ULDQM (output) LUDQM, LLDQM (output) <61> D0 to D31 (I/O) <56> SDCKE (output) Data <53> Row address <11> Bank address Address <11> <11> Row address Column address <51> <52> <54> <60> <55> <62> <56> Remarks 1. Number of waits inserted by BCW1n and BCW0n bits of SCRn register (TBCW): 2 2. Broken lines indicate high impedance. 3. n = 1, 3, 4, 6 User's Manual U16031EJ4V1UD 917 CHAPTER 17 ELECTRICAL SPECIFICATIONS (c) DMA flyby transfer timing (transfer from external I/O to SDRAM) (1/2) Parameter Address delay time (from BUSCLK) IORD delay time (from BUSCLK) IORD delay time (from BUSCLK) BCYST delay time (from BUSCLK) CSn delay time (from BUSCLK) SDRAS delay time (from BUSCLK) SDCAS delay time (from BUSCLK) xxDQM delay time (from BUSCLK) SDCKE delay time (from BUSCLK) WE delay time (from BUSCLK) DMAAKx output delay time (from BUSCLK) DMAAKx output hold time (from BUSCLK) IORD low-level width IORD high-level width Delay time from IORD to data output <102> tWRDL <103> tWRDH <104> tDRDOD (1.5 + wFW) T - 6 (1.5 + wAS + i) T - 6 (1 + i) T - 6 ns ns ns <66> tHKDA 0 13 ns Symbol <11> <13> <14> <51> <52> <53> <54> <55> <56> <60> <65> tDKA tDKRDL tHKRDH tDKBC tDKCS tDKRAS tDKCAS tDKDQM tDKCKE tDKWE tDKDA Conditions MIN. 2 1 2 2 2 2 2 2 2 2 0 MAX. 11 11 11 11 11 11 11 11 11 11 13 Unit ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK 2. i: Number of idle states 3. wAS: Number of address setup waits inserted by ASC register 4. wFW: Number of data waits inserted by FWC register 5. n = 1, 3, 4, 6 xx = UU, UL, LU, LL x = 0 to 3 918 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (c) DMA flyby transfer timing (transfer from external I/O to SDRAM) (2/2) T0 BUSCLK (output) <11> Bank address, A2 to A11, address other than A12 (output) <11> Bank address (output) <11> A12 (output) <11> A2 to A11 (output) <51> BCYST (output) <52> SDRAM: CSn (output) TACT TBCW TF TWR T0 T1 <11> Address <11> Bank Address address <11> Address <11> Row address <11> <11> Column address Row Address address <51> <52> <53> SDRAS (output) <53> <54> SDCAS (output) <60> WE (output) <55> UUDQM, ULDQM (output) LUDQM, LLDQM (output) <54> <60> <55> D0 to D31 (I/O) <56> SDCKE (output) <65> DMAAKx (output) Data <56> <66> IOWR (output) H <13> <14> <103> IORD (output) <102> <104> Remarks 1. Broken lines indicate high impedance. 2. n = 1, 3, 4, 6 x = 0 to 3 User's Manual U16031EJ4V1UD 919 CHAPTER 17 ELECTRICAL SPECIFICATIONS (7) DMAC timing (a) Level mode (1/3) Parameter DMARQn setup time (to BUSCLK) DMARQn hold time (from DMAAKn) Symbol <63> <64> tSDRK tHKDR Conditions 2-cycle/flyby transfer 2-cycle transfer MIN. 8 0 4TCPU - 20 6TCPU - 20 Flyby transfer 0 Note 1 MAX. Unit ns ns ns ns Note 2 2TBUS + wAS + wFW + wIC + 2TCPU - 20 Note 3 DMAAKn output delay time (from BUSCLK) DMAAKn output hold time (from BUSCLK) <65> tDKDA 2-cycle transfer Flyby transfer 0 0 0 0 nTCPU + 13 13 nTCPU + 13 13 ns ns <66> tHKDA 2-cycle transfer Flyby transfer Note 3 ns ns Notes 1. Second DMA transfer request disable timing in single transfer. The accesses are as follows. Transfer Source Internal data RAM Transfer Destination External memory/ internal instruction RAM External memory Internal data RAM Provided/none However, when the speculative read function is not provided, the following conditions apply. * BUSCLK = Internal system clock (fCLK) * External memory access wait setting = 0 Provided/none Speculative Read Function 2. Second DMA transfer request disable timing in single transfer. The access is other than that shown in the table in Note 1. 3. n is as follows. CKM1 0 0 1 1 CKM0 0 1 0 1 BUSCLK Division Ratio with Respect to Internal System Clock (fCLK) fCLK/1 fCLK/2 fCLK/3 fCLK/4 n 1 2 3 4 Remarks 1. n = 0 to 3 2. TBUS = 1 x BUSCLK cycle 3. TCPU = 1 x internal system clock (fCLK) cycle 4. wAS = Number of address setup waits inserted by ASC register wFW = Number of data waits inserted by FWC register wIC = Number of idle states inserted by FIC register 920 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (a) Level mode (2/3) Parameter Symbol tWDAL Conditions 2-cycle transfer Note 1 Note 3 MIN. 2TCPU - 8 6TCPU - 8 Note 2 MAX. Unit ns ns ns DMAAKn low-level width <67> Note 2 Flyby transfer TCn output delay time (from BUSCLK) TCn output hold time (from BUSCLK) <69> tHKTC 2-cycle/flyby transfer <68> tDKTC 2-cycle/flyby transfer 2TBUS + wAS + wFW + wIC - 8 2 13 ns 2 13 ns Notes 1. Normal operation (DMAAKn output width = memory controller output) 2. The access is as follows. Transfer Source Internal data RAM Transfer Destination External memory/ internal instruction RAM External memory Internal data RAM Provided/none However, when the speculative read function is not provided, the following conditions apply. * BUSCLK = Internal system clock (fCLK) * External memory access wait setting = 0 Provided/none Speculative Read Function 3. When selecting a mode in which DMAAKn output width = memory controller output + 4TCPU Remarks 1. n = 0 to 3 2. TBUS = 1 x BUSCLK cycle 3. TCPU = 1 x internal system clock (fCLK) cycle 4. wAS = Number of address setup waits inserted by ASC register wFW = Number of data waits inserted by FWC register wIC = Number of idle states inserted by FIC register User's Manual U16031EJ4V1UD 921 CHAPTER 17 ELECTRICAL SPECIFICATIONS (a) Level mode (3/3) BUSCLK (output) <64> DMARQn (input) <63> <65> DMAAKn (output) <67> <66> <68> TCn (output) <69> Remarks 1. The minimum DMAAKn inactive time is as follows. Transfer mode Single transfer, single-step transfer Transfer source External memory/ external I/O on-chip peripheral I/O Transfer destination External memory/ external I/O on-chip peripheral I/O/ internal instruction RAM Internal data RAM Internal data RAM Internal data RAM External memory/ external I/O on-chip peripheral I/O/ internal instruction RAM External memory/ external I/O on-chip peripheral I/O Block transfer - - TCPU Internal data RAM 9TCPU 5TCPU 9TCPU 4TCPU Inactive time 2. n = 0 to 3 922 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (b) Mask mode (1/3) Parameter DMARQn setup time (to BUSCLK) DMARQn hold time 1 (from DMAAKn) DMARQn hold time 2 (from BUSCLK) Note 2 Symbol <63> <70> tSDRK tHKDR1 Conditions 2-cycle/flyby transfer 2-cycle/flyby transfer MIN. 8 To DMAAKn MAX. Unit ns ns <71> tHKDR2 2-cycle transfer Flyby transfer 0 0 0 0 0 0 3TBUS - 8 4TBUS - 8 Note 1 ns ns ns ns (DMAAKn = "H" sample) DMAAKn output delay time (from BUSCLK) DMAAKn output hold time (from BUSCLK) <66> tHKDA <65> tDKDA Note 3 2-cycle transfer Flyby transfer 2-cycle transfer Flyby transfer nTCPU + 13 13 nTCPU + 13 13 Note 4 Note 4 ns ns Notes 1. The second transfer request disable timing in single transfer. To BUSCLK: Since the DMAAKn is output asynchronously with BUSCLK, in accordance with the DMAAKn rising "H" sample prescription, if DMAAKn = "H" is output at the timing in which it cannot be sampled at the BUSCLK (setup time < 8 ns), +1TBUS is added. 2. Time to DMAAKn high level from BUSCLK after DMAAKn rises 3. The second DMA transfer request disable timing in single transfer. 4. n is as follows. CKM1 0 0 1 1 CKM0 0 1 0 1 fCLK/1 fCLK/2 fCLK/3 fCLK/4 BUSCLK Division Ratio to Internal System Clock (fCLK) n 1 2 3 4 Remarks 1. n = 0 to 3 2. TBUS = 1 x BUSCLK cycle 3. TCPU = 1 x internal system clock (fCLK) cycle User's Manual U16031EJ4V1UD 923 CHAPTER 17 ELECTRICAL SPECIFICATIONS (b) Mask mode (2/3) Parameter DMAAKn low-level width Symbol <67> tWDAL Conditions 2-cycle transfer Note 1 Note 3 MIN. 2TCPU - 8 6TCPU - 8 Note 2 Note 2 MAX. Unit ns ns ns Flyby transfer TCn output delay time (from BUSCLK) TCn output hold time (from BUSCLK) <69> tHKTC 2-cycle/flyby transfer <68> tDKTC 2-cycle/flyby transfer 2TBUS + wAS + wFW + wIC - 8 2 13 ns 2 13 ns Notes 1. Normal operation (DMAAKn output width = memory controller output) 2. The access is as follows. Transfer Source Internal data RAM Transfer Destination External memory/ internal instruction RAM External memory Internal data RAM Provided/none However, when the speculative read function is not provided, the following conditions apply. * BUSCLK = Internal system clock (fCLK) * External memory access wait setting = 0 Provided/none Speculative Read Function 3. When selecting a mode in which DMAAKn output width = memory controller output +4TCPU Remarks 1. n = 0 to 3 2. TBUS = 1 x BUSCLK cycle 3. TCPU = 1 x internal system clock (fCLK) cycle 4. wAS = Number of address setup waits inserted by ASC register wFW = Number of data waits inserted by FWC register wIC = Number of idle states inserted by FIC register 924 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (b) Masks mode (3/3) BUSCLK (output) <70> <71> DMARQn (input) <63> <65> DMAAKn (output) <67> <66> <68> TCn (output) <69> Remarks 1. The minimum DMAAKn inactive time is as follows. Transfer mode Single transfer, Single-step transfer Transfer source External memory/ external I/O on-chip peripheral I/O Transfer destination External memory/ external I/O on-chip peripheral I/O/ internal instruction RAM Internal data RAM Internal data RAM Internal data RAM External memory/ external I/O on-chip peripheral I/O/ internal instruction RAM External memory/ external I/O on-chip peripheral I/O Block transfer - - TCPU Internal data RAM 9TCPU 5TCPU 9TCPU 4TCPU Inactive time 2. n = 0 to 3 User's Manual U16031EJ4V1UD 925 CHAPTER 17 ELECTRICAL SPECIFICATIONS (c) Edge mode (1/3) Parameter DMARQn hold time DMARQn high-level time 1 (from DMARQn) DMARQn high-level time 2 (from DMAAKn) DMAAKn output delay time (from BUSCLK) DMAAKn output hold time (from BUSCLK) <66> tHKDA <65> tDKDA 2-cycle transfer Flyby transfer 2-cycle transfer Flyby transfer 0 0 0 0 nTCPU + 13 13 nTCPU + 13 13 Note Note Symbol <64> <72> tHKDR tWDRH1 Conditions 2-cycle/flyby transfer 2-cycle/flyby transfer MIN. 2TCPU 2TCPU MAX. Unit ns ns <73> tWDRH2 2-cycle/flyby transfer 0 ns ns ns ns ns Note n is as follows. CKM1 0 0 1 1 CKM0 0 1 0 1 fCLK/1 fCLK/2 fCLK/3 fCLK/4 BUSCLK Ratio to Internal System Clock (fCLK) n 1 2 3 4 Remarks 1. n = 0 to 3 2. TCPU = 1 x internal system clock (fCLK) cycle 926 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (c) Edge mode (2/3) Parameter Symbol tWDAL Conditions 2-cycle transfer Note 1 Note 3 MIN. 2TCPU - 8 6TCPU - 8 Note 2 MAX. Unit ns ns ns DMAAKn low-level width <67> Note 2 Flyby transfer TCn output delay time (from BUSCLK) TCn output hold time (from BUSCLK) <69> tHKTC 2-cycle/flyby transfer <68> tDKTC 2-cycle/flyby transfer 2TBUS + wAS + wFW + wIC - 8 2 13 ns 2 13 ns Notes 1. Time to DMAAKn high level from BUSCLKafter DMAAKn rises 2. The access is as follows. Transfer Source Internal data RAM Transfer Destination External memory/ internal instruction RAM External memory Internal data RAM Provided/none However, when the speculative read function is not provided, the following conditions apply. * BUSCLK = Internal system clock (fCLK) * External memory access wait setting = 0 Provided/none Speculative Read Function 3. Normal operation (DMAAKn output width = memory controller output) Remarks 1. n = 0 to 3 2. TBUS = 1 x BUSCLK cycle 3. TCPU = 1 x internal system clock (fCLK) cycle 4. wAS = Number of address setup waits inserted by ASC register wFW = Number of data waits inserted by FWC register wIC = Number of idle states inserted by FIC register User's Manual U16031EJ4V1UD 927 CHAPTER 17 ELECTRICAL SPECIFICATIONS (c) Edge mode (3/3) BUSCLK (output) <64> <72> DMARQn (input) <73> <67> <65> DMAAKn (output) <66> <68> TCn (output) <69> Remarks 1. The minimum DMAAKn inactive time is as follows. Transfer mode Single transfer, Single-step transfer Transfer source External memory/ external I/O on-chip peripheral I/O Transfer destination External memory/ external I/O on-chip peripheral I/O/ internal instruction RAM Internal data RAM Internal data RAM Internal data RAM External memory/ external I/O on-chip peripheral I/O/ internal instruction RAM External memory/ external I/O on-chip peripheral I/O Block transfer - - TCPU Internal data RAM 9TCPU 5TCPU 9TCPU 4TCPU Inactive time 2. n = 0 to 3 928 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (8) Bus hold timing (1/2) Parameter HLDRQ setup time (to BUSCLK) HLDRQ hold time (from BUSCLK) Delay time from BUSCLK to HLDAK HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus float Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Symbol <74> <75> <76> <77> <78> <79> <80> <81> tSHRK tHKHR tDKHA tWHQH tWHAL tDKCF tDHAC tDHQHA1 Note 1 Note 2 Note 3 Delay time from HLDRQ to HLDAK <82> tDHQHA2 Conditions MIN. 10 2 2 T + 12 T - 11 0 0 4T 3T 3T T 2T + 12 11 11 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns Notes 1. BUSCLK divided by 2 2. BUSCLK divided by 3 3. BUSCLK divided by 4 Remark T = tCYK User's Manual U16031EJ4V1UD 929 CHAPTER 17 ELECTRICAL SPECIFICATIONS (8) Bus hold timing (2/2) TI BUSCLK (output) <75> <74> HLDRQ (input) <76> <81> HLDAK (output) <78> <79> A0 to A25 (output) Address <80> Undefined <82> <76> <74> <75> <74> <77> TH TH TH TI T0 D0 to D31 (I/O) Data CSn (output) BCYST (output) IORD, RD (output) IOWR, WE/WR (output) Note (output) SDRAS, SDCAS (output) WAIT (input) Note UUWR/UUBE/UUDQM, ULWR/ULBE/ULDQM, LUWR/LUBE/LUDQM, LLWR/LLBE/LLDQM Remarks 1. Broken lines indicate high impedance. 2. n = 0 to 7 930 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (9) Interrupt timing (1/2) Parameter NMI high-level width NMI low-level width INTPCm0, INTPCm1 pin (m = 0 to 3) high-level width INTPCm0, INTPCm1 pin (m = 0 to 3) low-level width INTPa pin high-level width <87> tWIT1H When clock-through has been set When noise elimination has been set <86> tWITCL When clock-through has been set When noise elimination has been set Symbol <83> <84> <85> tWNIH tWNIL tWITCH When noise elimination has been set Conditions MIN. 500 500 (Number of set elimination clocks + 1)/(fX/4) + 10 1/(fX/4) x 2 + 10 (Number of set elimination clocks + 1)/(fX/4) + 10 1/(fX/4) x 2 + 10 clocks + 1)/(fX/4) + 10 ns ns ns ns ns MAX. Unit ns ns ns Noise elimination clock (Number of set elimination = fX/4 selected Noise elimination clock (Number of set elimination = fX/32 selected clocks + 1)/(fX/32) + 10 1/(fX/4) x 2 + 10 When clock-through Noise elimination clock has been set Note INTPa pin low-level width <88> tWIT1L When noise elimination has been set = fX/4 selected ns Noise elimination clock (Number of set elimination = fX/4 selected clocks + 1)/(fX/4) + 10 ns Noise elimination clock (Number of set elimination = fX/32 selected clocks + 1)/(fX/32) + 10 1/(fX/4) x 2 + 10 500 + 1/(fX/4) + 10 500 + 1/(fX/4) + 10 ns When clock-through Noise elimination clock has been set INTPb high-level width <89> INTPb low-level width <90> tWITPH tWITPL Note ns = fX/4 selected ns ns Both edge and level detection Both edge and level detection Note When clock-through has been set, do not select a noise elimination clock of fX/32. Remarks 1. The noise elimination clock and clock-through are set values of the NCWC0 to NCWC3, NCW10, and NCW11 registers. 2. fX: Main clock 3. a = 100, 101, 110, 111 b = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, L1 User's Manual U16031EJ4V1UD 931 CHAPTER 17 ELECTRICAL SPECIFICATIONS (9) Interrupt timing (2/2) <83> <84> NMI (input) <85> <86> INTPCm0, INTPCm1 (input) <87> <88> INTPa (input) <89> <90> INTPb (input) Remark m = 0 to 3 a = 100, 101, 110, 111 b = 10, 11, 21 to 25, 50 to 52, 65 to 67, D0 to D15, L0, L1 (10) Timer C timing Parameter TICn high-level width Symbol <91> tWTCH Conditions When noise elimination has been set When clock-through has been set TICn low-level width <92> tWTCL When noise elimination has been set When clock-through has been set (Number of set elimination clocks + 1)/ (fX/4) + 10 1/(fX/4) x 2 + 10 ns ns MIN. (Number of set elimination clocks + 1)/ (fX/4) + 10 1/(fX/4) x 2 + 10 ns MAX. Unit ns Remarks 1. n = 0 to 3 2. The noise elimination clock and clock-through are set values of the NCWC0 to NCWC3 registers. <91> <92> TICn (input) 932 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (11) Timer ENC1 timing Parameter TCLR1n, TCUD1n, TIUD1n pin high-level width Symbol <93> tWTENCH When noise elimination has been set Conditions Noise elimination clock = fX/4 selected Noise elimination clock = fX/32 selected When clock-through has been set TCLR1n, TCUD1n, TIUD1n pin low-level width <94> tWTENCL When noise elimination has been set Note MIN. (Number of set elimination clocks + 1)/(fX/4) + 10 (Number of set elimination clocks + 1)/(fX/32) + 10 1/(fX/4) x 2 + 10 (Number of set elimination clocks + 1)/(fX/4) + 10 (Number of set elimination clocks + 1)/(fX/32) + 10 1/(fX/4) x 2 + 10 MAX. Unit ns ns Noise elimination clock = fX/4 selected Noise elimination clock = fX/4 selected Noise elimination clock = fX/32 selected ns ns ns When clock-through has been set Note Noise elimination clock = fX/4 selected ns Note When clock-through has been set, do not select a noise elimination clock of fX/32. Remarks 1. n = 0, 1 2. The noise elimination clock and clock-through are the set values of the NCW10 and NCW11 registers. <93> TCLR1n (input) TCUD1n (input) TIUD1n (input) <94> User's Manual U16031EJ4V1UD 933 CHAPTER 17 ELECTRICAL SPECIFICATIONS (12) CSI30, CSI31 timing (1/3) (a) Master mode Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn setup time (to SCKn) SIn hold time (from SCKn) SIn hold time (from SCKn) SOn output delay time (from SCKn) SOn output delay time (from SCKn) SOn output hold time (from SCKn) SOn output hold time (from SCKn) <101> tHSKSO 0.5tCYSK1 - 5 0.5tCYSK1 - 5 <100> tDSKSO <99> tHSKSI Symbol <95> <96> <97> <98> tCYSK1 tWSK1H tWSK1L tSSISK Conditions Output Output Output MIN. 182 0.5tCYSK1 - 12 0.5tCYSK1 - 12 12 12 5 5 7 7 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns Remark n = 0, 1 (b) Slave mode Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn setup time (to SCKn) SIn hold time (from SCKn) SIn hold time (from SCKn) SOn output delay time (from SCKn) SOn output delay time (from SCKn) SOn output hold time (from SCKn) SOn output hold time (from SCKn) <101> tHSKSO tWSK1H tWSK1H <100> tDSKSO <99> tHSKSI Symbol <95> <96> <97> <98> tCYSK1 tWSK1H tWSK1L tSSISK Conditions Input Input Input MIN. 182 0.5tCYSK1 - 20 0.5tCYSK1 - 20 30 30 1.5T + 10 1.5T + 10 12 12 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns Remarks 1. n = 0, 1 2. T = fX/4 934 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS (12) CSI30, CSI31 timing (2/3) (c) Timing when CKPn and DAPn bits of CSIC3n register = 00 <95> <97> <96> SCKn (I/O) <98> <99> SIn (input) Input data <100> <101> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 1 (d) Timing when CKPn and DAPn bits of CSIC3n register = 01 <95> <97> <96> SCKn (I/O) <98> <99> SIn (input) Input data <100> <101> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 1 User's Manual U16031EJ4V1UD 935 CHAPTER 17 ELECTRICAL SPECIFICATIONS (12) CSI30, CSI31 timing (3/3) (e) Timing when CKPn and DAPn bits of CSIC3n register = 10 <95> <97> <96> SCKn (I/O) <98> <99> SIn (input) Input data <100> <101> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 1 (f) Timing when CKPn and DAPn bits of CSIC3n register = 11 <95> <97> <96> SCKn (I/O) <98> <99> SIn (input) Input data <100> <101> SOn (output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 1 936 User's Manual U16031EJ4V1UD CHAPTER 17 ELECTRICAL SPECIFICATIONS A/D Converter Characteristics (EVDD = AVDD = AVREFP = 3.0 to 3.6 V, EVSS = AVSS = AVREFM = 0 V) Parameter Resolution Overall error Note 1 Symbol - - - - - - - - tCONV tSAMP - - - - VWASN AIDD tWAIH tWAIL Conditions MIN. 10 TYP. MAX. Unit bit 0.49 1/2 2.00 3 x conversion clock Note 2 %FSR LSB Quantization error Conversion time Sampling time Zero-scale error Full-scale error Note 1 10 /16 0.49 0.49 4 4 s ns %FSR %FSR LSB LSB V mA ns ns - - Note 3 Note 1 Integral linearity error - - - - <105> <106> Differential linearity error Analog input voltage Note 3 AVREFM AVREFP 10 AVDD power supply current ADTRG high-level width ADTRG low-level width 500 500 Notes 1. Excluding quantization error (0.05%FSR). 2. The conversion clock indicates the number of clocks set by the ADM1 register. 3. Excluding quantization error (0.5LSB). Remark LSB: Least Significant Bit FSR: Full Scale Range %FSR indicates the ratio to the full-scale value. <105> <106> ADTRG (input) User's Manual U16031EJ4V1UD 937 CHAPTER 18 PACKAGE DRAWINGS 176-PIN PLASTIC LQFP (FINE PITCH) (24x24) A B 132 133 89 88 detail of lead end S P C D T R Q 176 1 45 44 L U F G H I M J K S N NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. S M ITEM A B C D F G H I J K L M N P Q R S T U MILLIMETERS 26.00.2 24.00.2 24.00.2 26.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.4 0.10.05 3 +4 -3 1.50.1 0.25 0.600.15 S176GM-50-UEU-1 938 User's Manual U16031EJ4V1UD CHAPTER 18 PACKAGE DRAWINGS 240-PIN PLASTIC FBGA (16x16) E wSB ZD ZE B A D 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V U T R P NM L K J HG F E D C B A INDEX MARK wSA A y1 S A2 S (UNIT:mm) ITEM D E w A A1 A2 DIMENSIONS 16.000.10 16.000.10 0.20 1.480.10 0.350.06 1.13 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.20 1.20 P240F1-80-GA3 y S e A1 M e b x y y1 ZD ZE b x S AB User's Manual U16031EJ4V1UD 939 CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS The V850E/ME2 should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Caution The recommended soldering conditions for the following products are undetermined. * PD703111AGM-10-UEU-A * PD703111AGM-13-UEU-A * PD703111AGM-15-UEU-A * PD703111AF1-13-GA3 * PD703111AF1-13-GA3-A * PD703111AF1-15-GA3 * PD703111AF1-15-GA3-A Remark Products with -A at the end of the part number are lead-free products. Table 19-1. Surface Mounting Type Soldering Conditions PD703111AGM-10-UEU: 176-pin plastic LQFP (fine pitch) (24 x 24) PD703111AGM-13-UEU: 176-pin plastic LQFP (fine pitch) (24 x 24) PD703111AGM-15-UEU: 176-pin plastic LQFP (fine pitch) (24 x 24) Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature: 250C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Note Exposure limit: 3days (after that, prebake at 125C for 20 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - IR50-203-3 Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Remark For soldering methods and conditions other than those recommended above, consult an NEC Electronics sales representative. 940 User's Manual U16031EJ4V1UD APPENDIX A REGISTER INDEX (1/13) Symbol ADCR0 to ADCR7 ADCR0H to ADCR7H ADIC ADM0 ADM1 ADM2 ADTS ASC BCC BCP BCT0 BCT1 BEC BHC BMC CC100 CC101 CC10IC0 CC10IC1 CC110 CC111 CC11IC0 CC11IC1 CCC00 CCC01 CCC0IC0 CCC0IC1 CCC10 CCC11 CCC1IC0 CCC1IC1 CCC20 CCC21 CCC2IC0 CCC2IC1 A/D conversion result registers 0H to 7H ADC 747 A/D conversion result registers 0 to 7 Name Unit ADC Page 747 Interrupt control register 83 A/D converter mode register 0 A/D converter mode register 1 A/D converter mode register 2 ADC trigger select register Address setup wait control register Bus cycle control register Bus cycle period control register Bus cycle type configuration register 0 Bus cycle type configuration register 1 Endian configuration register Cache configuration register Bus mode control register Capture/compare register 100 Capture/compare register 101 Interrupt control register 53 Interrupt control register 54 Capture/compare register 110 Capture/compare register 111 Interrupt control register 59 Interrupt control register 60 Capture/compare register C00 Capture/compare register C01 Interrupt control register 37 Interrupt control register 38 Capture/compare register C10 Capture/compare register C11 Interrupt control register 39 Interrupt control register 40 Capture/compare register C20 Capture/compare register C21 Interrupt control register 41 Interrupt control register 42 User's Manual U16031EJ4V1UD ADC ADC ADC ADC ADC BCU BCU BCU BCU BCU BCU BCU BCU Timer Timer INTC INTC Timer Timer INTC INTC Timer Timer INTC INTC Timer Timer INTC INTC Timer Timer INTC INTC 337 742 743 745 746 155 160 156 121 121 124 162 151 463 464 336 336 463 464 336 336 411 411 335 335 411 411 335 335 411 411 336 336 941 APPENDIX A REGISTER INDEX (2/13) Symbol CCC30 CCC31 CCC3IC0 CCC3IC1 CCC40 CCC41 CCC4IC0 CCC4IC1 CCC50 CCC51 CCC5IC0 CCC5IC1 CCR10 CCR11 CKC CKS CM100 CM101 CM10IC0 CM10IC1 CM110 CM111 CM11IC0 CM11IC1 CMD0 CMD1 CMD2 CMD3 CMDIC0 CMDIC1 CMDIC2 CMDIC3 COVF3IC0 COVF3IC1 CSC0 CSC1 CSI3IC0 CSI3IC1 CSIC30 Capture/compare register C30 Capture/compare register C31 Interrupt control register 43 Interrupt control register 44 Capture/compare register C40 Capture/compare register C41 Interrupt control register 45 Interrupt control register 46 Capture/compare register C50 Capture/compare register C51 Interrupt control register 47 Interrupt control register 48 Capture/compare control register 10 Capture/compare control register 11 Clock control register Clock source select register Compare register 100 Compare register 101 Interrupt control register 55 Interrupt control register 56 Compare register 110 Compare register 111 Interrupt control register 61 Interrupt control register 62 Compare register D0 Compare register D1 Compare register D2 Compare register D3 Interrupt control register 49 Interrupt control register 50 Interrupt control register 51 Interrupt control register 52 Interrupt control register 70 Interrupt control register 72 Chip area select control register 0 Chip area select control register 1 Interrupt control register 69 Interrupt control register 71 Clocked serial interface clock select register 30 User's Manual U16031EJ4V1UD Name Unit Timer Timer INTC INTC Timer Timer INTC INTC Timer Timer INTC INTC Timer Timer CG CG Timer Timer INTC INTC Timer Timer INTC INTC Timer Timer Timer Timer INTC INTC INTC INTC INTC INTC BCU BCU INTC INTC CSI30 Page 411 411 336 336 411 411 336 336 411 411 336 336 454 454 368 373 461 462 336 336 461 462 336 336 439 439 439 439 336 336 336 336 336 336 118 118 336 336 542 942 APPENDIX A REGISTER INDEX (3/13) Symbol CSIC31 CSIL30 CSIL31 CSIM30 CSIM31 DADC0 DADC1 DADC2 DADC3 DBC0 DBC1 DBC2 DBC3 DCHC0 DCHC1 DCHC2 DCHC3 DDA0H DDA0L DDA1H DDA1L DDA2H DDA2L DDA3H DDA3L DIFC DMAIC0 DMAIC1 DMAIC2 DMAIC3 DSA0H DSA0L DSA1H DSA1L DSA2H DSA2L DSA3H DSA3L DTFR0 Name Clocked serial interface clock select register 31 Transfer data length select register 30 Transfer data length select register 31 Clocked serial interface mode register 30 Clocked serial interface mode register 31 DMA addressing control register 0 DMA addressing control register 1 DMA addressing control register 2 DMA addressing control register 3 DMA transfer count register 0 DMA transfer count register 1 DMA transfer count register 2 DMA transfer count register 3 DMA channel control register 0 DMA channel control register 1 DMA channel control register 2 DMA channel control register 3 DMA destination address register 0H DMA destination address register 0L DMA destination address register 1H DMA destination address register 1L DMA destination address register 2H DMA destination address register 2L DMA destination address register 3H DMA destination address register 3L DMA interface control register Interrupt control register 65 Interrupt control register 66 Interrupt control register 67 Interrupt control register 68 DMA source address register 0H DMA source address register 0L DMA source address register 1H DMA source address register 1L DMA source address register 2H DMA source address register 2L DMA source address register 3H DMA source address register 3L DMA trigger factor register 0 User's Manual U16031EJ4V1UD Unit CSI31 CSI30 CSI31 CSI30 CSI31 DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC INTC INTC INTC INTC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Page 542 550 550 540 540 261 261 261 261 260 260 260 260 264 264 264 264 258 259 258 259 258 259 258 259 274 336 336 336 336 256 257 256 257 256 257 256 257 268 943 APPENDIX A REGISTER INDEX (4/13) Symbol DTFR1 DTFR2 DTFR3 DTOC DWC0 DWC1 FIC FWC ICC ICCH ICCL ICD IMR0 IMR0H IMR0L IMR1 IMR1H IMR1L IMR2 IMR2H IMR2L IMR3 IMR3H IMR3L IMR4 IMR4H IMR4L IMR5 IMR5H IMR5L INTF1 INTF2 DMA trigger factor register 1 DMA trigger factor register 2 DMA trigger factor register 3 DMA terminal count output control register Data wait control register 0 Data wait control register 1 DMA flyby transfer idle control register DMA flyby transfer wait control register Instruction cache control register Instruction cache control register H Instruction cache control register L Instruction cache data configuration register Interrupt mask register 0 Interrupt mask register 0H Interrupt mask register 0L Interrupt mask register 1 Interrupt mask register 1H Interrupt mask register 1L Interrupt mask register 2 Interrupt mask register 2H Interrupt mask register 2L Interrupt mask register 3 Interrupt mask register 3H Interrupt mask register 3L Interrupt mask register 4 Interrupt mask register 4H Interrupt mask register 4L Interrupt mask register 5 Interrupt mask register 5H Interrupt mask register 5L External interrupt falling edge specification register 1 External interrupt falling edge specification register 2 Name Unit DMAC DMAC DMAC DMAC BCU BCU BCU BCU BCU BCU BCU BCU INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC Page 268 268 268 267 153 153 161 157 165 165 165 166 337 337 337 337 337 337 337 337 337 337 337 337 337 337 337 337 337 337 341, 818 326, 343, 823 345, 828 347, 833 349, 841 350, 852 350, 852 350, 852 INTF5 INTF6 INTFAL INTFDH INTFDHH INTFDHL External interrupt falling edge specification register 5 External interrupt falling edge specification register 6 External interrupt falling edge specification register AL External interrupt falling edge specification register DH External interrupt falling edge specification register DHH External interrupt falling edge specification register DHL INTC INTC INTC INTC INTC INTC 944 User's Manual U16031EJ4V1UD APPENDIX A REGISTER INDEX (5/13) Symbol INTR1 INTR2 Name External interrupt rising edge specification register 1 External interrupt rising edge specification register 2 Unit INTC INTC Page 341, 818 326, 343, 823 345, 828 347, 833 349, 841 350, 852 350, 852 350, 852 169 340 146 146 123 378 460, 872 460, 872 420, 871 420, 871 420, 871 420, 871 339 379 336 336 335 335 335 335 335 335 815 335 335 820 335 335 335 335 INTR5 INTR6 INTRAL INTRDH INTRDHH INTRDHL IRAMM ISPR LBC0 LBC1 LBS LOCKR NCW10 NCW11 NCWC0 NCWC1 NCWC2 NCWC3 NRS OSTS OV1IC0 OV1IC1 OVCIC0 OVCIC1 OVCIC2 OVCIC3 OVCIC4 OVCIC5 P1 P1IC0 P1IC1 P2 P2IC1 P2IC2 P2IC3 P2IC4 External interrupt rising edge specification register 5 External interrupt rising edge specification register 6 External interrupt rising edge specification register AL External interrupt rising edge specification register DH External interrupt rising edge specification register DHH External interrupt rising edge specification register DHL Internal instruction RAM mode register In-service priority register Line buffer control register 0 Line buffer control register 1 Local bus sizing control register Lock register Noise elimination width setting register 10 Noise elimination width setting register 11 Noise elimination width setting register C0 Noise elimination width setting register C1 Noise elimination width setting register C2 Noise elimination width setting register C3 NMI reset status register Oscillation stabilization time select register Interrupt control register 57 Interrupt control register 63 Interrupt control register 31 Interrupt control register 32 Interrupt control register 33 Interrupt control register 34 Interrupt control register 35 Interrupt control register 36 Port 1 Interrupt control register 0 Interrupt control register 1 Port 2 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 INTC INTC INTC INTC INTC INTC BCU INTC BCU BCU BCU CPU Timer Timer Timer Timer Timer Timer INTC CG INTC INTC INTC INTC INTC INTC INTC INTC Port INTC INTC Port INTC INTC INTC INTC User's Manual U16031EJ4V1UD 945 APPENDIX A REGISTER INDEX (6/13) Symbol P2IC5 P5 P5IC0 P5IC1 P5IC2 P6 P6IC5 P6IC6 P6IC7 P7 PAH PAHH PAHL PAL PALH PALL PCD PCM PCS PCT PDH PDHH PDHL PDIC0 PDIC1 PDIC2 PDIC3 PDIC4 PDIC5 PDIC6 PDIC7 PDIC8 PDIC9 PDIC10 PDIC11 PDIC12 PDIC13 PDIC14 PDIC15 Interrupt control register 6 Port 5 Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Port 6 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Port 7 Port AH Port AHH Port AHL Port AL Port ALH Port ALL Port CD Port CM Port CS Port CT Port DH Port DHH Port DHL Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Interrupt control register 16 Interrupt control register 17 Interrupt control register 18 Interrupt control register 19 Interrupt control register 20 Interrupt control register 21 Interrupt control register 22 Interrupt control register 23 Interrupt control register 24 Interrupt control register 25 Interrupt control register 26 Interrupt control register 27 Interrupt control register 28 User's Manual U16031EJ4V1UD Name Unit INTC Port INTC INTC INTC Port INTC INTC INTC Port Port Port Port Port Port Port Port Port Port Port Port Port Port INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC Page 335 825 335 335 335 830 335 335 335 835 843 843 843 838 838 838 864 861 854 858 845 845 845 335 335 335 335 335 335 335 335 335 335 335 335 335 335 335 335 946 APPENDIX A REGISTER INDEX (7/13) Symbol PFC1 PFC2 PFC5 PFC6 PFC7 PFCALL PFCCM PFCCS PFCCT PFCDH PFCDHH PFCDHL PLIC0 PLIC1 PM1 PM2 PM5 PM6 PM7 PMAH PMAHH PMAHL PMAL PMALH PMALL PMC1 PMC2 PMC5 PMC6 PMC7 PMCAH PMCAHH PMCAHL PMCAL PMCALH PMCALL PMCCD PMCCM PMCCS Port 1 function control register Port 2 function control register Port 5 function control register Port 6 function control register Port 7 function control register Port AL function control register L Port CM function control register Port CS function control register Port CT function control register Port DH function control register Port DH function control register H Port DH function control register L Interrupt control register 29 Interrupt control register 30 Port 1 mode register Port 2 mode register Port 5 mode register Port 6 mode register Port 7 mode register Port AH mode register Port AH mode register H Port AH mode register L Port AL mode register Port AL mode register H Port AL mode register L Port 1 mode control register Port 2 mode control register Port 5 mode control register Port 6 mode control register Port 7 mode control register Port AH mode control register Port AH mode control register H Port AH mode control register L Port AL mode control register Port AL mode control register H Port AL mode control register L Port CD mode control register Port CM mode control register Port CS mode control register User's Manual U16031EJ4V1UD Name Unit Port Port Port Port Port Port Port Port Port Port Port Port INTC INTC Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Page 817 822 827 832 837 840 863 856 860 849 849 849 335 335 816 821 826 831 836 844 844 844 839 839 839 816 821 826 831 836 844 844 844 839 839 839 865 862 855 947 APPENDIX A REGISTER INDEX (8/13) Symbol PMCCT PMCD PMCDH PMCDHH PMCDHL PMCM PMCS PMCT PMDH PMDHH PMDHL PRC PRCMD PRM10 PRM11 PSC PSMR PWM0 PWM1 PWMC0 PWMC1 PWMH0 PWMH1 PWML0 PWML1 RFS1 RFS3 RFS4 RFS6 RSUMIC SCR1 SCR3 SCR4 SCR6 SESA10 SESA11 SESC0 SESC1 SESC2 Port CT mode control register Port CD mode register Port DH mode control register Port DH mode control register H Port DH mode control register L Port CM mode register Port CS mode register Port CT mode register Port DH mode register Port DH mode register H Port DH mode register L Page ROM configuration register Command register Prescaler mode register 10 Prescaler mode register 11 Power-save control register Power-save mode register PWM modulo register 0 PWM modulo register 1 PWM control register 0 PWM control register 1 PWM modulo register H0 PWM modulo register H1 PWM modulo register L0 PWM modulo register L1 SDRAM refresh control register 1 SDRAM refresh control register 3 SDRAM refresh control register 4 SDRAM refresh control register 6 Interrupt control register 89 SDRAM configuration register 1 SDRAM configuration register 3 SDRAM configuration register 4 SDRAM configuration register 6 Valid edge select register 10 Valid edge select register 11 Valid edge select register C0 Valid edge select register C1 Valid edge select register C2 User's Manual U16031EJ4V1UD Name Unit Port Port Port Port Port Port Port Port Port Port Port MEMC CPU Timer Timer CPU CPU PWM PWM PWM PWM PWM PWM PWM PWM MEMC MEMC MEMC MEMC INTC MEMC MEMC MEMC MEMC INTC INTC INTC INTC INTC Page 859 865 847 847 847 862 855 859 847 847 847 202 387 457 457 388 387 776 776 774 774 776 776 776 776 243 243 243 243 337 216 216 216 216 354, 455 354, 455 352, 418 352, 418 352, 418 948 APPENDIX A REGISTER INDEX (9/13) Symbol SESC3 SFA30 SFA31 SFDB30 SFDB30H SFDB30L SFDB31 SFDB31H SFDB31L SFN30 SFN31 SIRB30 SIRB30H SIRB30L SIRB31 SIRB31H SIRB31L SSCGC STATUS10 STATUS11 TMC0 TMC1 TMC10 TMC11 TMC2 TMC3 TMC4 TMC5 TMCC00 TMCC01 TMCC10 TMCC11 TMCC20 TMCC21 TMCC30 TMCC31 TMCC40 TMCC41 TMCC50 Valid edge select register C3 CSIBUF status register 30 CSIBUF status register 31 Transmit data CSI buffer register 30 Transmit data CSI buffer register 30H Transmit data CSI buffer register 30L Transmit data CSI buffer register 31 Transmit data CSI buffer register 31H Transmit data CSI buffer register 31L Transfer data number specification register 30 Transfer data number specification register 31 Receive data buffer register 30 Receive data buffer register 30H Receive data buffer register 30L Receive data buffer register 31 Receive data buffer register 31H Receive data buffer register 31L SSCG control register Status register 10 Status register 11 Timer C0 Timer C1 Timer control register 10 Timer control register 11 Timer C2 Timer C3 Timer C4 Timer C5 Timer mode control register C00 Timer mode control register C01 Timer mode control register C10 Timer mode control register C11 Timer mode control register C20 Timer mode control register C21 Timer mode control register C30 Timer mode control register C31 Timer mode control register C40 Timer mode control register C41 Timer mode control register C50 User's Manual U16031EJ4V1UD Name Unit INTC CSI30 CSI31 CSI30 CSI30 CSI30 CSI31 CSI31 CSI31 CSI30 CSI31 CSI30 CSI31 CSI30 CSI31 CSI31 CSI31 CG Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Page 352, 418 547 547 546 546 546 546 546 546 551 551 545 545 545 545 545 545 375 459 459 409 409 452 452 409 409 409 409 413 415 413 415 413 415 413 415 413 415 413 949 APPENDIX A REGISTER INDEX (10/13) Symbol TMCC51 TMCD0 TMCD1 TMCD2 TMCD3 TMD0 TMD1 TMD2 TMD3 TMENC10 TMENC11 TUM10 TUM11 UB0CTL0 UB0CTL2 UB0FIC0 UB0FIC1 UB0FIC2 UB0FIC2H UB0FIC2L UB0FIS0 UB0FIS1 UB0RX UB0RXAP UB0STR UB0TX UB1CTL0 UB1CTL2 UB1FIC0 UB1FIC1 UB1FIC2 UB1FIC2H UB1FIC2L UB1FIS0 UB1FIS1 UB1RX UB1RXAP UB1STR UB1TX Timer mode control register C51 Timer mode control register D0 Timer mode control register D1 Timer mode control register D2 Timer mode control register D3 Timer D0 Timer D1 Timer D2 Timer D3 Timer ENC10 Timer ENC11 Timer unit mode register 10 Timer unit mode register 11 UARTB0 control register 0 UARTB0 control register 2 UARTB0 FIFO control register 0 UARTB0 FIFO control register 1 UARTB0 FIFO control register 2 UARTB0 FIFO control register 2H UARTB0 FIFO control register 2L UARTB0 FIFO status register 0 UARTB0 FIFO status register 1 UARTB0 receive data register UARTB0 receive data register AP UARTB0 status register UARTB0 transmit data register UARTB1 control register 0 UARTB1 control register 2 UARTB1 FIFO control register 0 UARTB1 FIFO control register 1 UARTB1 FIFO control register 2 UARTB1 FIFO control register 2H UARTB1 FIFO control register 2L UARTB1 FIFO status register 0 UARTB1 FIFO status register 1 UARTB1 receive data register UARTB1 receive data register AP UARTB1 status register UARTB1 transmit data register User's Manual U16031EJ4V1UD Name Unit Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB UARTB Page 415 441 441 441 441 438 438 438 438 449 449 451 451 484 489 493 495 496 496 496 499 500 491 491 487 490 484 489 493 495 496 496 496 499 500 491 491 487 490 950 APPENDIX A REGISTER INDEX (11/13) Symbol UCKC UD1IC0 UD1IC1 UF0AAS UF0ADRS UF0AIFN UF0ASS UF0BC UF0BI1 UF0BI2 UF0BO1 UF0BO1L UF0BO2 UF0BO2L UF0CIE0 to UF0CIE255 UF0CLR UF0CNF UF0CS UF0DD0 to UF0DD17 UF0DEND UF0DMS0 UF0DMS1 UF0DSCL Name USB clock control register Interrupt control register 58 Interrupt control register 64 UF0 active alternative setting register UF0 address register UF0 active interface number register UF0 alternative setting status register USB function 0 buffer control register UF0 bulk in 1 register UF0 bulk in 2 register UF0 bulk out 1 register UF0 bulk out 1 length register UF0 bulk out 2 register UF0 bulk out 2 length register UF0 configuration/interface/endpoint descriptor registers 0 to 255 CG Unit Page 377 336 336 634 675 633 635 684 655 659 648 651 652 655 681 INTC INTC USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF UF0 CLR request register UF0 configuration register USB function 0 DMA channel select register UF0 device descriptor registers 0 to 17 USBF USBF USBF USBF 598 676 683 680 UF0 data end register UF0 DMA status 0 register UF0 DMA status 1 register UF0 descriptor length register UF0 device status register L UF0 EP0 length register UF0 EP0NAK register UF0 EP0NAKALL register UF0 EP0 read register UF0 EP0 status register L UF0 EP0 setup register UF0 EP0 write register UF0 endpoint 1 interface mapping register UF0 EP1 status register L UF0 endpoint 2 interface mapping register UF0 EP2 status register L UF0 endpoint 3 interface mapping register UF0 EP3 status register L USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF 628 624 625 679 667 643 589 591 642 668 644 646 636 669 637 670 638 671 UF0DSTL UF0E0L UF0E0N UF0E0NA UF0E0R UF0E0SL UF0E0ST UF0E0W UF0E1IM UF0E1SL UF0E2IM UF0E2SL UF0E3IM UF0E3SL User's Manual U16031EJ4V1UD 951 APPENDIX A REGISTER INDEX (12/13) Symbol UF0E4IM UF0E4SL UF0E7IM UF0E7SL UF0E8IM UF0E8SL UF0EN UF0ENM UF0EPS0 UF0EPS1 UF0EPS2 UF0FIC0 UF0FIC1 UF0GPR UF0IC0 UF0IC1 UF0IC2 UF0IC3 UF0IC4 UF0IDR UF0IF0 UF0IF1 UF0IF2 UF0IF3 UF0IF4 UF0IM0 UF0IM1 UF0IM2 UF0IM3 UF0IM4 UF0INT1 UF0INT2 UF0IS0 UF0IS1 UF0IS2 UF0IS3 UF0IS4 UF0MODC UF0MODS Name UF0 endpoint 4 interface mapping register UF0 EP4 status register L UF0 endpoint 7 interface mapping register UF0 EP7 status register L UF0 endpoint 8 interface mapping register UF0 EP8 status register L UF0 EPNAK register UF0 EPNAK mask register UF0 EP status 0 register UF0 EP status 1 register UF0 EP status 2 register UF0 FIFO clear 0 register UF0 FIFO clear 1 register UF0 GPR register UF0 INT clear 0 register UF0 INT clear 1 register UF0 INT clear 2 register UF0 INT clear 3 register UF0 INT clear 4 register UF0 INT & DMARQ register UF0 interface 0 register UF0 interface 1 register UF0 interface 2 register UF0 interface 3 register UF0 interface 4 register UF0 INT mask 0 register UF0 INT mask 1 register UF0 INT mask 2 register UF0 INT mask 3 register UF0 INT mask 4 register UF0 interrupt 1 register UF0 interrupt 2 register UF0 INT status 0 register UF0 INT status 1 register UF0 INT status 2 register UF0 INT status 3 register UF0 INT status 4 register UF0 mode control register UF0 mode status register User's Manual U16031EJ4V1UD Unit USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF USBF Page 639 672 640 673 641 674 592 596 600 602 603 626 627 630 617 618 619 620 621 622 677 678 678 678 678 612 613 614 615 616 663 665 604 606 608 609 611 631 632 952 APPENDIX A REGISTER INDEX (13/13) Symbol UF0SDS UF0SET UIFIC0 UIFIC1 UREIC0 UREIC1 URIC0 URIC1 US0BIC US1BIC US2BIC USP2IC USP4IC UTIC0 UTIC1 UTOIC0 UTOIC1 VSWC WAS UF0 SNDSIE register UF0 SET request register Interrupt control register 76 Interrupt control register 81 Interrupt control register 73 Interrupt control register 78 Interrupt control register 74 Interrupt control register 79 Interrupt control register 84 Interrupt control register 85 Interrupt control register 86 Interrupt control register 87 Interrupt control register 88 Interrupt control register 75 Interrupt control register 80 Interrupt control register 77 Interrupt control register 82 System wait control register Write access synchronization control register Name Unit USBF USBF INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC BCU BCU Page 597 599 336 336 336 336 336 336 337 337 337 337 337 336 336 336 337 110 150 User's Manual U16031EJ4V1UD 953 APPENDIX B INSTRUCTION SET LIST B.1 Conventions (1) Register symbols used to describe operands Register Symbol reg1 reg2 Explanation General-purpose registers: Used as source registers. General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher order 32 bits of multiplication results. bit#3 immX dispX regID vector cccc sp ep listX 3-bit data for specifying the bit number X bit immediate data X bit displacement data System register number 5-bit data that specifies the trap vector (00H to 1FH) 4-bit data that shows the conditions code Stack pointer (SP) Element pointer (r30) X item register list (2) Register symbols used to describe opcodes Register Symbol R r w d I i cccc CCCC bbb L S 1-bit data of a code that specifies reg1 or regID 1-bit data of the code that specifies reg2 1-bit data of the code that specifies reg3 1-bit displacement data 1-bit immediate data (indicates the higher bits of immediate data) 1-bit immediate data 4-bit data that shows the condition codes 4-bit data that shows the condition codes of Bcond instruction 3-bit data for specifying the bit number 1-bit data that specifies a program register in the register list 1-bit data that specifies a system register in the register list Explanation 954 User's Manual U16031EJ4V1UD APPENDIX B INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Input for General-purpose register System register Expand n with zeros until word length. Expand n with signs until word length. Read size b data from address a. Write data b into address a in size c. Read bit b of address a. Write c to bit b of address a. Execute saturated processing of n (n is a 2's complement). If, as a result of calculations, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H. result Byte Halfword Word + - ll x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Reflects the results in a flag. Byte (8 bits) Half word (16 bits) Word (32 bits) Addition Subtraction Bit concatenation Multiplication Division Remainder from division results Logical product Logical sum Exclusive OR Logical negation Logical shift left Logical shift right Arithmetic shift right Explanation (4) Register symbols used in execution clock Register Symbol i r l Explanation If executing another instruction immediately after executing the first instruction (issue). If repeating execution of the same instruction immediately after executing the first instruction (repeat). If using the results of instruction execution in the instruction immediately after the execution (latency). User's Manual U16031EJ4V1UD 955 APPENDIX B INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier (Blank) 0 X R No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. Explanation (6) Condition codes Condition Name (cond) V NV C/L Condition Code (cccc) 0000 1000 0001 OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) NC/NL 1001 CY = 0 No carry Not lower (Greater than or equal) Z/E 0010 Z=1 Zero Equal NZ/NE 1010 Z=0 Not zero Not equal NH H N P T SA LT GE LE GT 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0 (CY or Z) = 1 (CY or Z) = 0 S=1 S=0 - Not higher (Less than or equal) Higher (Greater than) Negative Positive Always (Unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Condition Formula Explanation 956 User's Manual U16031EJ4V1UD APPENDIX B INSTRUCTION SET LIST B.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Clock i ADD reg1,reg2 imm5,reg2 ADDI imm16,reg1,reg2 r r rr r0 01 11 0 RRRRR rrrrr010010iiiii r r rr r1 10 00 0 RRRRR iiiiiiiiiiiiiiii AND ANDI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 01 0 RRRRR r r rr r1 10 11 0 RRRRR iiiiiiiiiiiiiiii Bcond disp9 ddddd1011dddcccc if conditions are satisfied Note 1 then PCPC+sign-extend(disp9) When conditions are satisfied When conditions are not satisfied BSH reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll 1 1 1 x x 0 x x x x 3 3 3 GR[reg2]GR[reg2]AND GR[reg1] GR[reg2]GR[reg1]AND zero-extend(imm16) 1 1 1 1 1 1 0 0 x 0 x x GR[reg2]GR[reg2]+GR[reg1] GR[reg2]GR[reg2]+sign-extend(imm5) GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 r 1 1 1 l 1 1 1 CY OV S x x x x x x x x x Z SAT x x x Flags Note 2 Note 2 Note 2 1 1 1 wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) BSW reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR 1 1 1 0 wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24) CALLT imm6 0000001000iiiiii CTPCPC+2(return PC) CTPSWPSW adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Load-memory(adr,Halfword)) CLR1 bit#3, disp16[reg1] 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd 3 3 3 x 5 5 5 Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,0) Note 3 Note 3 Note 3 reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100100 adrGR[reg1] 3 3 3 x Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,0) Note 3 Note 3 Note 3 CMOV cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i wwwww011000cccc0 if conditions are satisfied then GR[reg3]sign-extended(imm5) else GR[reg3]GR[reg2] 1 1 1 cccc,reg1,reg2,reg3 r r rr r1 11 11 1 RRRR if conditions are satisfied else GR[reg3]GR[reg2] 1 1 1 wwwww011001cccc0 then GR[reg3]GR[reg1] CMP reg1,reg2 imm5,reg2 r r rr r0 01 11 1 RRRRR rrrrr010011iiiii 0000011111100000 0000000101000100 resultGR[reg2]-GR[reg1] resultGR[reg2]-sign-extend(imm5) PCCTPC PSWCTPSW PCDBPC PSWDBPSW 1 1 4 1 1 4 1 1 4 x x R x x R x x R x x R R CTRET DBRET 0000011111100000 0000000101000110 4 4 4 R R R R R User's Manual U16031EJ4V1UD 957 APPENDIX B INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Clock i DBTRAP 1111100001000000 DBPCPC+2 (returned PC) DBPSWPSW PSW.NP1 PSW.EP1 PSW.ID1 PC00000060H DI 0000011111100000 0000000101100000 DISPOSE imm5,list12 0000011001iiiiiL LLLLLLLLLLL00000 spsp+zero-extend(imm5 logically shift left by 2) GR[reg in list12]Load-memory(sp,Word) spsp+4 repeat 2 steps above until all regs in list12 is loaded imm5,list12,[reg1] 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+3 n+3 n+3 Note 4 Note 4 Note 4 Flags r 4 l 4 CY OV S Z SAT 4 PSW.ID1 1 1 1 n+1 n+1 n+1 Note 4 Note 4 Note 4 LLLLLLLLLLLRRRRR GR[reg in list12]Load-memory(sp,Word) Note 5 spsp+4 repeat 2 steps above until all regs in list12 is loaded PCGR[reg1] DIV reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 35 35 35 x x x x x x x x x x x x x x x wwwww01011000000 GR[reg3]GR[reg2]%GR[reg1] DIVH reg1,reg2 reg1,reg2,reg3 r r rr r0 00 01 0 RRRRR r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 GR[reg2]GR[reg2]/GR[reg1] Note 6 35 35 35 35 35 35 wwwww01010000000 GR[reg3]GR[reg2]%GR[reg1] DIVHU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 34 34 34 wwwww01010000010 GR[reg3]GR[reg2]%GR[reg1] DIVU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 34 34 34 wwwww01011000010 GR[reg3]GR[reg2]%GR[reg1] EI 1000011111100000 0000000101100000 HALT 0000011111100000 0000000100100000 HSW reg2,reg3 rrrrr11111100000 wwwww01101000100 JARL disp22,reg2 rrrrr11110dddddd ddddddddddddddd0 Note 7 JMP JR [reg1] disp22 00000000011RRRRR PCGR[reg1] 0000011110dddddd ddddddddddddddd0 Note 7 LD.B disp16[reg1],reg2 r r rr r1 11 00 0 RRRRR dddddddddddddddd LD.BU disp16[reg1],reg2 r r rr r1 11 10 b RRRRR dddddddddddddd1 Notes 8, 10 adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Byte)) adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Byte)) 1 1 1 1 Note 11 Note 11 PSW.ID0 1 1 1 Stop 1 1 1 GR[reg3]GR[reg2](15 : 0) ll GR[reg2] (31 : 16) 1 1 1 x 0 x x GR[reg2]PC+4 PCPC+sign-extend(disp22) 3 3 3 4 3 4 3 4 3 PCPC+sign-extend(disp22) 958 User's Manual U16031EJ4V1UD APPENDIX B INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Clock i LD.H disp16[reg1],reg2 rrrrr111001RRRRR ddddddddddddddd0 Note 8 LDSR reg2,regID rrrrr111111RRRRR 0000000000100000 Note 12 LD.HU disp16[reg1],reg2 r r rr r1 11 11 1 RRRRR ddddddddddddddd1 Note 8 LD.W disp16[reg1],reg2 r r rr r1 11 00 1 RRRRR ddddddddddddddd1 Note 8 MOV reg1,reg2 imm5,reg2 imm32,reg1 r r rr r0 00 00 0 RRRRR rrrrr010000iiiii GR[reg2]GR[reg1] GR[reg2]sign-extend(imm5) 1 1 2 1 1 2 1 1 2 adrGR[reg1]+sign-extend(disp16) GR[reg2]Load-memory(adr,Word) 1 1 Note 11 Flags r 1 l Note 11 CY OV S Z SAT adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Halfword)) 1 SR[regID]GR[reg2] Other than regID = PSW regID = PSW 1 1 1 1 1 1 x x x x x adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Halfword) 1 1 Note 11 00000110001RRRRR GR[reg1]imm32 iiiiiiiiiiiiiiii IIIIIIIIIIIIIIII MOVEA imm16,reg1,reg2 r r rr r1 10 00 1 RRRRR iiiiiiiiiiiiiiii GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 MOVHI imm16,reg1,reg2 r r rr r1 10 01 0 RRRRR iiiiiiiiiiiiiiii GR[reg2]GR[reg1]+(imm16 ll 016) 1 1 1 MULNote 22 reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR wwwww01000100000 GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 2 Note14 2 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 00 Note 13 GR[reg3] ll GR[reg2]GR[reg2]xsign-extend(imm9) 1 2 Note14 2 MULH reg1,reg2 imm5,reg2 r r rr r0 00 11 1 RRRRR rrrrr010111iiiii r r rr r1 10 11 1 RRRRR iiiiiiiiiiiiiiii GR[reg2]GR[reg2]Note 6xGR[reg1]Note 6 GR[reg2]GR[reg2] GR[reg2]GR[reg1] Note 6 1 1 1 1 1 1 2 2 2 xsign-extend(imm5) ximm16 MULHI imm16,reg1,reg2 Note 6 MULUNote 22 reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR wwwww01000100010 GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 2 Note 14 2 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 10 Note 13 GR[reg3] ll GR[reg2]GR[reg2]xzero-extend(imm9) 1 2 Note 14 2 NOP NOT NOT1 reg1,reg2 bit#3,disp16[reg1] 0000000000000000 Pass at least one clock cycle doing nothing. r r rr r0 00 00 1 RRRRR GR[reg2]NOT(GR[reg1]) 1 1 3 1 1 3 1 1 3 0 x x x 01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,Z flag) Note 3 Note 3 Note 3 reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100010 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,Z flag) 3 3 3 x Note 3 Note 3 Note 3 User's Manual U16031EJ4V1UD 959 APPENDIX B INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Clock i OR ORI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 00 0 RRRRR r r rr r1 10 10 0 RRRRR iiiiiiiiiiiiiiii PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5) list12,imm5, sp/immNote 15 0000011110iiiiiL LLLLLLLLLLLff011 imm16/imm32 Store-memory(sp-4,GR[reg in list12],Word) GR[reg in list 12]Load-memory(sp,Word) spsp+4 Note 16 repeat 2 step above until all regs in list12 is loaded PCGR[reg1] RETI 0000011111100000 if PSW.EP=1 0000000101000000 then PC EIPC PSW EIPSW else if PSW.NP=1 then else PC PC FEPC EIPC x x x x x x PSW FEPSW PSW EIPSW SAR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010100000 imm5,reg2 rrrrr010101iiiii GR[reg2]GR[reg2]arithmetically shift right by GR[reg1] GR[reg2]GR[reg2]arithmetically shift right by zero-extend (imm5) SASF cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then GR[reg2](GR[reg2]Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2]Logically shift left by 1) OR 00000000H SATADD reg1,reg2 imm5,reg2 SATSUB SATSUBI reg1,reg2 imm16,reg1,reg2 r r rr r0 00 11 0 RRRRR rrrrr010001iiiii r r rr r0 00 10 1 RRRRR r r rr r1 10 01 1 RRRRR iiiiiiiiiiiiiiii SATSUBR reg1,reg2 SETF cccc,reg2 r r rr r0 00 10 0 RRRRR rrrrr1111110cccc 0000000000000000 GR[reg2]saturated(GR[reg1]-GR[reg2]) If conditions are satisfied then GR[reg2]00000001H else GR[reg2]00000000H 1 1 1 1 1 1 x x x x x GR[reg2]saturated(GR[reg2]+GR[reg1]) GR[reg2]saturated(GR[reg2]+sign-extend(imm5) GR[reg2]saturated(GR[reg2]-GR[reg1]) GR[reg2]saturated(GR[reg1]-sign-extend(imm16) 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 0 1 1 1 0 Note17 Note17 Note17 Flags r 1 1 l 1 1 CY OV S 0 0 x x Z SAT x x GR[reg2]GR[reg2]OR GR[reg1] GR[reg2]GR[reg1]OR zero-extend(imm16) 1 1 n+1 n+1 n+1 Note 4 Note 4 Note 4 LLLLLLLLLLL00001 spsp-4 n+2 n+2 n+2 Note 4 Note 4 Note 4 4 4 4 R R R R R 960 User's Manual U16031EJ4V1UD APPENDIX B INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Clock i SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100000 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,1) SHL reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000011000000 imm5,reg2 rrrrr010110iiiii GR[reg2]GR[reg2] logically shift left by zero-extend(imm5) SHR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010000000 imm5,reg2 rrrrr010100iiiii GR[reg2]GR[reg2] logically shift right by zero-extend(imm5) SLD.B disp7[ep],reg2 rrrrr0110ddddddd adrep+zero-extend(disp7) GR[reg2]sign-extend(Load-memory(adr,Byte)) SLD.BU disp4[ep],reg2 r r r r r 0 0 0 0 1 1 0 d d d d adrep+zero-extend(disp4) Note 18 GR[reg2]zero-extend(Load-memory(adr,Byte)) SLD.H disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d adrep+zero-extend(disp8) Note 19 GR[reg2]sign-extend(Load-memory(adr,Halfword)) SLD.HU disp5[ep],reg2 r r r r r 0 0 0 0 1 1 1 d d d d adrep+zero-extend(disp5) Notes 18, 20 GR[reg2]zero-extend(Load-memory(adr,Halfword)) SLD.W disp8[ep],reg2 r r r r r 1 0 1 0 d d d d d d 0 adrep+zero-extend(disp8) Note 21 GR[reg2]Load-memory(adr,Word) SST.B reg2,disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte) SST.H reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d adrep+zero-extend(disp8) Note 19 Store-memory(adr,GR[reg2],Halfword) SST.W reg2,disp8[ep] r r r r r 1 0 1 0 d d d d d d 1 adrep+zero-extend(disp8) Note 21 Store-memory(adr,GR[reg2],Word) ST.B reg2,disp16[reg1] r r rr r1 11 01 0 RRRRR dddddddddddddddd ST.H reg2,disp16[reg1] adrGR[reg1]+sign-extend(disp16) Store-memory(adr,GR[reg2],Byte) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 9 Flags r 3 l 3 CY OV S Z SAT x 3 Note 3 Note 3 Note 3 3 3 3 x Note 3 Note 3 Note 3 GR[reg2]GR[reg2] logically shift left by GR[reg1] 1 1 1 x x x x 0 x x x x x x x x 1 1 1 0 GR[reg2]GR[reg2] logically shift right by GR[reg1] 1 1 1 0 1 1 1 0 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 Note 9 r r rr r1 11 01 1 RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword) Note 8 ST.W reg2,disp16[reg1] rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Store-memory (adr,GR[reg2], Word) Note 8 1 1 1 STSR regID,reg2 r r rr r1 11 11 1 RRRRR 0000000001000000 GR[reg2]SR[regID] 1 1 1 User's Manual U16031EJ4V1UD 961 APPENDIX B INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Clock i SUB SUBR SWITCH reg1,reg2 reg1,reg2 reg1 r r rr r0 01 10 1 RRRRR r r rr r0 01 10 0 RRRRR GR[reg2]GR[reg2]-GR[reg1] GR[reg2]GR[reg1]-GR[reg2] 1 1 5 r 1 1 5 l 1 1 5 CY OV S x x x x x x Z SAT x x Flags 00000000010RRRRR adr(PC+2) + (GR [reg1] logically shift left by 1) PC(PC+2) + (sign-extend (Load-memory (adr,Halfword)) logically shift left by 1 SXB reg1 00000000101RRRRR GR[reg1]sign-extend (GR[reg1] (7 : 0)) 1 1 1 SXH reg1 00000000111RRRRR GR[reg1]sign-extend (GR[reg1] (15 : 0)) 1 1 1 TRAP vector 00000111111iiiii 0000000100000000 EIPC EIPSW PC+4 (Return PC) PSW (40H to 4FH, 50H to 5FH) 4 4 4 ECR.EICC Exception code PSW.EP PSW.ID PC 1 1 00000040H (when vector is 00H to 0FH (exception code: 40H to 4FH)) 00000050H (when vector is 10H to 1FH (exception code: 50H to 5FH)) TST TST1 reg1,reg2 bit#3,disp16[reg1] r r rr r0 01 01 1 RRRRR resultGR[reg2] AND GR[reg1] 1 3 1 3 1 3 0 x x x x x x x x 11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit (adr,bit#3)) adrGR[reg1] Z flagNot (Load-memory-bit (adr,reg2)) GR[reg2]GR[reg2] XOR GR[reg1] GR[reg2]GR[reg1] XOR zero-extend (imm16) Note 3 Note 3 Note 3 reg2, [reg1] r r rr r1 11 11 1 RRRRR 0000000011100110 3 3 3 Note 3 Note 3 Note 3 XOR XORI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 00 1 RRRRR r r rr r1 10 10 1 RRRRR iiiiiiiiiiiiiiii 1 1 1 1 1 1 0 0 ZXB ZXH reg1 reg1 00000000100RRRRR GR[reg1]zero-extend (GR[reg1] (7 : 0)) 00000000110RRRRR GR[reg1]zero-extend (GR[reg1] (15 : 0)) 1 1 1 1 1 1 Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. dddddddd: Higher 8 bits of disp9. 4 if there is an instruction that rewrites the contents of the PSW immediately before. If there is no wait state (3 + the number of read access wait states). n is the total number of list12 load registers. (According to the number of wait states. Also, if there are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1) RRRRR: other than 00000. The lower halfword data only are valid. ddddddddddddddddddddd: The higher 21 bits of disp22. ddddddddddddddd: The higher 15 bits of disp16. According to the number of wait states (1 if there are no wait states). 10. b: bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). 962 User's Manual U16031EJ4V1UD APPENDIX B INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Higher 4 bits of imm9. 14. In the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0 (the higher 32 bits of the results are not written in the register), shortened by 1 clock. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: Load sp in ep. 01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18. r r r r r : Other than 00000. 19. ddddddd: Higher 7 bits of disp8. 20. dddd: Higher 4 bits of disp5. 21. dddddd: Higher 6 bits of disp8. 22. Do not make a combination that satisfies all the following conditions when using the "MUL reg1, reg2, reg3" instruction and "MULU reg1, reg2, reg3" instruction. Operation is not guaranteed when an instruction that satisfies the following conditions is executed. * Reg1 = reg3 * Reg1 reg2 * Reg1 r0 * Reg3 r0 User's Manual U16031EJ4V1UD 963 APPENDIX C REVISION HISTORY C.1 Major Revisions in This Edition (1/3) Page Throughout p. 18 p. 27 p. 28 pp. 40, 41 p. 48 p. 67 p. 68 p. 69 p. 71 p. 72 p. 72 p. 110 p. 113 p. 114 p. 121 p. 122 p. 149 p. 150 p. 151 p. 155 p. 158 p. 159 p. 170 p. 171 p. 184 p. 212 p. 215 p. 216 Deletion of PD703111AF1-10-GA3 Modification of the number of instructions in 1.2 Features Modification of description in 1.6.2 (3) RAM Addition of 1.6.2 (11) On-chip debug function (DCU) Modification of description in 2.2 Pin Status Deletion of a part of description in 2.3 (6) (b) (iv) REFRQ (Refresh request) Addition and change of Note in Table 3-2 System Register Numbers Addition of 3.2.2 (1) Interrupt status saving registers (EIPC, EIPSW) Addition of 3.2.2 (2) NMI status saving registers (FEPC, FEPSW) Addition of 3.2.2 (5) CALLT execution status saving registers (CTPC, CTPSW) Addition of 3.2.2 (6) Exception/debug trap status saving registers (DBPC, DBPSW) Addition of 3.2.2 (7) CALLT base pointer (CTBP) Addition of items to 3.4.9 System wait control register (VSWC) Addition of 3.4.11 Restriction on conflict between sld instruction and interrupt request Addition of 3.5 Cautions Addition of description to Caution in 4.4 (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) Modification of Note in 4.5.1 Number of access clocks Modification of Caution 2 and addition of Caution 3 in 4.5.6 (1) (b) Write buffer function Addition of Caution to 4.5.6 (2) Write access synchronization control register (WAS) Modification of Caution 2 and addition of Caution 4 in 4.6 (1) Bus mode control register (BMC) Addition of Caution to 4.7.1 (2) Address setup wait control register (ASC) Deletion of Caution in 4.7.2 External wait function Modification of description in Table 4-1 Bus Cycles in Which Wait Function Is Valid Modification of Caution 3 in 4.10.2 (2) Write operation Addition of description to (5) in 4.10.3 Cautions Addition of 4.15 Cautions Addition of 5.3.3 (1) Output of each address and connection of SDRAM Addition of 5.3.3 (2) Bank address output Addition of description to Caution 4 in 5.3.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) p. 226 p. 243 p. 250 p. 253 p. 264 Deletion of a part of description to 5.3.5 (2) SDRAM single write cycle Addition of Caution 2 to 5.3.6 (1) SDRAM refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6) Modification of description in 5.3.8 SDRAM initialization sequence Addition of 5.4 Cautions Modification of description in 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Description 964 User's Manual U16031EJ4V1UD APPENDIX C REVISION HISTORY (2/3) Page p. 267 p. 268 p. 287 p. 313 pp. 315 to 317 p. 318 p. 321 p. 362 p. 366 p. 366 p. 369 p. 371 p. 373 p. 379 p. 384 Addition of Caution to 7.1 Features Modification of Remark 1 in Table 7-1 Interrupt Source List Addition of Caution to 7.5.2 (2) Restore Modification of description in 7.8 Periods in Which CPU Does Not Acknowledge Interrupts Addition of 7.9 Cautions Modification of Caution 2 in 8.3.1 Clock control register (CKC) Addition of 8.3.1 (1) Notes on changing refresh interval Addition of description to 8.3.2 Clock source select register (CKS) Addition of Caution to 8.3.6 Oscillation stabilization time select register (OSTS) Modification of description in 8.5.2 (6) Serial communication (transmission or reception) transfer rate of UARTB: p. 386 p. 388 p. 392 p. 394 p. 395 p. 396 Addition of description to Note 3 to Figure 8-2 Power-Save Mode State Transition Diagram Addition of Note to 8.6.2 (3) Power-save control register (PSC) Addition of description to 8.6.3 (2) Release of HALT mode Deletion of a part of description in 8.6.4 (1) Setting and operation status Deletion of a part of description in Table 8-6 Operation Status in IDLE Mode Addition of Caution to 8.6.4 (2) (a) Release according to a non-maskable interrupt request signal or an unmasked maskable interrupt request signal p. 399 p. 400 Deletion of a part of description in Table 8-8 Operation Status in Software STOP Mode Addition of Caution to 8.6.5 (2) (a) Release according to a non-maskable interrupt request signal or an unmasked maskable interrupt request signal p. 405 p. 436 p. 457 p. 458 p. 466 p. 468 p. 477 p. 492 Addition of 8.8 Cautions Addition of description to 9.1.8 Cautions Modification of description in 9.3.5 (5) Prescaler mode registers 10, 11 (PRM10, PRM11) Modification of description in 9.3.5 (5) (b) UDC mode (T1CMDn bit of TUM1n register = 1) Addition of a part of description to 9.3.6 (1) (e) Timer output operation Modification of description in Table 9-8 List of Count Operations in UDC Mode Addition of 9.3.8 Cautions Modification of Caution 3 in 10.2.3 (5) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) (n = 0, 1) pp. 535, 536 p. 578 p. 588 p. 630 p. 685 Addition of description to 10.2.9 Cautions Addition of description to 10.3.7 Cautions Addition of description to 11.3.1 (2) (i) SET_INTERFACE() request Modification of description in 11.4.1 (32) UF0 GPR register (UF0GPR) Addition of Figure 11-10 Flowchart of Program When Host Is Disconnected and Then Reconnected User's Manual U16031EJ4V1UD Description Modification of description in 6.3.6 DMA terminal count output control register (DTOC) Modification of Caution 2 in 6.3.7 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) Modification of description of (a) in 6.5.1 (1) Timing of DMARQn and DMAAKn signals for 2-cycle transfer Addition of description to Caution in 6.14 Maximum Response Time for DMA Transfer Request Addition of descriptions to 6.15 Cautions 965 APPENDIX C REVISION HISTORY (3/3) Page p. 686 pp. 788 to 790 p. 820 p. 856 p. 857 p. 874 p. 888 p. 908 Description Addition of Figure 11-11 Flowchart of Program When Power Is Supplied Modification of description in 14.2 (2) Function when each port's pins are reset and registers that set the port/control mode Addition of description to 14.3.2 Port 2 Addition of description to 14.3.9 (2) (c) Port CS function control register (PFCCS) Addition of Figure 14-25 Timing When CSDCn Bit Is Set to 1 Addition of 14.7 Cautions Deletion of a part of description in 16.1.1 Debug function Modification of the MIN. value of the delay time from IOWR to address <40> (tDWRA) in AC Characteristics (4) (d) DMA flyby transfer timing (transfer from SRAM to external I/O) (1/2) in CHAPTER 17 ELECTRICAL SPECIFICATIONS p. 937 Addition of items ADTRG high-level width <105> (tWAIH) and ADTRG low-level width <106> (tWAIL), and timing chart to A/D Converter Characteristics in CHAPTER 17 ELECTRICAL SPECIFICATIONS Major revisions in modification version (U16031EJ4V1UD00) p. 20 pp. 21, 22 p. 940 Modification of 1.4 Ordering Information Addition of description to 1.5 Pin Configuration Addition of description to CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS 966 User's Manual U16031EJ4V1UD APPENDIX C REVISION HISTORY C.2 Revision History up to Previous Edition The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/8) Edition 2nd Major Revision from Previous Edition * Addition of the following product. Applied to: Throughout PD703111GM-15-UEU * Deletion of indication "under development" for the following products (developed) PD703111GM-10-UEU, 703111GM-13-UEU * Change of the following register name. PFCAL PFCALL Addition of execution time of 150 MHz products to minimum instruction execution time in 1.2 Features Addition of Note in 2.1 (2) Non-port pins Addition of description in 2.3 (1) (b) (vii) UCLK (USB clock) Modification of description in 2.3 (3) (b) (ii) DMAAK0, DMAAK1 (DMA acknowledge) Modification of description in 2.3 (5) (b) (ii) DMAAK2, DMAAK3 (DMA acknowledge) Addition of execution time of 150 MHz products to minimum instruction execution time in 3.1 Features Modification of default value in 3.2.1 (2) Program counter (PC) Modification of description in 3.4.7 Peripheral I/O registers Change of table of VSWC setting values in 3.4.9 System wait control register (VSWC) Modification of description in 4.2.1 Pin status during internal instruction RAM, internal data RAM, and peripheral I/O access Modification of description when BTn1 and BTn0 bits are set to 11 in 4.4.1 (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) Modification of table of number of access clocks in 4.5.1 Number of access clocks Addition to Cautions and modification of description in 4.5.6 (1) Line buffer control registers 0, 1 (LBC0, LBC1) Addition of Remark in 4.5.6 (1) (a) Speculative read function (read buffer function) Modification of description, addition of Note, and addition to Cautions in 4.5.6 (1) (b) Write buffer function Addition to Cautions in 4.7.1 (3) Bus cycle period control register (BCP) Modification of Cautions in 4.9.1 (1) Cache configuration register (BHC) Addition of (5) in 4.10.3 Cautions Addition of timing and modification of Notes in 4.11.6 (1) SDRAM (when read, latency = 2, no idle state insertion) Addition of timing and modification of Notes in 4.11.6 (2) SDRAM (when read, latency = 2, two idle states inserted, 32-bit bus width) Addition of timing and modification of Notes in 4.11.6 (3) SDRAM (when written) Addition of 4.14 Timing at Which T0 State Is Not Inserted Addition of timing and modification of Notes in Figure 5-9 SDRAM Single Read Cycle Addition of timing and modification of Notes in Figure 5-10 SDRAM Single Write Cycle CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION CHAPTER 4 BUS CONTROL FUNCTION CHAPTER 3 CPU FUNCTION CHAPTER 1 INTRODUCTION CHAPTER 2 PIN FUNCTIONS User's Manual U16031EJ4V1UD 967 APPENDIX C REVISION HISTORY (2/8) Edition 2nd Major Revision from Previous Edition Addition of timing and modification of Notes in Figure 5-11 SDRAM Access Timing Modification of Caution in 5.3.6 (1) SDRAM refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6) Modification of description in Table 5-1 Example of Interval Factor Settings Addition of internal instruction RAM in block diagram in 6.2 Configuration Addition to Cautions in 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to DSA3H) Addition to Cautions in 6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) Addition to Cautions in 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) Addition to Cautions in 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) Addition to Cautions and description in 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Addition to Cautions and description in 6.3.6 DMA terminal count output control register (DTOC) Addition to Cautions in 6.3.7 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) Addition of 6.3.7 (1) DMA request detection function Addition of Caution and Note and modification of description in 6.3.8 DMA interface control register (DIFC) Addition of timing and modification of Notes in Figure 6-12 Timing of 2-Cycle DMA Transfer (SDRAM SRAM) Addition of 6.5.1 (1) Timing of DMARQn and DMAAKn signals for 2-cycle transfer Addition of 6.5.1 (2) DMAAKn signal active width extension function Addition of 6.5.1 (3) Outline of 2-cycle transfer timing Modification of timing in Figure 6-19 Timing of DMA Flyby Transfer (External I/O SDRAM) Modification of timing in Figure 6-23 Timing of DMA Flyby Transfer (SDRAM External I/O) Modification of timing in Figure 6-24 Timing of DMA Flyby Transfer (External I/O SDRAM) Modification of description and addition to Caution in Table 6-5 Relationship Between Transfer Type and Transfer Object Addition of description in 6.8 Next Address Setting Function Addition of Cautions in 6.9 DMA Transfer Start Factors Modification of description in 6.13 Times Related to DMA Transfer Modification of description in 6.15 (3) Bus arbitration for CPU Addition of 6.15 (7) Read values of DSAn and DDAn registers Modification of Note in Figure 7-14 Pipeline Operation at Interrupt Request Acknowledgment (Outline) CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Applied to: CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 968 User's Manual U16031EJ4V1UD APPENDIX C REVISION HISTORY (3/8) Edition 2nd Major Revision from Previous Edition Modification of selection of SSCG output by PLLSEL pin and MDL-Selector Table (modulation period) in 8.1 Features Addition to Cautions and modification of description in 8.3.1 Clock control register (CKC) Modification of sample coding <2> for data setting sequence of clock source select register (CKS) in 8.3.2 Clock source select register (CKS) Modification of description in 8.3.3 SSCG control register (SSCGC) Addition of Caution in 8.3.4 USB clock control register (UCKC) Modification of oscillation stabilization time in 8.3.6 Oscillation stabilization time select register (OSTS) Addition to Notes in Table 8-1 Operation Status of Each Clock Modification of description in Table 8-2 Frequency List Addition of 8.5 Operating Clock Provisions Modification of oscillation stabilization time in Table 8-11 Counting Time Examples Addition to Caution in 9.1.5 (2) Timer mode control registers C01 to C51 (TMCC01 to TMCC51) Modification of Figure 9-7 TMC1 Compare Operation Example (Set/Reset Output Mode) Addition of noise elimination width when fX = 150 MHz in Table 9-6 Relationship Between NCW1n Register Set Value and Noise Elimination Width Addition of 9.3.7 (6) Overflow interrupt signal (INTOV1n) and underflow interrupt signal (INTUD1n) Modification of transfer rate in 10.2.1 Features Modification of description in 10.2.2 (10) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) (n = 0, 1) Addition of description in 10.2.2 (12) UARTBn transmit data register n (UBnTX) (n = 0, 1) Modification of Caution in 10.2.3 (3) UARTBn control register 2 (UBnCTL2) (n = 0, 1) Addition of description in 10.2.3 (4) UARTBn transmit data register (UBnTX) (n = 0, 1) Modification of description in 10.2.3 (5) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) (n = 0, 1) Addition and modification of description in 10.2.3 (6) UARTBn FIFO control register 0 (UBnFIC0) (n = 0, 1) Modification of description in 10.2.3 (7) UARTBn FIFO control register 1 (UBnFIC1) (n = 0, 1) Addition of description in 10.2.4 (5) (b) FIFO mode Addition of description in 10.2.5 (2) Pending mode/pointer mode Addition of Note in 10.2.5 (2) (a) (i) During transmission (writing to transmit FIFOn) Addition of Note in 10.2.5 (2) (a) (ii) During reception (reading from receive FIFOn) Addition of description in 10.2.6 (4) (c) (ii) Reception timeout interrupt (UBTITOn) (in FIFO mode only) Addition of value when fX = 150 MHz in Table 10-4 Baud Rate Generator Setting Data CHAPTER 10 SERIAL INTERFACE FUNCTION CHAPTER 10 SERIAL INTERFACE FUNCTION CHAPTER 9 TIMER/ COUNTER FUNCTION (REAL-TIME PULSE UNIT) Applied to: CHAPTER 8 CLOCK GENERATION FUNCTION User's Manual U16031EJ4V1UD 969 APPENDIX C REVISION HISTORY (4/8) Edition 2nd Major Revision from Previous Edition Addition of 10.2.8 Control flow Modification of description in Figure 10-22 Block Diagram of Clocked Serial Interfaces 30 and 31 Modification of description of Caution 2 in 10.3.3 (1) Clocked serial interface mode registers 30, 31 (CSIM30, CSIM31) Modification of description in 10.3.3 (2) Clocked serial interface clock select registers 30, 31 (CSIC30, CSIC31) Addition of description in 10.3.3 (3) Receive data buffer registers 30, 31 (SIRB30, SIRB31) Addition of description in 10.3.3 (4) Transmit data CSI buffer registers 30, 31 (SFDB30, SFDB31) Modification of description in 10.3.3 (5) CSIBUF status registers 30, 31 (SFA30, SFA31) Modification of example in Caution 2 in 10.3.4 (2) Baud rate Modification of description in Figure 10-25 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register), Transfer Direction: MSB First (DIRn Bit = 0 in CSIM3n Register) Modification of description in Figure 10-26 Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register), Transfer Direction: LSB First (DIRn Bit = 1 in CSIM3n Register) Deletion of description of 10.3.5 (7) Slave mode Modification of Figure 10-30 Slave Mode (CKPn and DAPn Bits = 00 in CSIC3n Register, CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register (Transfer Data Length: 8 Bits)) Modification of description in Figure 10-32 Continuous Mode Modification of description in 10.3.5 (11) Transmission mode Addition of description in 10.3.5 (12) Reception mode Deletion of description in 10.3.5 (16) (a) SCKn pin Modification of description in Table 10-8 Default Output Level of SCKn Pin Modification of description of (1) to (12) in 10.3.6 Usage Addition of Caution in 11.1 Overview Addition of items in Table 11-2 Correspondence Between Requests and Decoded Values Addition of description in 11.4.1 (3) UF0 EPNAK register (UF0EN) Deletion of description in 11.4.1 (9) UF0 EP status 1 register (UF0EPS1) Modification of description in 11.4.1 (11) UF0 INT status 0 register (UF0IS0) Modification of description in 11.4.1 (34) UF0 mode status register (UF0MODS) Modification of description in 11.4.3 (2) UF0 EP0 status register L (UF0E0SL) Modification of description in 11.4.3 (9) UF0 address register (UF0ADRS) Modification of description in 11.4.3 (10) UF0 configuration register (UF0CNF) Modification of description in 11.4.3 (11) UF0 interface 0 register (UF0IF0) Modification of description in 11.4.3 (12) UF0 interface 1 to 4 registers (UF0IF1 to UF0IF4) CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Applied to: CHAPTER 10 SERIAL INTERFACE FUNCTION 970 User's Manual U16031EJ4V1UD APPENDIX C REVISION HISTORY (5/8) Edition 2nd Major Revision from Previous Edition Modification of Caution 2 in 11.4.3 (14) UF0 device descriptor registers 0 to 17 (UF0DD0 to UF0DD17) Modification of Caution 2 in 11.4.3 (15) UF0 configuration/interface/endpoint descriptor registers 0 to 255 (UF0CIE0 to UF0CIE255) Modification of Caution in 11.4.4 (1) USB function 0 DMA channel select register (UF0CS) Deletion of Caution in Table 11-8 FW-Supported Standard Requests Modification of description in Figure 11-15 Automatically Processed Requests for Control Transfer Modification of description in Figure 11-20 CPUDEC Request for Control Transfer Modification of description in Figure 11-30 USB Connection Example Addition of value when fX = 150 MHz in Table 12-1 Setting of A/D Conversion Operation Time Addition of 12.9 How to Read A/D Converter Characteristics Table Modification of repeat frequency in 13.1 Features Modification of description in Figure 13-1 Block Diagram of PWM Unit Modification of description in 13.3 (1) PWM control registers 0 and 1 (PWMC0 and PWMC1) Modification of description in 13.4.2 (1) Setting for starting PWM operation Modification of description in Table 13-1 Repeat Cycle of PWMn Modification of Caution in 14.3.8 Port DH Modification of Caution and description on bit 0 in 14.3.8 (2) (c) Port DH function control register (PFCDH) Addition to Caution in 14.3.10 (2) (c) Port CT function control register (PFCCT) Addition of noise elimination width when fX = 150 MHz in Table 14-4 Relationship Between NCW1n Register Set Value and Noise Elimination Width Modification of value of program counter (PC) after reset in Table 15-2 Initial Value of CPU, Internal Data RAM, Internal Instruction RAM, and On-Chip Peripheral I/O After Reset Modification of description in 16.1.1 (7) Mask function CHAPTER 15 RESET FUNCTIONS CHAPTER 14 PORT FUNCTIONS CHAPTER 13 PWM UNIT CHAPTER 12 A/D CONVERTER Applied to: CHAPTER 11 USB FUNCTION CONTROLLER (USBF) CHAPTER 16 DEBUG FUNCTION (DCU) Addition of CHAPTER 17 ELECTRICAL SPECIFICATIONS (TARGET VALUES) CHAPTER 17 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 18 PACKAGE DRAWING CHAPTER 18 PACKAGE DRAWING Addition of CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS Addition to Note in B.2 Instruction Set (in Alphabetical Order) APPENDIX B INSTRUCTION SET LIST Addition of APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY User's Manual U16031EJ4V1UD 971 APPENDIX C REVISION HISTORY (6/8) Edition 3rd Major Revision from Previous Edition Deletion of the following product Applied to: Throughout PD703111 Addition of the following product PD703111A Addition of 240-pin plastic FBGA to 1.2 Features Addition of 240-pin plastic FBGA to 1.5 Pin Configuration Addition of Caution to 2.3 (6) (b) (i) WAIT Addition of Caution to 2.3 (6) (b) (iii) HLDRQ Modification of description in 2.3 (6) (b) (iv) REFRQ Modification of Figure 3-1 CPU Register Set Modification of Table 3-2 System Register Numbers Modification of 3.2.2 (2) Program status word (PSW) Addition of write access synchronization control register, modification of description of R/W in 3.4.7 Peripheral I/O registers Addition of description to 3.4.10 <1> Automatically branch to address 100000H after reset is cleared Addition of Caution 3 to 4.5.6 (1) Line buffer control registers 0, 1 (LBC0, LBC1) Modification of Cautions 2 and 3 in 4.5.6 (1) (b) Write buffer function Addition of 4.5.6 (2) Write access synchronization control register (WAS) Addition of Caution 3 to 4.6 (1) Bus mode control register (BMC) Addition of Caution 4 to 4.7.1 (2) Address setup wait control register (ASC) Modification of Caution 3 in 4.7.1 (3) Bus cycle period control register (BCP) Modification of Figure 4-6 Example of Wait Insertion Modification of Table 4-1 Bus Cycles in Which Wait Function Is Valid Addition of 4.9.7 Cautions Modification of description in 4.10.3 Cautions (5) Modification of 4.11.5 (1) SRAM (when read, without speculative read, no idle state insertion, BUSCLK = fCLK/2) Modification of 4.11.5 (2) SRAM (when read, with speculative read, no idle state insertion, BUSCLK = fCLK/2) Modification of 4.11.5 (3) SRAM (when written, two idle states inserted, BUSCLK = fCLK/2) Addition of description to 5.2.3 On-page/off-page judgment Addition of item to 5.3.1 Features Addition of Caution 3 to 6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) Addition of Caution 4 to 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) Modification of Cautions 1 and 5 and Caution on Enn bit in 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Addition of Caution 2 to 6.5.1 2-cycle transfer Modification of Figure 6-8 Timing of 2-Cycle DMA Transfer (SRAM External I/O) CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) CHAPTER 4 BUS CONTROL FUNCTION CHAPTER 3 CPU FUNCTION CHAPTER 1 INTRODUCTION CHAPTER 2 PIN FUNCTIONS 972 User's Manual U16031EJ4V1UD APPENDIX C REVISION HISTORY (7/8) Edition 3rd Major Revision from Previous Edition Modification of Figure 6-9 Timing of 2-Cycle DMA Transfer (SDRAM SRAM) Modification of Figure 6-10 Timing of 2-Cycle DMA Transfer (SRAM SDRAM) Modification of Figure 6-11 Timing of 2-Cycle DMA Transfer (SRAM External I/O): Without Speculative Read Modification of Figure 6-12 Timing of 2-Cycle DMA Transfer (SDRAM SRAM) (a) Without speculative read Modification of Figure 6-12 Timing of 2-Cycle DMA Transfer (SDRAM SRAM) (b) With speculative read, speculative read hit Addition of Caution to 6.5.2 Flyby transfer Addition of Notes 3 and 5 to Table 6-5 Relationship Between Transfer Type and Transfer Target Modification of description in 6.10 Terminal Count Output upon DMA Transfer End Modification of Figure 6-23 Example of Forcible Termination of DMA Transfer Modification of description in 6.13 Times Related to DMA Transfer Modification of 6.14 Maximum Response Time for DMA Transfer Request Addition of description to 6.15 (5) DMAAKn signal output Addition of Caution 3 to 8.6.5 (1) Setting and operation status CHAPTER 8 CLOCK GENERATION FUNCTION Addition of description to 9.1.5 (4) Noise elimination width setting registers C0 to C3 (NCWC0 to NCWC3) Modification of Figure 9-17 Timer ENC1 Block Diagram Addition of Caution 2 to 9.3.4 (2) Compare registers 100, 110 (CM100, CM110) Addition of Caution 2 to 9.3.4 (3) Compare registers 101, 111 (CM101, CM111) Addition of Caution 6 to 9.3.4 (4) Capture/compare registers 100, 110 (CC100, CC110) Addition of Caution 6 to 9.3.4 (5) Capture/compare registers 101, 111 (CC101, CC111) Addition of Cautions 2 and 3 to 9.3.5 (1) Timer unit mode registers 10, 11 (TUM10, TUM11) Addition of Caution to description of MSELn bit in 9.3.5 (1) Timer unit mode registers 10, 11 (TUM10, TUM11) Addition of Caution 2 to 9.3.5 (2) Timer control registers 10, 11 (TMC10, TMC11) Deletion of a part of Caution on RLEN1n bit in 9.3.5 (2) Timer control registers 10, 11 (TMC10, TMC11) Addition of Caution 4 to 9.3.5 (3) Capture/compare control registers 10, 11 (CCR10, CCR11) Addition of Caution 3 to 9.3.5 (4) Valid edge select registers 10, 11 (SESA10, SESA11) Addition of Caution 4 to 9.3.5 (5) Prescaler mode registers 10, 11 (PRM10, PRM11) Modification of Caution in 9.3.5 (6) Status registers 10, 11 (STATUS10, STATUS11) Addition of Note 1 to description on NCC1n, NCC0n bits in 9.3.5 (7) Noise elimination width setting registers 10, 11 (NCW10, NCW11) Modification of Table 9-6 Relationship Between NCW1n Register Set Value and Noise Elimination Width Modification of Figure 9-18 TMENC1n Block Diagram (During PWM Output Operation) CHAPTER 9 TIMER/ COUNTER FUNCTION (REALTIME PULSE UNIT) Applied to: CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) User's Manual U16031EJ4V1UD 973 APPENDIX C REVISION HISTORY (8/8) Edition 3rd Major Revision from Previous Edition Modification of Caution in 10.2.3 (3) UARTBn control register 2 (UBnCTL2) (n = 0, 1) Addition of Caution 3 to 10.2.3 (5) UARTBn receive data register AP (UBnRXAP), UARTBn receive data register (UBnRX) (n = 0, 1) Modification of description of CSITn bit in 10.3.3 (1) Clocked serial interface mode registers 30, 31 (CSIM30, CSIM31) Addition of Caution to description on CKS3n2 to CKS3n0 bits in 10.3.3 (2) Clocked serial interface clock select registers 30, 31 (CSIC30, CSIC31) Addition of Caution to Table 10-7 Conditions Under Which Data Can Be Transferred in Slave Mode Modification of description in 11.4.1 (4) UF0 EPNAK mask register (UF0ENM) Modification of description in 11.4.1 (32) UF0 GPR register (UF0GPR) Modification of Figure 11-21 Processing for Bulk Transfer (IN) (Endpoint1) Modification of Figure 11-30 USB Connection Example Addition of description to 11.7.8 (2) Detecting USB cable connection/disconnection Change of 14.3.9 (2) (c) Port CS function control register (PFCCS) Addition of description to 14.6.3 (1) Noise elimination width setting registers C0 to C3 (NCWC0 to NCWC3) Addition of Note 1 to description on NCC1n, NCC0n bits in 14.6.3 (2) Noise elimination width setting registers 10, 11 (NCW10, NCW11) Modification of Table 14-4 Relationship Between NCW1n Register Set Value and Noise Elimination Width Modification of Table 15-2 Initial Value of CPU, Internal Instruction RAM, Internal Data RAM, and On-Chip Peripheral I/O After Reset Modification of Table 16-1 Emulator Connector Pin Function CHAPTER 15 RESET FUNCTIONS CHAPTER 16 DEBUG FUNCTION (DCU) Modification of tWWRH in CHAPTER 17 (4) (c) Write timing (SRAM, external ROM, external I/O) Modification of tSAW, tSBSW, and tDIWRRD, Note, and timing diagram in CHAPTER 17 (4) (d) DMA flyby transfer timing (transfer from SRAM to external I/O) Modification of tSAW, tSBSW, tWWRH, and tDWRIRD, Note, and timing diagram in CHAPTER 17 (4) (e) DMA flyby transfer timing (transfer from external I/O to SRAM) Modification of CHAPTER 17 (6) (a) Read timing (SDRAM access) Modification of CHAPTER 17 (6) (b) Write timing (SDRAM access) Addition of CHAPTER 17 (6) (c) DMA flyby transfer timing (transfer from external I/O to SDRAM) Modification of tHKDR in CHAPTER 17 (7) (a) Level mode Modification of tDHQHA1 and tDHQHA2, and addition of Notes 1, 2, and 3 in CHAPTER 17 (8) Bus hold timing Addition of 240-pin plastic FBGA (16 x 16) package drawing to CHAPTER 18 PACKAGE DRAWINGS Addition of Caution to CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS CHAPTER 18 PACKAGE DRAWINGS CHAPTER 19 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX A NOTES APPENDIX A NOTES CHAPTER 17 ELECTRICAL SPECIFICATIONS CHAPTER 14 PORT FUNCTIONS CHAPTER 11 USB FUNCTION CONTROLLER (USBF) Applied to: CHAPTER 10 SERIAL INTERFACE FUNCTION 974 User's Manual U16031EJ4V1UD |
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